Memory Organizatiom

7/27/2019 Memory Organizatiom

1/39

Memory organization


2/39

Three categories: Internal processor memory Main memory Secondary memory Cache memory

The choice of a memory device to built amemory system depends on its properties.


3/39

Goal of memory organization

To provide high averg performance withlow averg cost per bit: Hierarchy of different memory devices Automatic storage allocation method Virtual memory concepts Efficient memory interface to provide higher

data transfer rate.


4/39

Memory-device characteristics Cost, c = C/S dollars/bit Access time, t A

Time spent to transfer a data to the output after receiving a read-request.

Access modes Random-access memory (RAM). Serial access Semirandom or direct access

Alterability Read-only, ROM PROM, EPROM Read-write, RAM


5/39

Permanence of storage Destructive read-out Non-destructive read-out Dynamic storage, refreshing Volatility.


6/39

Cycle time and data-transfer rate Bandwidth, b M =w/t M t A may not be equal to t M,cycle time.

Physical characteristics Physical size Storage density

Energy consumption Reliability: mean time to failure (MTTF)


7/39

Semiconductor RAMs

Static RAM Data remains as long as power is

supplied Read: add line active, data line

connected to sense amp Write: Add line active, data line

connected to data (low or high), V b isconnected to V 1/2

Dynamic RAM Data goes away within a millisecondeven power is there.

Refreshing is required

V a

Add line

V 1/2 =V b

Data

line

GNDdata

add

Bipolar static RAM cell

Dynamic MOS cell

R R


8/39

RAM organization

D e c o

d e r

Structure of 4x2-bit RAM.

1-dimensional memory

Access circuitry has a very significant effecton total cost of any memory unit. To reducethe cost the organization has two essentialfeatures: The storage cells are physically arranged in

rectangular arrays of cells. This is to facilitatelayout of the connections between the cellsand the access circuitry.

The memory address is partitioned into d components so that address A i of cell C i becomes a d -dimensional vector ( A i,1,Ai,2 , . . . ,

A i,d ) = A i . Each of the d parts of an addressword goes to a different address decoder anda different set of address drivers. A particular cell is selected by simultaneously activatingall d of its address lines.

V a

V b

WE X 0 X 1 Z 0 Z 1 CE

A1

A0


9/39

RAM Design

2mxn bit RAM IC. m represent no of

address lines. n represent word size. 2mxn

RAMm n

Address A Data D

CS WE OE

A RAM IC


10/39

RAM design contd.

Increasing word size. Increasing number of words. Given that Nxw bit RAM ICs, design Nxw

bit RAM, where N>N and/or w>w: Construct a pxq array of given RAM ICs,

where p=ceil{N/N}, q=ceil{w/w}

Each row stores N words Each column stores a fixed set of w bits from

every words


11/39

Increasing word size


12/39

Increasing number of words2mxw

RAM

2mxw RAM

1 t o 4 d

e c o d e

r

2mxw RAM

2mxw RAME

2

m+2 m w Address A

Chip select CS

WE

OE

WE

WE

WE

WE OE

OE

OE

OE CS

CS

CS

CS

w

2-bit are added atthe msb position of m+2 bit address


13/39

Structure of commercial 8Mx8 bitDRAM chip

23 address lines aremultuplexed into 13external addresslines.

Page mode Refresh cycle time is

64ms.

If one-row readoperation takes 90ns,then time needed torefresh the DRAM is90nsx8192 =0.737ms


14/39


15/39

Fast RAM interface . If we need to supply a faster external processor

with individually accessible n-bit words, then twobasic ways to increase data-transfer rate acrossits external interface by a factor of S Use a bigger memory words: design the RAM with aninternal memory word size of w=Sn bits. Sn bits is

used as one unit to be accessed in one memory cycletime T M.

Access more than one words at a time: partition the

RAM into S separate banks M 0, M1, , M S-1 , eachcovering part of the memory address space and eachprovided with its own addressing ckt. Need fast cktinside the RAM to assemble and disassemble thewords being accessed.


16/39

Both require fast p-to-s and s-to-p ckts atthe memory processor interface.

Normally S words produced or consumed

by the processor have consecutiveaddress. Their placement in the physicalmemory uses Interleaving technique.


17/39

Address Interleaving

Let X h, Xh+1 , be words that expected tobe accessed in sequence. They normallybe placed in consecutive memory

locations A i,Ai+1, in the RAM. Assign A i to bank M j if j=i (modulo S). If S = p 2, then least significant p bits of a

memory add immediately identify the memorybank where it belongs to.


18/39

Magnetic surface recording Surface of magnetic medium: ferric oxide If each track has a fixed capacity N words, and rotate at r

revolutions/s. Let n be the number of words/block, itsdata can be transferred in n/(rN) s. The aver latency is

1/(2r) s. If t s is avrg seek time, then time needs toaccess a block of data,t B = t s + 1/(2r) + n/(rN)

Magnetic disk drive Platters heads Tracks: Sectors: sector header, inter-sector gap Cylinders


19/39

Magnetic tape

Data is stored in longitudinal tracks. Older tapes had 9 parallel tracks. Now about 80tracks are used.

A single head can read/write all trackssimultaneously.

Along the tracks data are stored in blokcs.

Large gaps are inserted between adjucentblocks so that tape can be started andstopped between blocks.


20/39

Optical memories

CD-ROMs Bits are stored in 0.1 m wide pits and

lands. Access time is about 100ms, data transfer

rate is 3.6 MB/s (for 24x; x = 150KB/s)


21/39


22/39

Virtual memory

Memory hierarchy comprising of differentmemory devices appears to the user program asa single, large, directly addressable memory.

Automatic memory allocation, and efficient sharing Makes program independent of main memory space Achieve relatively low cost/bit and low access time.

A memory location is addressed by virtualaddress V, and it is necessary to map thisaddress to the actual physical address R, f :V R


23/39

Locality of references

Over short term, the address generated bya program tend to be localized and aretherefore predictable.

Page mode: info is transferred between M i and M i+1 as a block of consecutive words.Spatial locality.

Temporal locality: loop instru has highfrequency of references.


24/39

Address translation

Address assignment and translation iscarried out at diffent stage in life of a pgro By the programmer while writing the prog By the compiler during compilation By the loader at initial prog-load time By run-time memory management HW and/or

software Static translation, dynamic translation


25/39

Effective add, Base add, Displacement Aeff = B+D or A eff = B.D

Memory address table. Limit address, L i Bi


26/39

Dynamic address-trans system

TLB is referred toas an addresscache.

TLB

BV D

BR D

AV

AR

To memory system

Translation tablecontaining part of the memory map


27/39

Segments and page

Page - Basic unit of memory info for swappingpurpose in a multilevel memory system.

Page-frame Segments higher level info blocks corresponding to

logical entities e.g program or data sets. A segmentscan be translated into one or more pages.

Segment add, displacement. when a segment is notcurrently resident in the M 1 memory, it is entirelytransferred from the secondary memory M 2.

Segment table.


28/39

Burroughs B6500 segmentation

Each program has a segment called itsprogram reference table PRT, whichserves as it segment table.

Segment descriptor Intel 80x86 and pentium series have four

16 bit segment registers forming asegment table

dd l h


29/39

Two-stage add translation withsegment and page


30/39

Add trans. For pentium


31/39

Advantages of segmentation

Segment boundaries corresponds to naturalprogram and data boundaries. Because of their logical independence, a program segment can

be changed or recompiled at any time withoutaffecting other segments. Implementation of access rights and scopes of

program variables have been easy. Implementation of Stack and queues have been

easy as the segment can be of variable length.


32/39

pages

Fixed length block page table

Page add, displacement

Page fault. External fragmentation Internal fragmentation

Segments can be assigned over a non-contiguous area in the memory by the use of paging.


33/39

Effect of page size, S P

Storage utilization, effective data-transfer rate. If S S >> S P , the last page assigned to a segment

should contain S p/2 words.

No. of page table is approx. S S /S P words.Memory-space overhead with each segment

Space utilization, P

S P

S

S S S

2

)1(22

2 P S P

P S

S

S

S S S

S S

S S

S u


34/39

Optimum page size is obtained when S isminimized.

Optimum space utilization,

The effect of page size on hit ratio is complex When S p is small, H increases with S p . When S p exceeds a certain value, H begins to

decreases.

S

OPT

P

P

S

P

S S

S

S

dS

dS

2

021

2

S

OPT

S u

/211


35/39


36/39

Memory Allocation

Placement of info blocks in memory system iscalled memory allocation.

Demand swapping

Anticipatory swapping Thrashing For to level memory system, memory map

contains Occupied memory list for M 1 Available space list for M 1 Directory for M 2.


37/39

Non-preemptive allocation

Does not overwrite or move existingblocks to make room for incoming blocks.

Algorithm for paged segment. Algorithms for unpaged segment

First fit Best fit


38/39

Preemptive allocation

Rellocation is done in 2 ways: Relocate a block to a different postion within

M1 Deallocate a block from M1 memory using a

replacement policy Dirty blocks, clean blocks

Relocation by compaction Replacement policies to achieve max. H


39/39

Optimal replacement policy find theblock for replacement that has minimumchance to be referenced next time.

Address trace Two policies

FIFO LRU

Date post:	14-Apr-2018
Category:	Documents
Upload:	chilledkarthik
View:	218 times
Download:	0 times

Memory Organizatiom

Documents