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Methodology for HW/SW Co-verification in SystemC

Part ofHW/SW Codesign of

Embedded Systems Course (CE 40-226)

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Topics Introduction Design Flow Processor Models Implementation: 8051 Conclusion

Reference:

L. Semeria & A. Ghosh, “Methodology for Hardware/Software Co-Verification in C/C++”, in ASP-DAC 2000

Reference:

L. Semeria & A. Ghosh, “Methodology for Hardware/Software Co-Verification in C/C++”, in ASP-DAC 2000

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Methodology for HW/SWCo-verification in SystemC

Introduction

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Introduction Shrinking device sizes => all digital

components on a single chip Software is traditionally fully tested after

hardware is fabricated => long TTM Integrating HW and SW earlier in the

design cycle => better TTM Co-simulation involves

Simulating a processor model along with custom hw (usually described in HDL)

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Introduction (cont’d) Heterogeneous co-simulation

environments (C-VHDL or C-Verilog) RPC or another form of inter-process

communication between HW and SW simulators

High overhead due to high data transmission between the simulators

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Introduction (cont’d) Recently HW synthesis techniques from

C/C++ are more investigated Eliminates C to HDL translation for synthesis

=> higher productivity Reduces translation time Eliminated bugs introduced during this translation

Easier verification by re-using testbenches developed during

system validation phase enabling hw/sw co-verification and performance

estimation at very early stages of design

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Introduction (cont’d) In this paper, authors present

How hw/sw co-verification is performed in a C/C++ based environment

hw and sw are both described in C++ (SystemC)

Other C/C++ based approaches: PTOLEMY, and CoWare N2C,

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Methodology for HW/SWCo-verification in SystemC

Design Flow

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Design FlowFunctional Specification

of the system

Architectural Specification

Mapping

Refinement of Individual hw and sw blocks

Synthesis for hw blocksCompilation for sw blocks

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Methodology for HW/SWCo-verification in SystemC

Processor Models

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Processor Models Bus Functional Model (BFM) Instruction-Set Simulator (ISS)

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Bus Functional Model (BFM) Encapsulates the bus functionality of a

processor Can execute bus transactions on the

processor bus (with cycle accuracy) Cannot execute any instructions

Hence, BFM is an abstract model of processor that

can be used to verify how a processor interacts with its peripherals

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Bus Functional Model (cont’d)

SWSW HWHWHWSW

C/C++ BFM

At early stages of the design

In the later stages of the design

SWSW HWHWHWSW

ISS BFMAssembly

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Design of the BFM Is a SystemC module

Ports of the module correspond to the pins of the processor

Methods of the module provide a PI (programming interface) to the software/ISS

They depend on the type of communication between hw and sw

BFM functionality is modeled as a set of concurrent FSMs

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Memory-mapped IO Peripherals are located on a portion of

CPU address space BFM provided methods

void bfm_read_mem(sc_address, sc_data *, int) void bfm_write_mem(sc_address, sc_data, int)

SW (without ISS) calls these functions to access hw

When using ISS, SW calls device drivers. Device drivers are run in the ISS and at

proper time call these functions

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Interrupt-driven IO An interrupt controller is implemented in

BFM It is made sensitive to the CPU interrupt lines

In case of an interrupt, the corresponding ISR is called

ISRs are registered by these BFM methods void bfm_register_handler(sc_interrupt,

void (*handler)(sc_interrupt))

Interrupts may be masked/change behavior using configuration ports

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Configuration ports,Access to internal registers CPUs often have configuration ports for

Multiple modes of operation Multiple timers/serial modes Masked interrupts etc

BFM methods to access these registers void bfm_read_reg(sc_register, sc_data*, int nb) void vfm_write_reg(sc_register, sc_data, int nb)

BFM usually doesn’t model general-purpose registers of the CPU

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Timers and Serial Ports Normally, controllers for these timers

and serial ports are implemented within BFM

They are configured using configuration ports and registers Previously mentioned functions are used

They may issue interrupts to the CPU

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Performance Estimation Functions BFM keeps track of bus transactions

Can report number of clock cycles spent for each bus transaction

Reporting can be taken after each transaction or at the end of simulation

Tracking is enabled using void bfm_enable_tracing(int level)

level is used to define multiple levels of tracking

Even debug information can be produced by the BFM

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HW/SW Synchronization Normal BFM methods are blocking

SW execution is suspended until the bus transaction is done

This essentially serialized SW and HW execution A flag can be set in the BFM to make SW

execute in parallel with HW i.e. BFM methods return immediately

SW can wait for a specific number of clock cycles by calling

void bfm_idel_cycle(int)

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Processor Model Bus Functional Model (BFM) Instruction-Set Simulator (ISS)

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Instruction-Set Simulator

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Methodology for HW/SWCo-verification in SystemC

Implementation: 8051

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What we learned today

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Complementary notes:Assignments Take Assignment 8

Due Date: Saturday, Khordad 12th