Microelectronics Lab ELCT605
Spring 2014
Digital Lab Session #2
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
Outline
FPGAs - Xilinx
Design Flow and Xilinx ISE
Getting Started with Xilinx
XOR Example
Writing VHDL Code Creating a Test-Bench Behavioral Simulation Synthesis and RTL Schematic Spartan3E FPGA configuration
Lab Task: 2-to-4 Decoder
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
FPGA: Field Programmable Gate Array
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
Design Entry
Synthesis
Implementation
Simulation
View and Analysis
Design Flow Xilinx ISE 10.1
Schematic
Editor/ Verilog
File
XST
ISim
FPGA Editor
Design Flow and Xilinx ISE 10.1
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
Getting started with Xilinx ISE 10.1
Start Xilinx ISE from the desktop or start menu
Select File => New Project
Select a project location and project name (Hint: do not choose the Z:\ location)
Enter the Project/FPGA configuration information then press next, next, Finish.
XC3S500E-4FG320
Spartan 3E family
500 k equivalent logic gates
speed grade
-4 = standard
performance
320 pins
package type
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
Getting started with Xilinx ISE 10.1
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
Getting started with Xilinx ISE 10.1
Project name and selected
project properties.
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
Design Entry/ Specification
Write a VHDL code to describe a the following
circuit for the XOR gate
X=A B
A
B
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
1. Create a New Source
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
1. Create a New Source
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET ELCT605 Lab Session #2 Spring 2014
2. Specify the Inputs and Outputs
The New Source Wizard Summary window will be displayed. Click Finish.
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
3. Writing the VHDL Code
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
3. Writing the VHDL Code
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
4. Check Code Syntax
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
5.Create TestBench for Functional Simulation
Simulation has the aim of checking the functionality of the written VHDL code describing the required 2x4 decoder circuit.
To check whether the code performs the required function or not, input values are entered and the output of the simulation is checked out.
Entering the input values is done by means of a test Bench code or test bench waveform
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
5.Create TestBench for Functional Simulation
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
5.Create TestBench for Functional Simulation
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
5.Create TestBench for Functional Simulation
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
6. Entering Input Values
Save
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
7. Behavioral Simulation
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
8. Simulation Results
Reminder: Now we should check if the output is the same as we expect for each input case.
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
9. Synthesize to Get the Implemented Circuit
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
10. View RTL Schematic
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
11. Allocate inputs and outputs on FPGA
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
11. Allocate inputs and outputs on FPGA
Save
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
12. Implement Design and Configure Target Device
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
12. Implement Design and Configure Target Device
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
12. Implement Design and Configure Target Device
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
12. Implement Design and Configure Target Device
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
12. Implement Design and Configure Target Device
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
12. Implement Design and Configure Target Device
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
13. Program the FPGA
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
13. Program the FPGA
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
Lab Task
Write the VHDL code which describes a 2-
to-4 decoder with enable.
Test your code using Test-bench waveform and
show the Simulation results.
Download the decoder VHDL code on the
Spartan3E FPGA and verify its functionality
using input switches and output LEDs
ELCT605 Lab Session #2 Spring 2014
Dr M. Abd El Ghany
Eng. Salma Hesham
Faculty of IET
Lab Assignment
Write a 2-3 pages report about FPGAs discussing the following aspects:
FPGA structure
FPGA vendors and history
FPGA usage and applications
FPGAs versus ASICs designs
ELCT605 Lab Session #2 Spring 2014