Microwave and Optical Technology Letters Volume 51 Issue 11 2009 [Doi 10.1002_mop.24682] Meng Miao;...

8/12/2019 Microwave and Optical Technology Letters Volume 51 Issue 11 2009 [Doi 10.1002_mop.24682] Meng Miao; Cam N…

http://slidepdf.com/reader/full/microwave-and-optical-technology-letters-volume-51-issue-11-2009-doi-101002mop24682 1/6

for the antenna in free space is 90° (see Fig. 1). Therefore,

when testing the antenna in free-space, the antenna is placed

vertically to have omnidirectionality. This is a common feature of

handset antennas especially when the frequency of operation is

such that the total length of the ground plane is less than 0.5 ,

therefore, the radiation is similar to a half-wavelength dipole.

Pr ct D , r 1 S 112 (2)

4. CONCLUSIONS

A phantom human body using MoM has been proposed to evaluate

the influence on the human body to an FM embedded handset

antenna. The phantom human body uses a combination of four

tissues (blood, bone, muscles, and fat). Based on the simulationresults, the efficiency of the antenna is improved in 10 dB when

holding the phone. Experimental results are in very good agree-

ment. It seems that the particular holding position improves the

efficiency since the human body acts as a dielectric antenna which

is comparable to the wavelength.

REFERENCES

1. P.S. Hall, Y. Hao, H. Kawai, and K. Ito, Antennas and propagation for

body-centric wireless communications, ISBN: 9781580534932, Artech

House, Norwood, MA, 2006.

2. Z. Krupka, The effect of the human body on radiation properties of

small-sized communication systems, IEEE Trans Antennas Propag 16

(1968), 154–163.

3. J. Anguera, D. Aguilar, J. Verges, M. Ribo, and C. Puente, Handset

antenna design for FM reception. IEEE Antennas Propag Soc Int Symp

(2008).

4. D. Aguilar, J. Anguera, C. Puente, M. Ribo, Small handset antenna for

FM reception, Microwave Opt Technol Lett 50 (2008), 2677, 2683.

5. E.H. Newman, Small antenna location synthesis using characteristic

modes, IEEE Trans Antennas Propag AP-27 (1979), 530–531

6. Patent application no. WO 2007/128340.

© 2009 Wiley Periodicals, Inc.

INTEGRATED CMOS IMPULSE UWBRECEIVER FRONT-END DESIGN

Meng Miao and Cam NguyenDepartment of Electrical and Computer Engineering, Texas A&MUniversity, College Station, TX 77843-3128; Corresponding author:[email protected]

Received 26 February 2009

ABSTRACT: A single-chip broadband CMOS receiver front-end, inte-

grating a low-noise amplifier (LNA), a correlator, and a template pulse

generator, was investigated in nonsinusoidal time-domain environment

for possible use as an impulse-type ultra-wideband (UWB) receiver

front-end. Particularly, the CMOS LNA and the multiplier making up

the core component of the correlator were designed, fabricated, and

tested to verify operation in the UWB range. Time-domain results of the

integrated CMOS receiver front-end demonstrate its workability as a

receiver for nonsinusoidal UWB applications. © 2009 Wiley Periodicals,

Inc. Microwave Opt Technol Lett 51: 2590–2595, 2009; Published on-

line in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/

mop.24682

Key words: UWB receiver; LNA; multiplier; correlator; pulse genera-

tor; CMOS RFIC

1. INTRODUCTION

UWB time-domain impulse communication and radar systems use

(nonsinusoidal) ultra-short-duration pulses in the sub-nanosecondregime, instead of the more conventional continuous sinusoidal

waves, to transmit and receive information. One of the two main

subsystems of UWB systems is the impulse-type UWB receiver.

Its function is to receive UWB pulse signals through the receiving

antenna and down-convert these signals to baseband signals. Per-

haps the most important requirement for the impulse-type UWB

receiver is to recover the down-converted signal waveform in the

same form as the RF input signal across the UWB range of

3.1–10.6 GHz.

An attractive feature of the impulse-type UWB receiver is its

much simpler architecture when compared with conventional con-

tinuous-wave (CW) narrow- and wide-band receivers including

(multiband) MB-OFDM UWB receivers. The architecture consistsmainly of UWB LNA, correlator (which functions as a down-

conversion mixer), and template pulse generator. The correlator is

always an indispensable component for detection in impulse-type

UWB systems, no matter what kind of modulation technique is

used. Normally, the correlator consists of multiplier, integrator,

and sampling/holding (S/H) circuit. In impulse-type UWB receiv-

ers, there is a stringent requirement for the correlation speed: both

the multiplier and integrator must be fast enough to process each

receiving pulse. This brings great challenge to the correlator de-

sign. For wireless mobile devices, to reduce the cost and power

consumption, it is necessary to integrate all the UWB components

on a single chip. Considering the UWB frequency range across

3.1–10.6 GHz, this requirement represented a big challenge for

previously available VLSI technology. With the rapid develop-ment of CMOS technology scaling and advances of more accurate

RF models, CMOS is quickly becoming the preferred choice for

RFIC’s and suitable for single-chip UWB receivers.

In this article, we investigate the workability of an impulse-type

UWB receiver front-end consisting of UWB LNA, correlator, and

template pulse generator, fully integrated on a single chip using

0.18-m CMOS technology. Individual CMOS UWB LNA and

correlator circuits using optimized structures and patterned-

ground-shield (PGS) inductors were designed and implemented to

verify the design topology.

Figure 4 This measurement is the received signal power of the antenna. In the holding position the antenna has a better behavior than in the free space

situation. [Color figure can be viewed in the online issue, which is available at www.interscience.wiley.com]

2590 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 51, No. 11, November 2009 DOI 10.1002/mop



2. IMPULSE-TYPE UWB LNA

The impulse UWB LNA should exhibit the performance of not

only good input matching, flat gain, low noise figure (NF), and low

power consumption over the entire UWB bandwidth, as for con-

ventional broadband CW LNA, but also good linearity across the

UWB range for impulse applications. Good linearity allows the

LNA to reproduce faithfully the waveform of input UWB pulse

signals which is critically needed for impulse UWB systems. There

are many different options for the design of high-frequency wide-

band amplifiers depending on requirements and applications. Con-

sidering the NF, power dissipation, and die area, the cascoded

common-source inductively degenerated LNA, with extended ul-

tra-wideband ladder matching network, was selected to form the

impulse-type UWB LNA [1, 2]. The schematic of this LNA is

shown in Figure 1(a). The LNA was implemented using Jazz

0.18-m RFCMOS process [3] with the output buffer included to

drive the external 50- load for facilitating measurement.

The initial component parameters of the third-order Chebyshev

bandpass filter, as shown in Figure 1(a), was determined using the

module Filter Design Guide of ADS [4]. These components were

later replaced with on-chip MIM capacitors and optimized spiral

inductors to achieve a fully integrated LNA structure. To achieve

a flat gain over the whole UWB band, the shunt-peaking topology[1] was also used. For the noise performance of the LNA, the loss

associated with the input network and the noise from the ampli-

fying component were considered. For the input network, the MIM

capacitors have much higher quality factor (Q) than those of the

on-chip spiral inductors. To reduce the noise contribution from the

inductors, the structure of the inductors were optimized with EM

simulation and PGS topology to achieve the highest Q for the

specific inductance value.

The picture of the fabricated CMOS LNA is shown in Figure

1(b) with an overall size of 0.88 mm 0.7 mm including on-wafer

RF and DC-bias pads. All the measurements were performed on

wafer. Figure 2(a) presents the gain performance of the LNA

including the buffer stage. A maximum gain of 12.4 dB was

achieved over the band. Across the 3-dB bandwidth of 2.6–9.8

GHz, a minimum gain of 9.4 dB was achieved. The LNA achieves

relatively flat gain with the help of the shunt-peaking topology, as

expected. Parasitic capacitance from the output buffer, which was

not fully considered during the simulation, caused the gain degra-

dation by the shunt-peaking inductor load at the high-frequency

end. On-wafer time-domain measurement was also performed with

a digitizing oscilloscope and is shown in Figure 2(b). The input

Figure 1 (a) Schematic of the impulse UWB LNA. (b) Photograph of the LNA chip. [Color figure can be viewed in the online issue, which is available

at www.interscience.wiley.com]

Figure 2 (a) Power gain of the UWB LNA with buffer. (b) LNA performance in time-domain. [Color figure can be viewed in the online issue, which is

available at www.interscience.wiley.com]

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 51, No. 11, November 2009 2591



signal is a monocycle pulse, with a 3-dB pulse width of 150 ps and

peak-to-peak amplitude of 0.1 V, generated by a commercial pulse

generator. The measured output pulse has a peak-to-peak voltage

of 0.3 V with almost symmetric pulse shape and relatively small

ripple. When compared with the simulated result, there is some

pulse-width expansion because of the gain roll-off at the high-

frequency end. Nevertheless, the output signal demonstrates the

high signal fidelity of the LNA, making it suitable for impulse

UWB applications.

3. UWB CORRELATOR DESIGN

In a simplest topology, the impulse UWB receiver front-end is

only composed of a wideband LNA, a wideband correlator, and a

high frequency analog-to-digital converter (ADC) [5]. The basic

function of the correlator is to convert the received RF signal from

the LNA to baseband for detection. The correlator normally con-

sists of a multiplier followed by an integrator. The two inputs to

the correlator, or the multiplier, are the input pulse signal from the

LNA and its template pulse signal generated on the chip. The

received pulse signal is correlated with the local template pulse

during a certain period, and its output is sampled and held to detect

whether there is a signal in the observing window.

The correlator can be implemented either in analog or digital

format. Considering the UWB bandwidth and power efficiency,analog correlator is the preferred choice. It can process signals in

real time and provide a continuous output at low frequency, and

thereby can remove the need of special requirements for the ADC

in the receiver [6]. Analog correlators are therefore well suited for

UWB receiver front-end implementation, where the analog multi-

plier is required to have a good linearity for low signal distortion.

The correlated input signal is integrated with the local template

signal over the pulse duration and to produce a certain output

voltage. The cross-correlation function can be expressed as:

f t t 0

t t 0T

RFt LOt dt (1)

where LOt is the local template signal, RFt is the input RF

signal, and T is the integration period.

In UWB receiver design, the multiplier is required to have widebandwidth up to 10.6 GHz to assure that the output waveform

preserves the input pulse shape. Most of the published CMOS

analog multipliers can only operate at low frequencies [7–10]. In

this section, an UWB four-quadrant multiplier is introduced as

shown in Figure 3(a), which can be used for the correlator of UWB

receivers.

3.1. DC Analysis

The multiplier schematic is based on the transconductor multiplier

structure proposed in [11]. The central component of this four-

quadrant multiplier is the CMOS programmable transconductors.

As a current-mode element, it converts the input voltage signal into

differential current to realize the multiplication.

The structure, as seen in Figure 3(a), is differential; hence, the

even-order terms generated by the nonlinear components are can-

celled, thereby enhancing the linearity of the multiplier. To reduce

the leakage of the input RF signal to the output, a pair of NMOS

transistors is inserted between the outputs of the transconductor

M 5– M 8 and the multiplier output. To compensate the gain roll-off

at high frequencies, the shunt-peaking topology is used as in the

foregoing UWB LNA design. Two inductors L1 and L2 with

optimized values are added in series with the load resistors at the

output (drain of M 9 and M 10 ), resulting in improved gain perfor-

mance at the high-frequency end and wide bandwidth. Two

source-follower buffers are also included to facilitate the output

signal measurement.

As shown in Figure 3(a), the RF signal x enters the lowerbranches, which operate in the linear region through the bias

voltage of X . Although for the upper branches used for the LO

template signal y, operation in saturation region is achieved when

proper DC bias voltage Y is provided. Using a large signal model,

the current flowing through each of the lower branches can be

expressed as [12, 13]

Figure 3 (a) Schematic of proposed multiplier. (b) Simplified small-signal equivalent circuit

Figure 4 (a) Frequency response for dominant pole. (b) Frequency response with shunt-peaking inductor effect. [Color figure can be viewed in the online

issue, which is available at www.interscience.wiley.com]




I i K X x V tn

V dsi

2 V dsi (2)

where K nC ox

W

L with n being the mobility, C ox being the

oxide capacitance, and W and L being the gate width and length,respectively, V tn is the NMOS threshold voltage, and V dsi is the

drain-source voltage of the i-th MOS transistor.

Assuming all the sizes of the transistors are equal, the final

output current can be simplified as [13]

I o 2Kx V ds y 2Kx V ds y 4Kxy (3)

Hence, the multiplication function is achieved, and the correspond-

ing output voltage of the multiplier can be expressed as

V o I o Z o 4KxyZ o (4)

3.2. AC Analysis

Figure 3(b) shows the simplified small-signal equivalent circuitused for bandwidth analysis. The transconductor is assumed to be

an ideal current source with the parasitic capacitance C at its

output. The output resistance is omitted because of its much larger

value. To improve the bandwidth, the shunt-peaking topology is

used, where the output load resistance is in series with the inductor

to compensate the gain roll-off at the high frequency end. The

parasitic capacitance associated with the source node could be

large, because three transistors are connected to the same node,

thus producing a dominant pole as discussed in [13]. The dominant

and nondominant poles are separated from each other with the

dominant pole p1 around 2.2 GHz and nondominant pole p2

much higher than p1. Under the condition that the dominant pole

p1 can be cancelled by the zero z, the bandwidth of the multiplier

will be increased dramatically, hence the shunt-peaking topology

effectively improve the bandwidth performance.

3.3. Fabrication and Results

The layout of the multiplier structure fabricated with the Jazz

0.18-m CMOS process was arranged symmetrically to reduce

potential unbalance caused by nonsymmetric structure. The octag-

onal-shape inductors were optimized to achieve constant induc-

tance over the frequency range from 3.1 to 10.6 GHz.

For frequency-response calculation, the RF and LO ports were

only fed with DC signals, while the input signal was directly fed

to the source node. Without the shunt-peaking inductor and load

capacitor at the output, the frequency response of the multiplier is

shown in Figure 4(a). The 3-dB bandwidth in this case is around

2 GHz. An additional 100-pf capacitance was also connected to thesame source node for comparison purpose, and the bandwidth

reduced to about 1 GHz as seen in Figure 4(a). Figure 4(b)

compares the frequency response with and without the output

buffer when the shunt-peaking inductors are used. It is obvious that

after the inductor of around 30 nH was included, the bandwidth

was increased to 10 GHz, indicating that the pole-zero cancellation

topology was really in effect. In the case where the buffer was

included in the output of the multiplier, the simulation result

indicates that the bandwidth of the multiplier is reduced to 7 GHz.

Figure 5 (a) Photograph of the fabricated multiplier. (b) Conversion gain and RF return loss with IF frequency of 10 MHz, LO power of 1 dBm, and

RF power of 20 dBm. [Color figure can be viewed in the online issue, which is available at www.interscience.wiley.com]

Figure 6 (a) Block diagram of the receiver front-end. (b) Layout of the proposed receiver front-end. [Color figure can be viewed in the online issue, which

is available at www.interscience.wiley.com]




This bandwidth reduction is due to the extra capacitive loading

from the buffer.

Figure 5(a) shows the fabricated multiplier chip with size of 1

mm 0.7 mm including RF and DC bias pads for on-wafer

measurement purpose. On-wafer RF probes were used on the RF

and LO ports, while the output ports were measured through

off-chip with package.The measured and simulated conversion gain and RF-port

return loss are shown in Figure 5(b), where the output frequency is

fixed to 10 MHz and the LO power is 1 dBm. The measured

conversion gain is more than 7 dB over the band of 3–10 GHz,

including the output buffer effects. The difference between the

measured and simulated conversion gain is caused by the parasitic

resistive loss from the shunt-peaking inductor and buffer and by

the parasitic capacitor from the buffer. Over the band of 3–10

GHz, measured return loss of more than 10 dB is achieved.

4. IMPULSE UWB RECEIVER FRONT-END

An impulse UWB receiver front-end was investigated for possible

use in impulse UWB systems by integrating the designed template

tunable pulse generator [14], LNA, and multiplier. Figure 6 shows

this UWB receiver front-end. To simulate the time domain re-

sponse, two monocycle pulses with the same pulse width of 0.2 ns

but different amplitudes were used. The pulse with smaller ampli-

tude was applied to the RF input of the multiplier through the

LNA, while the larger pulse was fed to the LO port of the

multiplier from the template tunable pulse generator. The output

signal was extracted at the output of the source-follower buffer.

The layout of the CMOS receiver front-end, including the template

tunable pulse generator, UWB LNA, multiplier as well as RF and

DC pads as seen in Figure 6(b), occupies a die size of 1.4 mm

0.7 mm.

Figure 7 shows the simulated output signal in time-domain,

where the output of the multiplier depends on the polarity of the

received RF signal. When the RF pulse is in-phase with the LO

pulse, the output signal is positive as seen in Figure 7(a). When the

RF pulse is out-of-phase with the LO pulse, the output is negative,

which is shown in Figure 7(b). The output signals are obtained at

the output of the multiplier and their well-behaved waveforms

confirm that both the LNA and the multiplier have sufficiently

wide bandwidth and are able to work with sub-nanosecond pulse

inputs. The achieved good output waveforms with negligible dis-

tortion also demonstrate that the proposed impulse UWB receiver

front-end is well suited for nonsinusoidal UWB applications.

5. CONCLUSION

A compact low-cost, low-power, broadband single-chip CMOS

receiver front-end, integrating LNA, correlator, and template pulse

generator using a 0.18-m CMOS technology, has been investi-

gated for possible use as an impulse UWB receiver front-end.

Measurement results of the receiver’s constituents show the suit-

ability of these components for UWB usage. Simulation results of

the investigated receiver front-end demonstrate its workability,

hence presenting itself as a viable candidate for impulse UWB

systems.

ACKNOWLEDGMENTS

This work was supported in part by the National Science Founda-

tion and in part by the Air Force Research Laboratory.

REFERENCES

1. T.H. Lee, The design of CMOS radio-frequency integrated circuits, 1st

ed., Cambridge Univ. Press, New York, NY, 1998.

2. A. Bevilacqua and A.M. Niknejad, An ultrawideband CMOS low-

noise amplifier for 3.1–10.6-GHz wireless receivers, IEEE J Solid-State Circuits 39 (2004), 2259–2268.

3. Jazz 0.18-m CMOS Process, Jazz Semiconductor, Newport Beach,

CA, 2006.

4. Advanced Design System, Agilent Technologies Inc., Santa Clara,

CA, 2006.

5. N. Daniele, M. Pezzin, S. Derivaz, J. Keignart, and P. Rouzet, Prin-

ciple and motivations of UWB technology for high data rate WPAN

applications, Proceedings of Smart Objects Conference, Grenoble,

France, 2003.

6. C. Tu, B. Liu, and H. Chen, An analog correlator for ultra-wideband

receivers, EURASIP J Appl Signal Process (2005), 455–461.

7. A.L. Coban and P.E. Allen, A 1.5V four-quadrant analog multiplier,

IEEE Circuits and Systems, Proceedings of the 37th Midwest Sympo-

sium, Vol. 1, August 1994, pp. 117–120.

8. K. Tanno, O. Ishizuka, Z. Tang, Four-quadrant CMOS current-mode

multiplier independent of device parameters, IEEE Trans Circuits

Syst-II Analog Digital Signal Process 47 (2000), 473–477.

9. G.A. Hadgis and P.R. Mukund, A novel CMOS monolithic analog

multiplier with wide input dynamic range, IEEE Proceedings of 8th

International Conference on VLSI Design, January 1995, pp. 310–

314.

10. G. Colli and F. Montecchi, Low voltage low power CMOS four-

quadrant analog multiplier for neural network applications, IEEE Proc

Int Symp Circuits Syst 1 (1996), 496–499.

11. G. Han and E. Sanchez-Sinencio, CMOS transconductance multiplier:

A tutorial, IEEE Trans Circuits Syst-II Analog Digital Signal Process

45 (1998), 1550–1563.

Figure 7 Transient simulation of the UWB receiver front-end: (a) RF and LO pulses are in-phase, (b) RF and LO pulses are out-of-phase. [Color figure

can be viewed in the online issue, which is available at www.interscience.wiley.com]




12. I. Oppermann, M. Hamalainen, and J. Iinatti, UWB theory and appli-

cations, Wiley, Hoboken, NJ, 2004.

13. L. Zhou, Y.P. Xu, and F. Lin, A gigahertz wideband CMOS multiplier

for UWB transceiver, IEEE Int Symp Circuits Syst 5 (2005), 5087–

5090.

14. M. Miao and C. Nguyen, On the development of an integrated CMOS-

based UWB tunable-pulse transmit module, IEEE Trans Microwave

Theory Tech 54 (2006), 3681–3687.

© 2009 Wiley Periodicals, Inc.

DISCRETELY TUNABLE FIBER RINGLASER USING FBG TUNABLE FILTER AND MACH-ZEHNDERINTERFEROMETER

Wei Chen, Ning Hua Zhu, Jiang Wei Man, Shang Xiong, andLiang XieState Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, CAS, Beijing, China, 100083; Correspondingauthor: [email protected]

Received 9 February 2009

ABSTRACT: A discretely tunable Er-doped fiber-ring laser using a

fiber Mach-Zehnder interferometer (MZI) and a tunable fiber Bragg

grating (FBG) is proposed. In this scheme, the combination of MZI and

FBG acts as a discrete wavelength selector. Analysis of its transmission

function shows that discrete wavelength tuning can be realized, and ex-

perimen ts demonst rate 64 single -mode output s with a mode spacin g

of 181.7 pm, and the output power is quite stable in the whole tuning

range. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett

51: 2595–2598, 2009; Published online in Wiley InterScience (www.

interscience.wiley.com). DOI 10.1002/mop.24690

Key words: tunable fiber ring laser; fiber Bragg gratings; Mach-

Zehnder interferometers

1. INTRODUCTION

Wavelength-tunable fiber lasers have attracted great interests forapplications in WDM fiber communication systems, fiber sensors,

and so forth. Several wavelength-tuning techniques have been

reported for fiber lasers [1–12], such as the use of tunable fiber

Bragg gratings (FBG) [1–3], wavelength-tunable double-ring fiber

laser [5], tunable dual or single-wavelength fiber lasers employing

external optical injection [6, 7], fast tuning fiber laser with out-

standing quality [8], and Sagnac loop filter based fiber lasers [10].

As we know, wavelength shift is a common and difficult problem

for wavelength tunable devices, including optical tunable filters

and tunable fiber lasers. On the other hand, to enhance the multi-

plexing capability in the WDM networks of the fiber communica-

tion system, smaller channel spacing is desirable. Zhou et al. [11]

proposed a tunable fiber laser with fourteen wavelengths using a

FBG-based Fabry-Perot Filter. However, the number of available

channels is limited and the channel spacing is difficult to change.

In this letter, we propose a tunable Er-doped fiber (EDF) ring

laser with a relatively simple structure (Fig. 1). Here a fiber MZI

and a FBG filter are employed to achieve mode selection dis-

cretely. We simulate the transmission of the cascaded filter (FBG

and MZI). The experiment demonstrates a discontinuous tuning as

the simulation predicted. With our method, both wavelength sta-

bility and smaller channel spacing can be realized.

2. ANALYSIS OF THE TRANSMISSION FUNCTION

Figure 1 shows the schematic of the proposed tunable fiber laser

system. The mode selection of the fiber laser is achieved using a

FBG filter combined with an asymmetric fiber MZI which consists

of two 3-dB optical fiber couplers. The transmission function of

the unbalanced MZI is a typical cosine function, and can be written

as [13, 14]

T MZI

1

21 cos

2 nl

(1)

Figure 1 Configuration of the proposed MZI-based tunable fiber ring

laser. [Color figure can be viewed in the online issue, which is available at

www.interscience.wiley.com]

Figure 2 (a) Measured transmission spectra of both MZI (solid) and

FBG (dashed), (b) Gaussian fit of the FBG. [Color figure can be viewed in

the online issue, which is available at www.interscience.wiley.com]


Date post:	03-Jun-2018
Category:	Documents
Upload:	damodar-telu
View:	216 times
Download:	0 times

Microwave and Optical Technology Letters Volume 51 Issue 11 2009 [Doi 10.1002_mop.24682] Meng Miao;...

Documents