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SEEE DIGIBOOK ON ENGINEERING & TECHNOLOGY, VOL. 01, MAY 2018 ALTERNATE ENERGY TECHNOLOGIES 978-81-933187-0-6 © 2018 SEEEPEDIA.ORG Society for Engineering Education Enrichment Thivagr.A, [email protected] ; Dr.K.Ranjith Kumar, [email protected] ; Mitigation of THD in Multilevel Inverter with Reduced Number of Switches utilizing Solar PV Application THIVAGAR A, Dr.K.RANJITH KUMAR Government college of Technology Coimbatore, India [email protected] Abstract— In this paper, a new general cascaded multilevel inverter using developed H-bridges is proposed with new Trapezoidal Triangular Pulse Width Modulation technique (TTPWM). The proposed topology requires a lesser number of dc voltage sources and power switches, which minimize the cost of the inverter and the proposed TTPWM technique mitigates the Total Harmonics Distortion (THD) in multilevel inverter. The proposed multilevel inverter is designed to provide 31 levels. The performance of both existing and new PWM techniques in proposed multilevel inverter is compared with the help of MATLAB simulation. Index TermsTotal Harmonics Distortion (THD), Mitigation of THD, Trapezoidal Triangular PWM, Cascaded Multilevel inverter. I. INTRODUCTION Nowadays, multilevel inverters have received more attention for their ability on high-power and medium-voltage operation and because of other advantages such as high power quality, lower order harmonics, lower switching losses, and better electromagnetic interference [1], [2]. These inverters generate a stepped voltage waveform by using a number of dc voltage sources as the input and an appropriate arrangement of the power-semiconductor-based devices [3]. Three main structures of the multilevel inverters have been presented: “diode clamped multilevel inverter,” “flying capacitor multilevel inverter,” and “cascaded multilevel inverter” [4]. The cascaded multilevel inverter is composed of a number of single-phase H-bridge inverters and is classified into symmetric and asymmetric groups based on the magnitude of dc voltage sources. In the symmetric types, the magnitudes of the dc volt-age sources of all H-bridges are equal while in the asymmetric types, the values of the dc voltage sources of all H-bridges are different. In recent years, several topologies with various control techniques have been presented for cascaded multilevel inverters [5]–[8]. In [4] and [9]–[15], different symmetric cascaded multilevel inverters have been presented. The main advantage of all these structures is the low variety of dc voltage sources, which is one of the most important features in determining the cost of the inverter. In this paper, in order to increase the number of output voltage levels and reduce the number of power switches and the total cost of the inverter, a new topology of cascaded multilevel inverters is proposed. The major advantage of this topology is ability to generate a considerable number of output voltage levels by using a low number of dc voltage sources and power switches and the proposed Trapezoidal Triangular PWM technique is help to reduce the percentage of THD. II. PROPOSED TOPOLOGY The 31-level proposed inverter topology shown in Fig.1. This topology consists of ten unidirectional power switches and four dc voltage sources. According to Fig. 2, if the power switches of (S L,1 , S L,2 ), (S L,3 , S L,4 ), (S R,1 , S R,2 ), and (S R,3 , S R,4 ) turn on simultaneously, the dc voltage sources of V L,1 , V L,2 , V R,1 , and V R,2 will be short-circuited, respectively. Therefore, the simultaneous turn-on of these switches should be avoided. In addition, S a and S b should not turn on simultaneously. It is important to note that the 31-level topology can be provided through the structure presented. In the proposed general topology, the number of output voltage levels (N step ), number of switches (N switch ), number of dc voltage sources (N source ), and the maximum magnitude of the generated voltage (V o,max ) are calculated as follows, respectively: 235
Transcript
Page 1: Mitigation of THD in Multilevel Inverter with Reduced ...seeepedia.org/wp-content/uploads/2018/06/S18_05_48.pdf · Three main structures ofthe multilevel inverters have been presented:

SEEE DIGIBOOK ON ENGINEERING & TECHNOLOGY, VOL. 01, MAY 2018 ALTERNATE ENERGY TECHNOLOGIES

978-81-933187-0-6 © 2018 SEEEPEDIA.ORG Society for Engineering Education Enrichment

Thivagr.A, [email protected]; Dr.K.Ranjith Kumar, [email protected];

Mitigation of THD in

Multilevel Inverter with Reduced Number of

Switches utilizing Solar PV Application

THIVAGAR A, Dr.K.RANJITH KUMAR Government college of Technology

Coimbatore, India [email protected]

Abstract— In this paper, a new general cascaded multilevel inverter using developed H-bridges is proposed with new Trapezoidal Triangular Pulse Width Modulation technique (TTPWM). The proposed topology requires a lesser number of dc voltage sources and power switches, which minimize the cost of the inverter and the proposed TTPWM technique mitigates the Total Harmonics Distortion (THD) in multilevel inverter. The proposed multilevel inverter is designed to provide 31 levels. The performance of both existing and new PWM techniques in proposed multilevel inverter is compared with the help of MATLAB simulation.

Index Terms— Total Harmonics Distortion (THD), Mitigation of THD, Trapezoidal Triangular PWM, Cascaded Multilevel inverter.

I. INTRODUCTION Nowadays, multilevel inverters have received more attention for their ability on high-power and medium-voltage operation and because of other advantages such as high power quality, lower order harmonics, lower switching losses, and better electromagnetic interference [1], [2]. These inverters generate a stepped voltage waveform by using a number of dc voltage sources as the input and an appropriate arrangement of the power-semiconductor-based devices [3]. Three main structures of the multilevel inverters have been presented: “diode clamped multilevel inverter,” “flying capacitor multilevel inverter,” and “cascaded multilevel inverter” [4]. The cascaded multilevel inverter is composed of a number of single-phase H-bridge inverters and is classified into symmetric and asymmetric groups based on the magnitude of dc voltage sources. In the symmetric types, the magnitudes of the dc volt-age sources of all H-bridges are equal while in the asymmetric types, the values of the dc voltage sources of all H-bridges are different. In recent years, several topologies with various control techniques have been presented for cascaded multilevel inverters [5]–[8]. In [4] and [9]–[15], different symmetric cascaded multilevel inverters have been presented. The main advantage of all these structures is the low variety of dc voltage sources, which is one of the most important features in determining the cost of the inverter. In this paper, in order to increase the number of output voltage levels and reduce the number of power switches and the total cost of the inverter, a new topology of cascaded

multilevel inverters is proposed. The major advantage of this topology is ability to generate a considerable number of output voltage levels by using a low number of dc voltage sources and power switches and the proposed Trapezoidal Triangular PWM technique is help to reduce the percentage of THD. II. PROPOSED TOPOLOGY The 31-level proposed inverter topology shown in Fig.1. This topology consists of ten unidirectional power switches and four dc voltage sources. According to Fig. 2, if the power switches of (SL,1, SL,2), (SL,3, SL,4), (SR,1, SR,2), and (SR,3, SR,4) turn on simultaneously, the dc voltage sources of VL,1, VL,2, VR,1, and VR,2 will be short-circuited, respectively. Therefore, the simultaneous turn-on of these switches should be avoided. In addition, Sa and Sb should not turn on simultaneously. It is important to note that the 31-level topology can be provided through the structure presented. In the proposed general topology, the number of output voltage levels (Nstep), number of switches (Nswitch), number of dc voltage sources (Nsource), and the maximum magnitude of the generated voltage (Vo,max) are calculated as follows, respectively:

235

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SEEE DIGIBOOK ON ENGINEERING & TECHNOLOGY, VOL. 01, MAY 2018

978-81-933187-0-6 © 2018 SEEEPEDIA.ORG Society for Engineering Education Enrichment

Fig.1.Proposed Inverter Topology Nstep = 22n+1 – 1 Eq. 1 Nswitch = 4n + 2 Eq. 2 Nsource = 2n Eq. 3 Vo,max = VLn + VRn Eq. 4 The magnitudes of the dc voltage sources of the proposed 31-level inverter are recommended as follows VL1 = Vdc Eq. 5 VR1 = 2Vdc Eq. 6 VL2 = 5Vdc Eq. 7 VR2 = 10Vdc Eq. 8 The proposed inverter can generate all negative and positive voltage levels from 0 to 15Vdc with steps of Vdc III. TRAPEZOIDAL TRIANGULAR PWM In Trapezoidal Triangular PWM the carrier consists of two waveforms viz, a trapezoidal and a triangular wave as shown below in fig. 2. The lower part is trapezoidal and upper part is triangular wave.

Fig. 2 A Typical Trapezoidal Triangular Wave The Fig.3 shows that the various level shifting technique in TTPWM, Such as Phase Disposition (PD) TTPWM, Phase Opposition Disposition (POD) TTPWM and Alternate Phase Opposition Disposition (APOD) TTPWM.

(a) PD TTPWM

(b) POD TTPWM

(c) APOD TTPWM

Fig. 3 Trapezoidal Triangular Pulse Width Modulation (a) PD TTPWM (b) POD TTPWM (c) APOD TTPWM

IV. RESULTS AND DISCUSSION In order to clarify the advantage of the proposed topology with proposed TTPWM technique, it should be compared with existing Triangular PWM Technique. Here the Output voltage of inverter and percentage of THD are compared based on the MATLAB simulation results. The percentage of THD of the output voltage can be calculate by THD = √(∑∞

n=2,3..Vn2)1/2/V1 Eq. 9

Where, V1 and n are the fundamental component of voltage and order of the harmonics, respectively.

(a)For 1kHz Carrier Frequency

(b)For 5kHz Carrier Frequency

Fig.4 Proposed inverter Output voltage in TTPWM technique for (a)1kHz and (b)5kHz carrier frequency.

The Fig.4 shows the output voltage and current waveform of proposed inverter with proposed TTPWM technique.

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SEEE DIGIBOOK ON ENGINEERING & TECHNOLOGY, VOL. 01, MAY 2018

978-81-933187-0-6 © 2018 SEEEPEDIA.ORG Society for Engineering Education Enrichment

To verify the effective performance of proposed method the harmonic analysis of existing PWM and TTPWM were taken and shown in Fig.5

(a)harmonic analysis of existing Triangular PWM

(b)harmonic analysis of existing Triangular PWM

(c)harmonic analysis of proposed TTPWM

(d)harmonic analysis of proposed TTPWM

Fig.5 Harmonic analysis of proposed method output. The Fig.5(a) and Fig.5(b) are the harmonic analysis result of existing Triangular PWM technique in proposed inverter for 1kHz and 5kHz carrier Frequency respectively. The Fig.5(c)

and Fig.5(d) are the harmonic analysis result of proposed TTPWM technique in proposed inverter for 1kHz and 5kHz carrier Frequency respectively.

PWM technique Output Voltage THD

1k Triangular PWM 361.1 3.72 1k TTPWM 361.1 3.67

5k Triangular PWM 359.8 3.65 5k TTPWM 360 3.43

Table Number.1 V. CONCLUSION This paper present simulation results for new general cascaded multilevel inverter using developed H-bridges is proposed with new TTPWM technique and existing PWM technique. The brief comparison of Existing and New PWM in proposed inverter topology output voltage and Harmonic analysis results are tabulated in Table No.1. and its clearly shows the proposed TTPWM have advantage that is its minimized the THD compare to the existing PWM results. So, the proposed inverter topology is cost effective compare to conventional inverter because it requires less number of power switches and voltage source and the TTPWM is the best choice for minimizing THD and obtain maximum output voltage. REFERENCES [1]. E. Babaei and S. H. Hosseini, “Charge balance control

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SEEE DIGIBOOK ON ENGINEERING & TECHNOLOGY, VOL. 01, MAY 2018

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