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Modeling and Design for Large Scale Heterogeneous Integration
Neil Goldsman
Dept. of Electrical and Computer Engineering, UMCP
Collaborators: B. Jacob, A. Akturk, Z. Dilli, T. Chitnis,
M. Khbeis and G. Metze
Modeling and Design for Large Scale Heterogeneous Integration
Major Goal:
Design, model and fabricate high performance circuits and systems using optimized devices, circuits, as well as 3D and wafer-level integration.
Outline• Conventional Multi-Chip PC Board Integration
Summary and Limitations
• Solutions• Research Tasks for Achieving Solutions
Device and Mixed Mode Modeling Interconnect Modeling Circuit Prototyping Interconnect Prototyping and Characterization Passive components achievable with 3D fabrication
• Summary for Achieving High Performance 3D Integrated System
Processor
Integrated Systems• Systems using a mixed-signal multi-chip PCB architecture:
– Communication circuits– High performance computers– Information capture and processing
Input Output
Limiting Factors in Multi-Chip PCB Integration
• Contact Pads
• Internal and External Interconnects
• Chip Package Pins
• Printed Circuit Board Lines and Connections Between Active Circuits
• Individual Device and Inverter Switching Speeds and Current Drive
Problems with Conventional Multi-Chip Integration
Bond PadBond Wire
Transmission Line
Pins
Transmission Line
Input OutputIC 1 IC 2
Chip-to-chip PCB integration is limiting:
The parasitics of the bond pads, wires and board buses limit speed, driving capability and functionality
Problems with Conventional Multi-Chip Integration
Increased demand for complexity…
Problems with Conventional Multi-Chip Integration
…does NOT improve matters
Limitations in IntegrationIn fact, not only interconnects but each level in the integration hierarchy imposes its own limitations on the system performance.
•Speed•Power•Parasitics
•Speed•Power•Noise
•Speed•Power•Parasitics (C & L)•Crosstalk
Search for Solutions to Integration Bottlenecks
•Focus on improved device design for devices with higher driving capability on pads and interconnects
•Focus on improved circuit design and layout to minimize the parasitic effect of pads and interconnects
•3-D integration (3-DI)•Wafer-scale integration (WSI)
Wafer Level & 3D Solutions
• To nullify some of the negative effects of chip-to-chip interconnects
Wafer-Scale Integration (WSI) Three-Dimensional Integration
Research Tasks
1. Model and design devices optimized for speed and drive2. Develop mixed signal modeling algorithms to design
fundamental circuit elements for drive and speed.3. Develop algorithms and codes for modeling interconnect
parasitics (C and L)4. Design and prototype circuits for implementation in 3D and
wafer level integration.5. Design and fabricate 3D and wafer level interconnect test
structures and passive circuit elements.6. Measure to extract parasitics for characterization of 3D
interconnects.7. Combine Tasks 1 through 6 to design and fabricate high
performance 3D circuit.
Task1. Model and Design devices optimized for speed and drive
Modeling: Device Dimensions and Doping Profiles Optimized for Switching & Drive
Dopant Concentrations of the Devices
Doping Profile of a 0.1m Physical Gate LengthSource Side Halo Implanted NMOSFET
1. Contact Regions: S/D (0.3m wide),Gate (0.1m wide),
2. Spacer (0.1m wide)3. Gate Oxide (25Å tall, 0.3m wide)4. Highly Doped Source/Drain
(0.1m tall, 0.35m wide) LDD
Regions are at the edges of channel (0.05m tall, 0.05m wide)
5. Substrate (0.5m tall, 0.9m wide)6. Halo (0.01m thick, either around
the Source or Drain)
Devices DSUB (cm-3) DHALO (cm-3) DLDD (cm-3) DS/D (cm-3)
Halo 1x1016 5x1017 5x1018 1x1020
Conventional 5x1017 - 5x1018 1x1020
Asymmetric Doping
Modeled DC Current Densities for Different NMOS Structures
Asymmetric Best
ppp
nnn
Si
GRJqt
p
GRJqt
n
Dnpq
.1
.1
)(2
DD Equations
pVqpqJ
nVqnqJ
Tppp
Tnnn
Supplementary DD Equations
Coupled Discretized DD Equations are solved at each mesh point
DC Current Densities of NMOS for |VGS|=(0.4,0.7,1.0)V and VSB=0V
Electric Fields in Channel Explain
Improvement of Asymmetrical Device
(a) Lateral and (b) Vertical Surface ElectricFields of NMOS at VGS= VDS =1V
Modeled NMOS Turn-on Characteristics
(a) Turn-on and (b) Turn-off Characteristics of NMOS
Task2. Develop mixed signal modeling algorithms to design fundamental circuit elements for drive and speed.
ppp
nnn
Si
GRJqt
p
GRJqt
n
Dnpq
.1
.1
)(2
DD Equations
pVqpqJ
nVqnqJ
Tppp
Tnnn
Supplementary DD Equations
Coupled Discretized DD Equations are solved at each mesh point
CMOS Inverter (CMI)
LPNLL
LPNLLi
oSSi
o
io
io
LL
SSi
oioPP
ioNN
CRDPDN
RBBtCR
RAAtCR
VVV
t
VVC
R
VVVBAVBA
IIIILL
)(1
)(
0
0
1
1111
Lumped KCL equation check at the output nodeand using the KCL equation, the output guess isupdated for the next iteration, VO
i+1:
Mixed-Mode Simulator
Modeled Transfer Characteristics of CMOS
Inverters
Transfer Characteristics of CMOS Inverterswith(out) a Resistive Load.
Output Current Densities of CMOS Inverters
Switching Characteristics of CMOS Inverters
Switching Characteristics of CMOS Inverterswithout a Capacitive Load.
Switching Characteristics of CMOS Inverterswith Capacitive Loads
Switching Characteristics of CMOS Inverterswith CL=0.3pF/20m.
Switching Characteristics of CMOS Inverterswith CL=10fF/20m.
Net Charge Density During
Low-to-High Input Transition
The variation of the net charge density at the conventional MOSFET during low-to-high transition.NMOS and PMOS channels are around 0-0.1 and 1.0-1.1 μms along the lateral x, respectively.
Task 3: Calculation of the Induced Voltage on
Floating Metals via Capacitive Effects
A Typical Bus allows one Write and certain number of Reads through a single line while the remaining connections are kept in high
Impedance or floating states.
Voltages induced on the floating pins due to the capacitive network
Simulation
We developed a simulation tool to find the induced voltages on the floating metals due to the pins tied up to a fixed
voltage source in an arbitrary rectangular geometry.
0
0
2
2
2
2
2
2
2
zyxzyx
Net Charge is zero inside the metals and the
insulator that is filling the region between the metals
InsinsMetMetInsInsS
S
S
V
V
EEE
dSdV
0Total charge concentration on the
floating metals is zero
AppliedM VThe potential is constant
for the fixed metals
2D Simulation Result
Here, there are 36 metals uniformly distributed on our mesh grid.The voltages on the two metals at the opposite corners are set to
0 and 10V, and the rest is left to float.
Potential Distribution
3D Simulation ResultThe previous distribution is kept for 3 layers
in the z direction (3rd-5th), and no othermetals are put outside this z range
Potential Distribution at z=4
Isopotential Surfaces
Capacitances In Multiconductor Systems
NNNNNN
NN
NN
VCVCVCQ
VCVCVCQ
VCVCVCQ
...
:
...
...
2211
22221212
12121111 The relation between potential and charge
is linear
NNNN
N
N
ijVi
iji
CCC
CCC
CCC
CV
QC
j
...
::
...
...
21
12221
11211
,0
MMMMLLLLL
MLL
MLL
MMMMMMMMFFFFFFFFF
MMMMMMMMFFFFFFFFF
MMMMMMMMFFFFFFFFF
VCVCVCVCVCVC
VCVCVCVCVCVC
VCVCVCVCVCVC
......
:
......
......
22112211
22221122222212
12211111221111
By LU decomposition, we find the voltages on the floating metals, (VF1-VFL), using the C matrix and the voltages of the fixed metals, (VM1-VMM).
Then, we find the potential distribution by the utilization of the Conjugate Gradient Method.
0.6 0.8 1 1.2 1.4 1.6ThicknessHumL0.15
0.2
0.25
0.3
0.35
fl
eS
ec
na
tc
ud
nIHHnmmL
w=3um
t
Typical Inductance of Internal Interconnect
Proposed Model: Coupling Maxwell Eqns. to Semiconductor Transport Eqns.:
VneJ
VnmnkTBVEqn
dt
Vdnm
Vnt
n
Jt
E
cB
t
BE
m
ee
r
)(
0)(
2
Assuming isothermal condition: T= constant.
ne
m ue
mCollisional time , un: electron mobility
Nonlinearity: collisional term (mobility) is a nonlinear function.
Keeping inertial term in the momentum equation to account for the electron finite response time.
Task 4:Design and prototype circuits for implementation in 3D and wafer level integration.
Prototype Processor
• Verilog HDL
• Teaching ISA
• TI ‘C6000 DSP ISA in progress
• Fully pipelined
• Handles interrupts precisely
• Can boot an RTOS (or OS …)
INSTRUCTIONMEMORY
DATAMEMORY
REGISTERFILE
Program Counter
TGT
SRC1
SRC2
SRC1 SRC2
CONTROL
PC Update
MUX
TGT
WDATA ADDR
RDATA
ADDR
ALU Result Bus
ALU
INSTRUCTION
OPCODE
Phase-Locked Loops• Can be designed and operated both for analog and digital signals
FM TransceiverThe quintessential analog communication system representative
MatchingNetwork
Antenna
PAInputSignal
DCBias
VoltageAdder
VCO
RCNetwork
FM Modulator
LNAMatchingNetwork
AntennaMixer
LocalOscillator
PLL
CrystalFilter
IFA AAOutputSignal
FMDemodulator
Transmitter
Receiver
Task 5: Design and fabricate 3D and wafer
level interconnect test structures and passive circuit elements.
On-Chip Inductors and Transformers:Surface versus 3D
Current Sheet Approach
• Valid for geometries with small spacing between between the metal lines.
• Approximates a square Spiral with four trapezoids forming a square.
• Adjacent trapezoids don’t have mutual inductance since current flow in them is perpendicular.
Different Inductor Geometries
Square Inductor
Hexagonal Inductor
Octagonal Inductor
Square Transformer – One Inductor Outside Another
Advantages : -High Self Inductance-Low terminal to substrate capacitance-Low terminal to terminal capacitance
Disadvantages : -Low Mutual coupling (0.3 – 0.5)
Parameters :
Li = 2.3 nH ( Inner L)Lo = 3.56 nH ( Outer L)LT = 9.87 nH ( Total L)M = 2.00 nH ( Mutual L)K = 0.35 ( Coupling )Area = 350 um2
Reducing Parasitic Capacitance of Surface Inductor
SiO2 supports Air Gap formed by etching
Removing the Silicon Dioxide reduces the capacitance to substrate and is
expected to improve Inductor Quality Factor.
Layout 3-D Picture (not to scale)(Connection to pads not shown)
Layout 3-D Picture ( not to scale)(connection to Pads not shown)
Wafer 2
Wafer 1Air Gap(formed by etchedout Silicon Dioxide)
Vertical Vias
3D Allows Much Larger L
Area of Via = 2 m x 2 mDimension of Layout : W = 250 m, L = 450 mNumber of turns = 100 ; Inductance = 115 nH
Comparison of Areas and Inductances
Area InductanceSquare Spirals 32400 m2 2.5 nH
48000 m2 8.1 nH
Hexagonal Spirals 32500 m2 2.3 nH48000 m2 7.6 nH
Octagonal Spirals 35000 m2 3.5 nH55000 m2 11.7 nH
3-D Inductors 28800 m2 28.8 nH(Expected Inductance) 57600 m2 57.74 nH
115200 m2 115 nH
Task 6: Measure to extract parasitics for
characterization of 3D interconnects.
Preliminary analysis indicates pad, pin parasitics are significantly detrimental.
Test structure layout complete; submission to Northrop Grumman immenant. (M. Khbeis, G. Metze)
Conclusion• Conventional Multi-Chip PC Board Integration
Summary and Limitations
• Solutions• Research Tasks for Achieving Solutions
Device and Mixed Mode Modeling Interconnect Modeling Circuit Prototyping Interconnect Prototyping and Characterization Passive components achievable with 3D fabrication
Bond Pad
Electro-Static Discharge(ESD)
Die(Integrated Circuits)
An IC with Bonding Pads
Chip-to-Chip Connection on PC Board:
Bond Pad
Bond WireTransmission Line
Pins
Input Output
Die (Integrated Circuits)PC Board
Standard Planar Technology Implementation: IC Chips on PCBs
Bond Pad
Bond Wire
Transmission Line
Pins
Input Output
ICs ICs
Signal Path in Planar Chip-to-chip Connection
Si Substrate
Metal
InsulatorOxide
padC
Metal Layer
Substrate
Plate Capacitor
0
20
40
60
80
100
120
140
160
1.5u 0.5u 0.35u 0.25u
Process
Pad
Cap
acit
ance
(fF
)
Pad Parasitic Capacitance vs. Process(Best Case assuming top metal, no ESD)
Pad Capacitance
Example Circuit: Ring Oscillator
Faster!
Slower!
Bond Pad
0.5
1
1.5
2
No Pads 1 Pad 2 Pads 3 Pads
Number of Pads in Loop
Osc
illa
ting
Fre
quen
cy (
GH
z)
Digital Circuit Speed
BondPad
fFC pad 40
Circuit Driving Capacity
mmWL 48.024.0
mmWL 92.124.0
NMOS:
PMOS:
fFC nmosg 7.0,
fFC pmosg 8.2,
fFC totalg 4,
Input Capacitance of A CMOS Inverter:
totalgpad CC ,10
Driving a bond pad is equal to driving TEN inverters!
Conventional Bonding: Limitations on System Performance
IC Package Parasitics
Bond Pad
Bond Wire
Pin
Bond Pad(Several Hundred femto-Farad)
Bond Wire & Pin(Several nano-Henry)
Requires impedance matching in design to:
• Maximize Power Transformation• Eliminate Signal Reflection• Minimize Clock Skew
Transmission Line
IC 1 IC 2Input Output
Tune to Z0
Tune to Z0 Tune to Z0
Z0
Effect of Pad and Package Parasitics on Circuit Operation Speed
Test circuit: Binary-to-Gray-to-Binary converterObjective: To find out max. clock frequency for which Input = Output
Effect of Pad and Package Parasitics on Circuit Operation Speed: Simulation Results
Device Size ( L = 0.25u)
SeparateChips
As a stack Without pads and pins
W = 0.5u Speed 80 MHz 100 MHz 2.5316 GHz
Power 0.98 mW 0.435 mW 2.31 mW
W = 1.0u
Speed 133 MHz 166 MHz 2.5974 GHz
Power 1.825 mW 1.06 mW 4.5 mW
W = 1.5u
Speed 200 MHz 250 MHz 2.6316 GHz
Power 2.825 mW 1.757 mW 6.575 mW
W = 2.0u Speed 222 MHz 333 MHz 2.6666 GHz
Power 3.425 mW 2.675 mW 8.5 mW
Research into Mixed-Signal Architectures
• Circuit-level research aims to identify bottlenecks and limitations more precisely
• Design, simulate and fabricate mixed-signal circuits for the purpose– FM transceiver– PLL– Microprocessors– Image sensor systems
Processor? Insert material from Dr. Jacob here?
• Signal networks within the ICs themselves also require investigation
• Example: Clock and power networks in CPUs
Clock networks: H-networks. Power networks: Grids.Reminiscent of some antenna configurations:EM-interference problems?
• Fan-out and bus-driving problems: Tie-in to new device and circuit architectures
Intra-chip interconnect problems
Current Sheet Approach (contd..)
• We require expressions for Self Inductance of a Trapezoidal sheet and mutual inductance between two parallel trapezoidal sheets.
• Self Inductance of a Trapezoidal sheet and mutual inductance between two parallel trapezoidal sheets is calculated as an extension of the mutual inductance between two unequal sized parallel lines.
• A further extension of this yields expressions for the inductance of a Square Spiral.
• This can be extended to Hexagons and Octagons.
• For example in a Hexagon the adjacent trapezoids have a component of mutual inductance.
Current Sheet Approach (contd..)
A general expression for the inductance is
Where = Magnetic Permeabilityn = No. of turns
davg = Average length of elementc = Constants depending on the shape of the inductor = Fill Factor = (nw + (n-1)s)/lw = Width of conductors = Spacing between conductors
l = Average length of element ( Different from davg for shapes other than square)
])[ln(2
243
212
cc
ccdnL avg