Modern Memory Interfaces (DDR3) Design with ANSYS … · Modern Memory Interfaces (DDR3) Design ......

1-1 ANSYS, Inc. Proprietary © 2009 ANSYS, Inc. All rights reserved.

February 23, 2009 Inventory #002593

© 2012 ANSYS, Inc. November 14, 2012 1

Modern Memory Interfaces (DDR3) Design with ANSYS Virtual Prototype approach




• DDR Design Challenges

• How does simulation solve these design challenges?

– Circuit + EM Extraction! (Virtual Prototype)

• Virtual Prototype – Accuracy – Speed – Capacity – Repeatability & Automation

• Summary

Agenda




VIH.ac=1.15V

1.8V SSTL

Vref =0.9V

VIL.ac=0.65V

0V

VIH.dc=1.025V

VIH.dc=0.775V

Logic Voltage Level & AC&DC Logic Thresholds

0.65V Single-ened

without shunt(ODT) termination For AC250

+250mV

-250mV

• DDR3 Design Challenges for Signal Inetgrity – Reduced Voltage Noise Margin

DDR X Technology

VIH.ac=0.925V

1.5V SSTL

Vref =0.75V

VIL.ac=0.575V

0V

VIH.dc=0.85V

VIH.dc=0.65V


0.575V Single-ened

without shunt(ODT) termination For AC175

+175mV

-175mV

Standard DDR SDRAMs DDR2 SDRAM

DDR3 SDRAM

DDR4 SDRAM

Mobile DDR SDRAMs LPDDR

VIH.ac=1.44V(VDDx0.8)

1.8V LVCMOS

Vref =0.9V

VIL.ac=0.36V(VDDx0.2)

0V

VIH.dc=1.26V(VDDx0.7)

VIH.dc=0.54V(VDDx0.3)


0.36V Single-ened

LPDDR2 VIH.ac=0.9V

1.2V HSUL

Vref =0.6V

VIL.ac=0.3V

0V

VIH.dc=0.8V(VDDx0.7) VIH.dc=0.4V(VDDx0.3)


0.3V Single-ened For AC300

+300mV

-300mV

VIH.ac=0.75V

1.2V HSUL

Vref =0.6V

VIL.ac=0.45V

0V

VIH.dc=0.7V(VDDx0.7) VIH.dc=0.5V(VDDx0.3)


0.45V Single-ened For AC150

+150mV

-150mV

LPDDR3

Cfixture (<2~3pF)

Without off-chip interconnect.

V ~

Output buffer for DDR interface

VIH.ac=TBD

1.2V POD(Peudo-open drain)

Vref =0.6V

VIL.ac=TBD

0V

VIH.dc=TBD

VIH.dc=TBD


Less than 0.52V Single-ened

without shunt(ODT) termination




• DDR3 Design Challenges for Signal Inetgrity – Reduced Timing Margin

DDR X Technology

Data

Strobe

Bit Width(Unit Interval) = 2.5ns

LPDDR

LPDDR2


DDR2


LPDDR3 DDR3


DDR4





• Design challenges? – Validation

• Prototype • Measurement • Interpret and implementation(calculation) of Design Spec such as DDR3, LPDDR2

and more… • Large amount output data report of results

– Capacity or Complexity and Time

• Chip to Chip or Chip to PKG • Chip + Package + PCB + Connector/Cable + PCB + Package + Chip • Full System

DDR X Technology & Challenges

227 pages of JEDEC DDR3 specs




Electrical

Fluid Dynamic Mechanical

ANSYS Solution

Images and models courtesy of the Xilinx, Micron Technology, TE Connectivity.




Electrical 3D CAD

Layout

Virtual Prototype Electromagnetic Extraction

Vendor Specific Driver/Receiver Models

Vendor Specific VRM Models

Electronics Virtual Compliance

Virtual System

Virtual System Prototyping

ECAD

MCAD

HFSS™, PSI™, SIwave™

DesignerSI™, UDS, UDD




• Solutions & Benefits

Simulation Technology

HFSS™

PSI™

SIwave™

Accuracy

3D FEM

Prism

2D FEM/MOM

Speed

Capacity

Automation

AN

SYS D

esigner SI™




• Main Board Side – No termination resistors for all signals – Point-to-Point Interconnect topology between FPGA and SODIMM – Controlled skews by serpentine traces – Layer Stackup; 16 layers, 2mm Thickness, 8 power planes, – Substrate : FR4 – Board size : 139.7mm x 266.7mm

Design Review (1/2)




• SODIMM Side – Data Group Signals : Point-to-Point Topology with series termination resistor – Clock/Address/Command Signals : Fly-by-Topology

Design Review (2/2)

Ex) CAS signal with pull-up end termination

Vtt termination rail




• Hybrid Solution – Main PCB, SODIMM PCB, SODIMM Connector

Simulation Technology 1/3

SIwave™

SIwave™

Connector(S-Parameter from Vender or Simulation)




• Full 3D FEM and Prism – Main PCB, DIMM PCB, 204pin Connector(Full 3D EM Model)


Spice Model

n-Node Component from HFSS

HFSS™ Connector + PCB

Sentinel PSI™





Solve in Designer using HFSS

Clip

• HFSS Solver on Demand, – HFSS in Designer can handle full 3D interconnect PCB, PKG and Package on PCB Model




• Critical Net in HFSS – Add full 3D HFSS interconnect Model include ALL(PKG, Connector, PCB)

Simulation Technology




• Differential Clock Signal

Post Layout Simulation (1066Mbps)

ANSYS DesignerSITM

Memory Controller

soDIMM Connector

Odd mode propagation

+350mV

-350mV




• Data group signals


Point-to-Point Topology



With Series R(20Ohm)




• Data group signals – Write Operation / ODT(on-die-termination) Disabled


Differential Strobe0 DATA0 DATA0 + DATA1 DATA0 + DATA1 + DATA2 + … DATA0 + DATA1 + DATA2 + … + DATA7

ANSYS DesignerSITM




DATA0 + DATA1 + DATA2 + … + DATA7


• Setup Margin Calculation (before derating)


Vref=0.75V

AC150 Vref+150mV VIH.AC=0.9V

AC150 Vref-150mV VIL.AC=0.6V


The earliest strobe signal at Vref.diff

Valid Before Time Tvb=152psec

75psec setup time from receiver(JEDEC) specification 77 psec

Setup Margin

ANSYS DesignerSITM




ANSYS DesignerSITM

Slew Rate Comparison Between Differential DQS and Data Signals

6.15V/ns

3.53V/ns

6.15V/ns

3.53V/ns

1) setup time(without derating)



• Setup Margin Caculation (with derating value)




• UDS (User Defined Solutions)

UDS




•UDS (User Defined Solutions) allows calculations and post-processing of simulated or raw transient simulation data

– Supported thru IronPython scripting – Designer .sdf solutions file – H-Spice .tr0 solutions file – Useful in Virtual Compliance calculations for different standards

•Key benefits: – AC Data Timing Calculations (tDS, tDH, derate …) – Non-Ideal voltage supply is supported – Every bit-by-bit falling and rising transition edge is calculated – Fully customizable through Python scripts.

• Templates currently exists for LPDDR, DDR2 and DDR3 standards

Why ANSYS UDS ?




For the waveforms(tr0, sdf) from HSPICE or Nexxim

Valid Before Time (Tvb) Setup Margin without derating value = Tvb(151.86..ps) – setup time (75ps)

Derating Value is automatically calculated!!! (After comparing tangential slew rates through UDS.)



• ANSYS UDS(User Defined Solution) for DDR application






• Hold Margin Calculation (before derating)


DC100 Vref+100mV VIH.DC=0.85V

DC100 Vref-100mV VIL.DC=0.65V

The latest strobe signal at Vref.diff

Valid After Time Tva=160psec

60 psec Hold Margin

100psec Hold time from receiver(JEDEC) specification

ANSYS DesignerSITM





• Hold Margin Calculation (with derating value)


ANSYS DesignerSITM

Valid After time(Tva)=160psec Hold Margin(without derating value)

= Tva(160psec) – hold time(100psec) = 60psec

Hold Time for DC100 & 1066Mbps




• Data group signals – Write Operation / with ODT 120/60/40 Ohm


ODT_disabled at DDR3 SDRAM ODT_120 at DDR3 SDRAM 240Ohm

240Ohm

Negative Setup Margin

All positive hold margin!

ODT_120 at DDR3 SDRAM ODT_60Ohm at DDR3 SDRAM 120Ohm

120Ohm

VDD(Q)

For all data signals, setup margin with derating value is positive.

Hold margin with derating value is also positive.

ODT_60Ohm at DDR3 SDRAM ODT 40Ohm at DDR3 SDRAM 80Ohm

80Ohm

VDD(Q)

Negative Setup Margin!

Hold margin with derating value is also positive.

ODT 40Ohm at DDR3 SDRAM

ANSYS DesignerSITM




UDD (User Defined Document)




• UDD include – Design Summery, Simulation Setup – Per-Lain, Per-DQ and Per-Edge Calculation – HTML Report support Hyperlink and automatic Post Processing.

UDD Slides




Summary

• Modern Memory Interfaces (DDR3) Design with ANSYS Virtual Prototype approach

– Power of EM & Circuit Simulation • The combination of ANSYS Solution are very helpful to get insight for your SI

problem in all direction

– Easy Validation • UDS, UDD

– Virtual Compliance Test

• H/W engineers can prevent from logical malfunction through SI simulation and optimized the system performance through what-if simulation.




Thank You

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