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Module Design Side by Gerrit Muller University of South-Eastern Norway-NISE e-mail: [email protected] www.gaudisite.nl Abstract This module addresses the Conceptual and Realization Views. Distribution This article or presentation is written as part of the Gaudí project. The Gaudí project philosophy is to improve by obtaining frequent feedback. Frequent feedback is pursued by an open creation process. This document is published as intermediate or nearly mature version to get feedback. Further distribution is allowed as long as the document remains complete and unchanged. September 6, 2020 status: draft version: 0 logo TBD
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Page 1: Module Design Side - gaudisite.nl

Module Design Sideby Gerrit Muller University of South-Eastern Norway-NISE

e-mail: [email protected]

Abstract

This module addresses the Conceptual and Realization Views.

Distribution

This article or presentation is written as part of the Gaudí project. The Gaudí projectphilosophy is to improve by obtaining frequent feedback. Frequent feedback is pursued by anopen creation process. This document is published as intermediate or nearly mature versionto get feedback. Further distribution is allowed as long as the document remains completeand unchanged.

September 6, 2020status: draftversion: 0

logoTBD

Page 2: Module Design Side - gaudisite.nl

The conceptual viewby Gerrit Muller University of South-Eastern Norway-NISE

e-mail: [email protected]

Abstract

The purpose of the conceptual view is described. A number of methods or modelsis given to use in this view: construction decomposition, functional decomposition,class or object decomposition, other decompositions (power, resources, recycling,maintenance, project management, cost, ...), and related models (performance,behavior, cost, ...); allocation, dependency structure; identify the infrastructure(factoring out shareable implementations), classify the technology in core, keyand base technology; integrating concepts (start up, shutdown, safety, exceptionhandling, persistency, resource management,...).

Distribution

This article or presentation is written as part of the Gaudí project. The Gaudí projectphilosophy is to improve by obtaining frequent feedback. Frequent feedback is pursued by anopen creation process. This document is published as intermediate or nearly mature versionto get feedback. Further distribution is allowed as long as the document remains completeand unchanged.

September 6, 2020status: preliminarydraftversion: 0.7

storage

acquisition

processingcompress

encoding

display

processing

de-

compress decodingdisplay

acquisition

Page 3: Module Design Side - gaudisite.nl

Example construction decomposition simple TV

tunerframe-

bufferMPEG DSP CPU RAM

drivers scheduler OS

etc

audio video TXTfile-

systemnetworkingetc.

view PIP

browseviewport menu

adjustview

TXT

hardware

driver

applications

services

toolboxes

domain specific generic

signal processing subsystem control subsystem

The conceptual view3 Gerrit Muller

version: 0.7September 6, 2020

CVconstructionDecomposition

Page 4: Module Design Side - gaudisite.nl

Characterization of the construction decomposition

management of design

file

box

IP core

IC

unit of aggregation for

organisation

test

release

unit of

creation

storage

update

SW example

package

module

PCB

IP cells

IP core

HW example

The conceptual view4 Gerrit Muller

version: 0.7September 6, 2020

CVconstructionDecompositionCharacterization

Page 5: Module Design Side - gaudisite.nl

Example functional decomposition camera type device

storage

acquisition

processingcompress

encoding

display

processing

de-

compress decodingdisplay

acquisition

The conceptual view5 Gerrit Muller

version: 0.7September 6, 2020

CVfunctionalDecomposition

Page 6: Module Design Side - gaudisite.nl

Characterization of the functional decomposition

How;

what is the flow of internal activities

to realise external functionality?

some keywords:

activities

transformation

input output

data flow

control flow

multiple functional decompositions

are possible and valuable!

The conceptual view6 Gerrit Muller

version: 0.7September 6, 2020

CVfunctionalDecompositionCharacterization

Page 7: Module Design Side - gaudisite.nl

Question generator for multiple decompositions

memory usage

export

server

print

server

database

server

SNR

accuracy

latency

processing

brightness

next

play movie

render film

query DB What is the memory usage of

the user interface

when querying the DB

import

server

user

interface

functions

component

characteristics

when performing <function>?

of the <component>

How about the <characteristic>

The conceptual view7 Gerrit Muller

version: 0.7September 6, 2020

MSquestionGeneratorEasyVision

Page 8: Module Design Side - gaudisite.nl

Selection factors to improve the question generator

Critical for system performance

Risk planning wise

Least robust part of the design

Suspect part of the design

- experience based

- person based

The conceptual view8 Gerrit Muller

version: 0.7September 6, 2020

CVimprovedQuestionGenerator

Page 9: Module Design Side - gaudisite.nl

Addressing planes or lines

component

memory usage

export

server

print

server

database

server

SNR

accuracy

latency

processing

brightness

next

play movie

render film

query DB

memory budget plane

import

server

user

interface

fun

ctio

ns

char

acte

ristic

squery DB

design spec

The conceptual view9 Gerrit Muller

version: 0.7September 6, 2020

CVquestionGeneratorPlanes

Page 10: Module Design Side - gaudisite.nl

Example partial internal information model

patient

examination

scan

2D images

3D volume

attributes

scan procedures

exam procedures

attributes

attributes

attributes

attributes

work-listattributes

volume index

image index

pictorial index precompiled

data elements additional

to the external information

model

The conceptual view10 Gerrit Muller

version: 0.7September 6, 2020

CVinformationModel

Page 11: Module Design Side - gaudisite.nl

Example process decomposition

image handlingscan control

scan

control

acq

control

recon

control

xDAS recon

db

control

disk

scan

UI

image handling

UI

archiving

control

media

import

export

network

display

control

display device hardware

server

process

UI process

legend

The conceptual view11 Gerrit Muller

version: 0.7September 6, 2020

CVprocessDecomposition

Page 12: Module Design Side - gaudisite.nl

Execution architecture

other architecture

views

execution

architecture

functional

model

process

display

receive demux

store

Map

process

task

threadthreadthread

process

task

threadthreadthread

process

taskthreadthreadthread

interrupt

handlersinput

hardware

tuner drive

CPU DSP RAM

input

repository

structure

queue

DCTmenu

txt

tuner

foundation

classes

hardware

abstraction

list DVD drive

UI toolkit processing

Applicationsplay zap

input

dead lines

timing, throughput

requirements

execution architecture

issues:

concurrency

scheduling

synchronisation

mutual exclusion

priorities

granularity

The conceptual view12 Gerrit Muller

version: 0.7September 6, 2020

CVexecutionArchitecture

Page 13: Module Design Side - gaudisite.nl

Performance Model

trecon =

nraw-x * ( tfft(nraw-y)

ny * ( tfft(nraw-x)

tfilter(nraw-x ,nraw-y) +

+

+

tfft(n) = cfft * n * log(n)

filter FFT FFTcorrections

nraw-x

nraw-y

nraw-x

nraw-y

nraw-x

ny

nx

ny

nx

ny

tcol-overhead

tcorrections(nx ,ny)

trow-overhead

tcontrol-overhead

+

) +

) +

The conceptual view13 Gerrit Muller

version: 0.7September 6, 2020

CVreconstructionPerformanceModel

Page 14: Module Design Side - gaudisite.nl

Safety, Reliability and Security concepts

• containment (limit failure consequences to well defined scope)

• graceful degradation (system parts not affected by failure continue operation)

• dead man switch (human activity required for operation)

• interlock (operation only if hardware conditions are fulfilled)

• detection and tracing of failures

• black box (log) for post mortem analysis

• redundancy

The conceptual view14 Gerrit Muller

version: 0.7September 6, 2020CVlistSRSconcepts

Page 15: Module Design Side - gaudisite.nl

Simplified start up sequence

discover kernel HW

initialise kernel data structures

determine next layer

load and initialise loader

determine loading HW

determine next layer

bring in initial state

load and initialise firmware

configure services

allocate resources

load, initialise and start services

configure UI

allocate resources

load, initialise and start UI

detect external services

publish internal services

connect where needed

load

configure

initialise, start

power

boot-loader

HW

kernel

services

user interface

connect to outside

application

stop in safe sequence

flush ongoing activities

close connections

save persistent data

free resources

stop

start up

HW SW interface

shut down

The conceptual view15 Gerrit Muller

version: 0.7September 6, 2020

CVstartUp

Page 16: Module Design Side - gaudisite.nl

Example work breakdown

work packagesproject organization

TIP:NBE

R1

xDASreconstruction

hardware

viewing

database

scanning

xFEC

run time

acq

prepa-

ration

conver-

sion

algo-

rithms

UIgfxalgo-

rithmsVDU console

import

exportarchive

bulk

dataclinical

database

engine

computing

system

host OSfoundation

classes

start up

shutdown

exception

handling

integra-

tionSPS

SD

STPS

alfa

test

beta

test

conf

man

make SW

make HW

buy SW

buy HW

system

segment

project

legend

The conceptual view16 Gerrit Muller

version: 0.7September 6, 2020CVworkBreakdown

Page 17: Module Design Side - gaudisite.nl

Core, Key or Base technology

Core

Key

Base

make outsource buy refer customer

to 3rd party

Own valueIP

Critical for finalperformance

Commodity

Technology life cycle

Partnering

Total Product

The conceptual view17 Gerrit Muller

version: 0.7September 6, 2020

SSScoreKeyBase

Page 18: Module Design Side - gaudisite.nl

Example integration plan

existing base system

new HW subsystem

SW dev system

test HW subsystem

test SW for new HW subsystem

new application

existing base system

integrate subsystem

SW dev system test and refine application

integrate and refineapplication

adopt existing base SW

new base system test new base systemintegrate HW

system

integrate

system

SW for new HW subsystem

adopt existing base SW

existing new

2 partial

systems for

SW testing

2 existing

base

systems

new base

systems

time

integrated

system

application integration

new subsystem

integration

The conceptual view18 Gerrit Muller

version: 0.7September 6, 2020CVintegrationPlan

Page 19: Module Design Side - gaudisite.nl

The realization viewby Gerrit Muller University of South-Eastern Norway-NISE

e-mail: [email protected]

Abstract

The realization view looks at the actual technologies used and the actual imple-mentation. Methods used here are logarithmic views, micro-benchmarks andbudgets.Analysis methods with respect to safety, reliability and security provide a link backto the functional and conceptual views.

Distribution

This article or presentation is written as part of the Gaudí project. The Gaudí projectphilosophy is to improve by obtaining frequent feedback. Frequent feedback is pursued by anopen creation process. This document is published as intermediate or nearly mature versionto get feedback. Further distribution is allowed as long as the document remains completeand unchanged.

September 6, 2020status: preliminarydraftversion: 0.1

complex

compression

simple

compression

100

200

150

250

1.5 2.0 2.51.00.50.010020 40 60 80 120

50

$

sourc

e:

http

://w

ww

.mpcom

p.c

om

/

Septe

mber

5, 2002

GHzGByte

performance

effort needed

to obtain required

storage capacity

effort needed

to obtain required

processing performance

no compression

man-year

5

10

15

20

5400 rpm

7200 rpm

7200 rpm,

8 MB buffer

pentium4

Page 20: Module Design Side - gaudisite.nl

Budget based design flow

budgetdesign

estimates;simulations

V4aa

IO

micro benchmarks

aggregated functions

applications

measurements existing system

model

tproc

tover

+

tdisp

tover

+

+

spec

SRStboot 0.5s

tzap 0.2s

measurements new (proto)

systemform

micro benchmarks

aggregated functions

applications

profiles

traces

tuning

10

20

30

5

20

25

55

tproc

tover

tdisp

tover

Tproc

Tdisp

Ttotal

feedback

can be more complex

than additions

The realization view20 Gerrit Muller

version: 0.1September 6, 2020

EAAbudget

Page 21: Module Design Side - gaudisite.nl

Example of a memory budget

shared code

User Interface process

database server

print server

optical storage server

communication server

UNIX commands

compute server

system monitor

application SW total

UNIX Solaris 2.x

file cache

total

obj data

3.0

3.2

1.2

2.0

2.0

0.2

0.5

0.5

12.6

bulk data

12.0

3.0

9.0

1.0

4.0

0

6.0

0

35.0

code

11.0

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

13.4

total

11.0

15.3

6.5

10.5

3.3

6.3

0.5

6.8

0.8

61.0

10.0

3.0

74.0

memory budget in Mbytes

The realization view21 Gerrit Muller

version: 0.1September 6, 2020

RVmemoryBudgetTable

Page 22: Module Design Side - gaudisite.nl

Actual timing on logarithmic scale

Disk se

ek

hum

an 1st ir

ritat

ion

thre

shold

appl le

vel fun

ction

resp

onse

hum

an 2nd ir

ritat

ion

thre

shold

eye-

hand

co-

ordina

tion

1 pa

ckag

e tra

nsfe

r

fast e

ther

net

(ps)

10-12

(ns)

10-9

(s)

10-6

(ms)

10-3

(s)

1

cycle

2 GHz CPU

pure

con

text switc

h

DRAM

late

ncy

1 by

te tr

ansfer

fast e

ther

net

zero

mes

sage

tran

sfer

appl le

vel n

etwor

k

mes

sage

exc

hang

e

appl le

vel m

essa

ge

exch

ange

appl le

vel fun

ction

resp

onse

hum

an re

actio

n tim

e

hum

an e

ye

FO4

inve

rter d

elay

DRAM

cyc

le tim

e

100

Hz TV

fram

e

100H

z vide

o

pixe

l tim

e

100H

z vide

o lin

e

from

low level to high level

processing times

from low to high level

storage/network

application

needs

light

travels

1 cm

The realization view22 Gerrit Muller

version: 0.1September 6, 2020

RVtimeAxis

Page 23: Module Design Side - gaudisite.nl

Typical micro benchmarks for timing aspects

object creation

object destructionmethod invocation

component creation

component destruction

open connection

close connection

method invocationsame scope

other context

start session

finish session

perform transaction

query

transfer data

function call

loop overhead

basic operations (add, mul, load, store)

infrequent operations,

often time-intensive

often repeated

operations

database

network,

I/O

high level

construction

low level

construction

basic

programming

memory allocation

memory free

task, thread creationOS task switch

interrupt response

HW cache flush

low level data transfer

power up, power down

boot

The realization view23 Gerrit Muller

version: 0.1September 6, 2020

RVuTimingBenchmarks

Page 24: Module Design Side - gaudisite.nl

The transfer time as function of blocksize

tim

e

blocksize

worst case

optimal block-size

toverhead

rate-1

The realization view24 Gerrit Muller

version: 0.1September 6, 2020

RVparametrizedTransferRate

Page 25: Module Design Side - gaudisite.nl

Performance evaluation

overhead

trecon = nraw-x * ( tfft(nraw-y)

ny * ( tfft(nraw-x)

tfilter(nraw-x ,nraw-y) + +

+

tfft(n) = cfft * n * log(n)

filter FFT FFTcorrections

tcol-overhead

tcorrections(nx ,ny)trow-overhead +tcontrol-overhead+

) +

) +

nraw-x

nraw-y

nraw-x

nraw-y

nraw-x

ny

FFT computations

column overhead

FFT computations

row overheadcorrection computations

overhead

filter computations

read I/O

write I/O

malloc, freetranspose

bookkeeping

number crunching

overhead

focus on overhead

reduction

is more important

than faster algorithms

this is not an excuse

for sloppy algorithms

readI/O

writeI/O

trans-pose

nraw-x

ny

nx

ny

nx

ny

tread I/O +twrite I/O+ttranspose

The realization view25 Gerrit Muller

version: 0.1September 6, 2020

RVreconstructionPerformanceAnalysis

Page 26: Module Design Side - gaudisite.nl

Performance Cost, input data

100

200

150

250

1.5 2.0 2.51.00.50.010020 40 60 80 120

5400 rpm

7200 rpm

7200 rpm,

8 MB buffer

50

$

pentium4

so

urc

e:

http

://w

ww

.mp

co

mp

.co

m/

Se

pte

mb

er

5, 2

00

2

GHzGByte

performance

performance / cost

storage capacity

performance / cost

processing performance

The realization view26 Gerrit Muller

version: 0.1September 6, 2020

RVperformanceCost

Page 27: Module Design Side - gaudisite.nl

Performance Cost, choice based on sales value

100

200

150

250

1.5 2.0 2.51.00.50.010020 40 60 80 120

5400 rpm

7200 rpm

7200 rpm,

8 MB buffer

50

$

pentium4

so

urc

e:

http

://w

ww

.mp

co

mp

.co

m/

Se

pte

mb

er

5, 2

00

2

GHzGByte

performance

sales value

processing performance

sales value

storage capacity

The realization view27 Gerrit Muller

version: 0.1September 6, 2020

RVperformanceCostChoice

Page 28: Module Design Side - gaudisite.nl

Performance Cost, effort consequences

complex

compression

simple

compression

100

200

150

250

1.5 2.0 2.51.00.50.010020 40 60 80 120

50

$so

urc

e:

http

://w

ww

.mp

co

mp

.co

m/

Se

pte

mb

er

5, 2

00

2

GHzGByte

performance

effort needed

to obtain required

storage capacity

effort needed

to obtain required

processing performance

no compression

man-year

5

10

15

20

5400 rpm

7200 rpm

7200 rpm,

8 MB buffer

pentium4

The realization view28 Gerrit Muller

version: 0.1September 6, 2020

RVperformanceCostEffort

Page 29: Module Design Side - gaudisite.nl

But many many other considerations

costprocessing

performance

storage

capacity

image

quality

effort

time to market

user value

risk

future

evolution

1

2

3

rest of

system

system

context

2

3

The realization view29 Gerrit Muller

version: 0.1September 6, 2020

RVcostPerformanceIssues

Page 30: Module Design Side - gaudisite.nl

Safety, Reliability and Security analysis methods

potential hazardssafetyhazard analysis

reliabilityFMEA

failure modes

security vulnerability risks

probability

severity

effects

consequences

measures

measures

measures

analysis andassessment

(systematic)brainstorm

improvedesign

The realization view30 Gerrit Muller

version: 0.1September 6, 2020

RVanalysisSRS

Page 31: Module Design Side - gaudisite.nl

Exercise Design Side

Make a first design:• decomposition in functions• decomposition in building blocks• budgets for most important quality requirements

Exercise Design Side31 Gerrit Muller

version: 0.1September 6, 2020

MCRVexercise

Page 32: Module Design Side - gaudisite.nl

Exercise Design Side, second iteration

• Make a design:

• that covers the most critical design aspects

• that fulfills the most important and valuable customer needs

• Make a presentation of the design of maximal 8 sheets.

Exercise Design Side32 Gerrit Muller

version: 0.1September 6, 2020

MCRVexercise2


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