Mos Logic

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MOS Logic and Gate Circuits

A

Y

A

B AB

A

A

Wired OR

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` Introduction

` NMOS Logic` Resistive Load

` Saturated Enhancement Load

` Linear Enhancement Load

` Depletion Load

` Some Gates

` Transient in NMOS Circuit` Pseudo-NMOS

` CMOS Logic` Static CMOS Logic Gates

NOT NAND NOR

Realization of More Complicated Gate Circuits

` Transmission Gates Family NMOS Only Switch CMOS

` Differential Cascode Voltage Switch Logic

` Rules of Thumb

`Summary

Contents

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`The MOS inverter is the basic circuit exhibits all of theessential features of MOS Logic. Extension of MOS inverter

concepts to NOR and NAND Gate is very simple. In this

lecture we will analysis for VTC, NM, PD, . Both NMOS

and CMOS circuits are considered. Digital MOS circuits can

be classified into two categories:

` Static Circuits: require no clock or other periodic signal for

operation. Clocks are required for static circuit in sequential

logic

` Dynamic Circuits: require periodic clock signals, synchronizedwith data signals, for proper operation even in combinational

logic

Introduction

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Vdd+

Vo

Vi

RL

Vo

Vio

OLV

Vdd

NMOS Logic

`Resistive Load

WVoL C Speed

L

P RL Area

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NMOS Logic

`Resistive Load Properties` N transistors + Load

` VOH = Vdd

` VOL = Vdd ( rN/(rN + RL))

` Assymetrical response

` Static power consumption

` tPL = 0.69RLCL

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Vo

Vi

Vdd+ Vdd+

M2

M1Vo

Vio

OLV

OHV

Vo1

Vi

=

R

ILV

IHV

NMOS Logic

`Saturated Enhancement Load

T2

Vds2 Vgs2

Vds2 Vgs2 V

M2 is in saturation

=

>

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`Saturated Enhancement Load` VIL

IL T1

2 21 T1 2 T2

I 1

T

R

L

2

T

R

V V M1, M2 are in saturation

K (Vgs1 V ) K (Vgs2 V ) ,V Cte

VoVgs1 Vi, Vgs2 Vdd Vo , 1

Vi

Vo

1Vi V V

=

= = = >

NMOS Logic

Vo

Vio

OLV

OHV

Vo1

Vi

=

R

ILVIHV

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`Saturated Enhancement Load` VOL

VOL is difficult to obtainbecause it is the output

voltage when input equal to

VOH, the resulting expressionis a fourth order polynomial!

NMOS Logic

Vo

Vio

OLV

OH

V

Vo1

Vi

=

R

ILV

IHV

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NMOS Logic

( )

( )

1

1

2

1 1 T1

2

2 2 T2

1

1

iVords1 rds2

Vi ViVo

rds1 rds2 rds1i

i K Vgs1 V Vo Vo 2

1i K (Vgs2 V )2

iK Vo

Vi

=

=

=

=

=

`Saturated Enhancement Load` VIH

M1 is in triode and M2 in saturation

( )1 1 T1

1

1 T1

T1

IH T1

IH

iK Vgs1 V Vo

VoK VoVo

1Vi K (Vgs1 V Vo)

Vi VVo

2

V VVi V Vo

2

=

= =

=

= =

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( )

1 2

2 2

1 IH T1 2 T2

T2

IH T1R

i i

1K V V Vo Vo 2 K (Vdd Vo V )

2

2(Vdd V )V V

3 1

=

=

= +

+

NMOS Logic

`Saturated Enhancement Load` VIH

M1 is in triode and M2 in saturation

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IL OL

OH IH T2 IH

NML V V Some tenth of volt

NMH V V Vdd V V

=

= =

NMOS Logic

`Saturated Enhancement Load` NM

` Power

disH disL d

dis d

P 0, P I Vdd

P 1 2I Vdd

=

=

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Vo

Vi

VGG

Vdd+

M2

M1

NMOS Logic

`Linear Enhancement Load

Linear Enhancement Load

T2VGG Vdd V

M2 is in triode

+

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NMOS Logic

Vo

Vio

OLV

Vdd

ILV

IHVTV

Vdd

`Linear Enhancement Load` VTC

By this circuit the VOHcan be increased (or Vdd

can be decreased

because Vomax = Vdd )

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`Linear Enhancement Load` VIL

M1 is in saturation and M2 in triode

` VIH M1 and M2 are in tr iode

( )

( )

1 1

1

2

2 2 T2

22 T2

i iVo Vds2rds2

Vi Vi Vi ii K Vgs2 V Vds2 Vds2 2

iK VGG Vo V Vds2

Vds2

= =

=

=

( )

2

1 1 T1

11 T1

1 T1

2 T2

IL

1i K (Vi V )

2

iK Vi V

Vi

K (Vi V )Vo1

Vi K (VGG Vo V Vds2)

V f (Vo)

=

=

= =

=

NMOS Logic

rds2 rds1 rds2

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R

NMOS Logic

`

Linear Enhancement Load` Disadvantages:

More chip area is required (since an extra voltage source VGG)

Additional interconnection on the chip is needed

The required value of is even larger than a saturated load

Vo

Vi

VGG

Vdd+

M2

M1

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NMOS Logic

`Depletion Load` Ion implantation processing step is needed to create

depletion device, but overcome the disadvantages of

the previous circuit

Vo

Vi M1

Vdd+

M2

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NMOS Logic

`Depletion Load` VTC

` Therefore M2 is in triode

1 1 2

22

2 T2 2

Vi Low i 0, M1 in cutoff i i 0

K

if M2 is in saturation then i (Vgs2 V ) , Vgs2 0 i 02

= = = =

= = >

Vo

Vio

OLV

Vdd

ILV

IHVTV

Vdd

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`Depletion Load` VOL, VIL, VIH

NMOS Logic

( )

( )

2 221 OH T1 OL OL T2 OL

1 T11 2 IL

2 T2

2 221 1 IH T1 2 T2 IH

KK V V V V 2 (0 V ) V ?

2

K (Vgs1 V )Vo1 1, i i V ?

Vi K (Vgs2 V Vds2)

K Voi K V V Vds1 Vds1 2 i (0 V ) , 1 V ?

2 Vi

= =

= = = =

= = = = =

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`Some Gates` In all previous structures which different only in load,

the following Gates can be implemented. Note that the

NMOS Gates are not available as separately packaged

individual circuits, but they are used extensively in LSI

systems

NOR Gates

NAND Gates

NMOS Logic

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`Some Gates` NOR Gate

NMOS Logic

A M1

Y

B M2

Vdd+

RLY

A

B

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`Some Gates` NAND Gate

NMOS Logic

B

A

Vdd+

M2

M1

Y

RL

A

B

Y

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`Some Gates` In NOR Gate two transistors are paralleled but in

NAND Gate two transistors are in series. Because of

the need for increased area when adding NAND inputs,

NAND logic with more than 2 inputs is not

economically be attractive in NMOS. NOR logic is

preferable

` In NAND the M2 has body effect

` In NOR we need the less interconnection (this can be

shown from layout)

NMOS Logic

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NMOS Logic

` Transient in NMOS Circuits

` Saturated Enhancement Load

tot L d sub1 s sub2C C Ceq Ceq Cgs2 Cgd 2 1 = + + + +

Vdd+Vdd+

M1

M2

Vi

Cgs2

Cgd1

s sub2

C

d sub1C

CL

Vo

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` Super Buffer (1)

` If Fan-out is very large then

Cto t will be large. For

reduction it and decrease the

switching time the Super

Buffer circuit is used

` In this circuit if Vi is Lowstate then V1 will be high

very more rapid than Vo.

Thus the Gate of M2 is in

high state very rapidly.

Therefore M2 will be insaturation which result the

reduction of switching time

(ton)

M1

Vdd+

M4

Vo

M3

Vdd+

M2

Vi

V1

NMOS Logic

Super Buffer (1) Circuit

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` Super Buffer (2)

` It is non-Inverting

` Describe the operation of

this circuit!

NMOS Logic

Super Buffer (2) Circuit

M1

Vdd+

M4

Vo

M3

Vdd+

M2

Vi

V1

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`Pseudo-NMOS` What makes a circuit fast?

I = C dV/dt -> tpd (C/I) DV

low capacitance

high current small swing

` Logical effort is proportional to C/I

` PMOS are the enemy!

High capacitance for a given current` Can we take the PMOS capacitance off the input?

` Various circuit families try to do this

NMOS Logic

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`Pseudo-NMOS` In the old days, NMOS processes had no PMOS

Instead, use pull-up transistor that is always ON

` In CMOS, use a PMOS that is always ON

Make PMOS about effective strength of pulldownnetwork

NMOS Logic

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` Pseudo-NMOS

` Uses a p-type as a resistive pullup, n-type network for

pulldowns

NMOS Logic

Vi M1

Vdd+

Vo

M2

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` Pseudo-NMOS Characteristics

` Compared to CMOS, thisfamily has higher packingdensity, since for n inputs onlyn+1 transistors are required

` The main disadvantages with

Pseudo-NMOS Gates is thelarge static power dissipationthat occurs whenever a pull-down path is activated

` Has much smaller pullup

network than static gate` Pulldown time is longer

because pullup is fighting

NMOS Logic

Vi M1

Vdd+

VoM2

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` Pseudo-NMOS Output Voltages

` Logic 1 output is always at Vdd

` Logic 0 output is above Vss

` VOL = 0.25 (Vdd - Vss) is one

plausible choice

Vi M1

Vdd+

VoM2

NMOS Logic

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` Pseudo-NMOS Design Topics

` For logic 0 output, pullup and

pulldown form a voltage divider

` Must choose n, p transistor

sizes to create effective

resistances of the requiredratio

` Effective resistance of

pulldown network must be

computed in worst case

series n-types means largertransistors Vi M1

Vdd+

VoM2

NMOS Logic

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NMOS Logic

` Pseudo-NMOS Transistor Ratio Calculation

` MOSFET sizing is important

` Need to have reasonable W/L ratios for circuit to work

correctly

` VOL>VSS but must be low enough to turn off/on next

MOSFET in the chain` Static current drain when on

` Vout is a function of the number of parallel and series N

channels in the pull down network

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NMOS Logic

` Pseudo-NMOS Transistor Ratio Calculation

` For single supply

( ) ( )

OH

2 2OL P

n Tn OL TP

p

OL n T 2

n

T Tn Tp

OL p n

V Vdd, For the worst case one NMOS to be on

V KK Vdd V V Vdd V2 2

KV K (Vdd V ) 1 1

K

Assuming that V V V

V 0 K K

=

=

=

= =

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0.0 0.5 1.0 1.5 2.0 2.50.0

0.5

1.0

1.5

2.0

2.5

3.0

Vin

[V]

Vout

[V]

W/Lp = 4

W/Lp = 2

W/Lp = 1

W/Lp = 0.25

W/Lp = 0.5

NMOS Logic

` Pseudo-NMOS VTC ( W/Ln=1)

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` Pseudo-NMOS Gates

` Design for unit current on output

` PMOS fights NMOS

f

inputs

Y

NMOS Logic

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` Pseudo-NMOS Power

` Pseudo-NMOS draws power whenever Y = 0

Called static power P = IVDD

A few mA / gate * 1M gates would be a problem

This is why NMOS went extinct!

` Use Pseudo-NMOS sparingly for wide NORs

` Turn off PMOS when not in use

A B

Y

C

en

NMOS Logic

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Out

In1 In2 In3 In4

NMOS Logic

` Pseudo-NMOS ( NAND) Layout Example

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` Static CMOS Logic Family

` All of the circuits described in the previous sections

have a large static power dissipation. This

disadvantage can be overcome by using Static CMOS

Logic Family

CMOS Logic

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Vi

M1

Vdd+

Vo

M2

CMOS Logic


` NOT

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CMOS Logic


` Two inputs NAND

M3

B M2

Y

M4

Vdd+

A M1

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CMOS Logic


` Two inputs NOR

Y

A

B

Vdd+

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CMOS Logic


` NAND is more suitable for CMOS because by suppose

the equal W/L for NMOS and PMOS transistors, the

PMOS transistor has more resistance respect to

NMOS, therefore it is better to design circuit by

paralleling the PMOS and cascading the NMOS

` The better Technology for digital circuit is N-Well,

because in this Technology the NMOS transistors are

made in the Sub. Which result better characteristic for

transistor

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` Realization of More Complicated Gate Circuits

` a) Y = A(B+C)

` It can be implemented in three levels:

Gate Level

Transistor Level

Layout Level

CMOS Logic

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` a) Y = A(B+C)

Gate Level It consists of10 transistors, 4 transistors for NOR, 2 for NOT and 4 for

NAND

A

YB

C

CMOS Logic

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` a) Y = A(B+C)

Transistor Level It need on ly 6 transistors

A

B

C

Vdd+

Y

A

B C

CMOS Logic

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` a) Y = A(B+C)

Layout Level By proper construction of layout, the parasitic capacitors are also

reduced and area can be saved

CMOS Logic

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` b) XNOR (Y = AB + AB)

Gate Level 16 transis tors are needed

A

B

Y

CMOS Logic

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` b) XNOR (Y = AB + AB)

Transistor Level (1) How many transistors are

needed?

Vdd+

A

A

A

A

B

BB

B

Y AB AB= +

CMOS Logic

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` b) XNOR

Transistor Level (2) Previous circuit can be

simplified by eliminating

two wiring lines

Vdd+

A

A

A

A

B

BB

B

Y AB AB= +

CMOS Logic

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` b) XNOR Transistor Level (3)

In this circuit we havestatic power dissipationin the state of (A=0,B=1)or (A=1,B=0)

A

M1

Vdd+

M3Y AB AB= +

M2

B

CMOS Logic

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` b) XNOR Transistor Level (4) (For less dissipation)

Note to the state of A = B = Vdd

A

M1

Vdd+

M3

Y AB AB= +

M2

B

M4

Vdd-VthVddVdd

00Vdd

0Vdd0

Vdd00

YBA

CMOS Logic

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` c) XOR

As Previous the Source and Drain of M3 (or M4) arereplaced by each other in different states, for example in

state of A=0, B=0 the b connection of M3 is Source

0VddVdd

Vdd0Vdd

Vdd-VthVdd0

Vth00

YBA Vdd+

A B

M1

M2M3

M4

Y AB AB= +

A

a

a

b

b

CMOS Logic

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` d) Tri-State Outputs

A floating state at the output is needed Non-Inverting

D

En

Y

D

Vdd+En

Y

En 1 Y D

En 0 Y Hi Z

= = = =

CMOS Logic

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` d) Tri-State Outputs

A floating state at the output is needed Inverting

En 1 Y Hi Z

En 0 Y D

= = = =

D

En

Y

Vdd+

D

En

Y

CMOS Logic

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` Realization of More Complicated

Gate Circuits

` e) Schmitt Trigger M3 and M6 have minimum sized

geometries

With Vin = 0 , the transistors M1 and

M2 will be on but conductingnegligible Drain current since M4

and M5 are off

Vdd+

Vin Y

Vdd+

M5M6

Vz

M4

Vy

M2

M3M1

Vx

TN

Vy Vx Vdd

Vy Vdd M6 on Vz Vy V

=

CMOS Logic

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` Realization of More Complicated

Gate Circuits` e) Schmitt Trigger

When Vin rise to VTN, M5 turns on,but M4 is off. M5 and M6 form an

NMOS amplifier. Thus as Vin rises,

Vz is fall ing and in the certainvoltage M4 turns on. With both M4

and M5 conducting, Vy rapidly goes

to zero turning off M6. With Vy=0, M3

turns on, which aids in turning off

M2 as Vx goes from Vdd to Vy-VTP

As Vin decrease from Vdd to zerothe operation is essentially similar.But now M1 turns on, in different

voltage and

Vdd+

Vin Y

Vdd+

M5M6

Vz

M4

Vy

M2

M3M1

Vx

CMOS Logic

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` Transmission Gates Family

` Use pass transistors like switches to do logic

` Inputs drive diffusion terminals as well as gates

` N transistors instead of2N

` No static power consumption

` Ratioless

` Bidirectional

CMOS Logic

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` NMOS Only Switch

CMOS Logic

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]

V

oltage

[V]

x

Out

In

Vdd X

In

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` NMOS Only Switch

VB does not pull up to 2.5V, but 2.5-VTN Threshold voltage loss causes (M2 may be weakly

conducting forming a path from Vdd to GND)

NMOS has higher threshold than PMOS (body effect)

CMOS Logic

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CMOS Logic


` NMOS Only Switch

Pass transistor gates should neverbe cascaded as onthe left

Logic on the right suffers from static power dissipation

and reduced noise margins

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` NMOS Only Switch

Solution1: Level Restoring Transistor

CMOS Logic

M2

M1

n OutA

B

VVdd

X

M

M

Mr

OutA

B

VddV

Level Restorer

X

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` NMOS Only Switch

Solution1: Level Restoring Transistor

` Advantages

Full swing on x (due to Level Restorer) so no static power

consumption by inverter No static backward current path through Level Restorer and PT

since Restorer is only active when A is high

Restorer adds capacitance, takes away pul l down current at X

` For correct operation Mr must be sized correctly (ratioed)

CMOS Logic

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` NMOS Only Switch

Solution2: Multiple VT Transistors

CMOS Logic

Out

In2 = 0V

In1 =2.5V

A = 2.5V

B = 0V

low VT

transistors

sneak path

on

off but

leaking

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` NMOS Only Switch

Solution2: Multiple VT Transistors

` Technology solution: Use (near) zero VT devices for the

NMOS TGs to eliminate most of the threshold drop (body

effect still in force preventing full swing to Vdd)` Impacts static power consumption due to subthreshold

currents flowing through the TGs (even if VGS is below VT)

CMOS Logic

Out

In2 =0V

In1 =2.5V

A =2.5V

B =0V

low VT transistors

sneak path

on

off butleaking

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` NMOS Only Switch

Disadvantage: It can be bad because the signal can be degraded

We do not allow a few gates in series for one signal (Pure TG logicis not regenerative, the signal gradually degrades after passing

through a number of TGs)

Advantage: Al low us to save transistor or less stage of logic

CMOS Logic

ZA

B

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` CMOS Transmission Gates Family

` PMOS

` CMOS

A Y

C

CMOS Logic

C

C

A Y A Y

C

C

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` There are many symbols for transmission gate

` Be careful, because it is bi-directional

B'

B

A Z

B'

B

A Z

B

A Z

OR

B'

A Z

BOOK ME

CMOS Logic

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` This circuit performs a function similar to that of the well known diode bridge

` The input voltage VA (which must be between Vss and Vdd) is then

connected to the output through the parallel on resistance of the channels of

the two transistors. As VA approaches Vdd, the N-channel device cuts off but

the P-channel device remains non saturated, as VA approaches Vss, the P-channel device cuts off but the N-channel device remains non saturated.

Therefore there is always a non saturated transistor between input and output

CMOS Logic

C

C

A Y A Y

C

C

C Vss, C 0 Both transistor are on A Y= = =

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C

C

A Y

CL

PI

NI

S

D

t

VA

Vdd

Vy


` For more understanding note to this circuit` We assume:

CMOS Logic

TP TNVy(0 ) 0, C Vdd, C 0, V Vdd V = = = <

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C

C

A Y

CL

PI

NI


CMOS Logic

TP

TP TN

TN

CL N PVy V

PVy V Vy Vdd V

PVy Vdd V Vy Vdd

N sat0 t t I I I

P sat

N satt t t r CL

P triode

N offt t t r CL

P triode

=

= =

= =

= = +

=

=

==

=

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C

C

A Y

CL

PI

NI


` It is normally assumed as a resistor

CMOS Logic

A

TG

TG TG

TG N P

V (t) Vddu(t)

tVy(t) Vdd 1 exp u(t)

R CLR r r

=

=

==

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` rN and rP are approximately as follow (In saturation region)

AN

N 2

N TN

APP 2

P TP

A

2Vr

(Vdd V )2V

r(Vdd V )

V is Early Voltage

CMOS Logic

R

VyTPV TNVdd V Vdd

Pr Nr

TG N PR r r=

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` What to note about TG The inputs must be able to give high current because they are

connected directly to Drain and Source of transistors

Since each input is connected to an RC circuit, The delay canbe considered directly

Limited Fan-in

Excessive Fan-out

Noise vulnerability (not restoring)

Supply voltage offset/bias vulnerabil ity

Poor high voltage levels if NMOS-only

Body effect

CMOS Logic

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` Rules of Thumb Pass-Logic may consume half the power of static logic. But be

careful of VT drop result ing in static leakage

Pass-Gate Logic is not appropriate when long interconnectsseparate logic stages or when circuits have high Fan-out load

(use buffering)

CMOS Logic

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` AND

CMOS Logic

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` OR

Y A AB (A A)(A B) A B= + = + + = +

CMOS Logic

A

Y

A

B AB

A

A

Wired OR

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` MUX

A S 1Y

B S 0

==

=

CMOS Logic

A

Y

S

B

S

S

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` MUX

CMOS Logic

GND

Vdd

In1 In2S S

S S F

1 2F (In S In S)= +

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` XOR

CMOS Logic

A

Y A B=

B

B

B

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` XNOR

CMOS Logic

A

Y AB AB= +B

B

B

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` D Latch

CMOS Logic

D

LD

Q

Q

n n

n n-1

1) Load Q D

2) Hold Q Q

=

=

DQ

LD

LD

LDLD

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` D Latch

CMOS Logic

1) Load LD 1=

2) Hold LD 0=

D Q D=

D Q=

Q

Q

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` D Latch (Simpler Realization) If in Load Mode a level voltage opposite to the output of weak

inverter is applied to the input by TG, Q = D and weak inverter

is not damaged!

CMOS Logic

DQ

LD

LD

QWeak Inverter

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C C C C C C

e qR e qR e qR e qR e qR eqR

In

m644474448

C C C C C C

e qR e qR e qR e qR e qR e qRIn

1V 2V iV i 1V + n 1V nV

C C C C C C

In1V 2V iV i 1V + n 1V nV

CMOS Logic

` Delay in Transmission Gate

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` Delay Optimization

` Delay of RC chain

` Delay of Buffered chain

n

P e q eq

k 1

n(n 1)t 0.69 CR k 0.69C R

2=

+= =

CMOS Logic

P e q buf

e q buf

Pbuf

opt

e q

n m(m 1) nt 0.69 CR 1 t

m 2 m

n(m 1) n0.69 CR 1 t

2 m

tm 1.7

CR

+ = +

+ = +

=

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CMOS Logic

` TG Points to Remember

` Stored charge leaks away due to reverse-bias leakagecurrent

` Stored value is good for about 1 ms

` Value must be rewritten to be valid

` If not loaded every cycle, must ensure that latch isloaded often enough to keep data valid

` Capacitance comes primarily from inverters gate logic

CMOS L i

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CMOS Logic

` TG Layout

CMOS L i

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CMOS Logic

` TG Properties

` Strong pull-up

` Strong pull-down

` May be difficult to design into a circuit (layout) because

of close proximity of N and P devices (design rule

separation)` Always requires 2N transisitors for any N x TG design

` Many logic functions (multiplexers in particular) are

easily implemented using TG based designs

CMOS L i

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` Complementary Pass-transistorLogic (CPL) or

Differential (+) TG Logic` Dual-rail form of pass transistor logic

` Avoids need for ratioed feedback

B

S

S

S

S

A

B

AY

YL

L

CMOS Logic

A

B

AB

PT NetworkF

A

B

AB

Inverse PTNetwork F

F

F

CMOS L i

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CMOS Logic

` CPL

A

A

B

B

B B

AND/NAND

A

A

B

B

B B

AND/NAND

A

A

B

BB

B BB

AND/NAND

CMOS L i

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CMOS Logic

` 4 Input NAND in CPL

CMOS Logic

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CMOS Logic

` CPL Advantages

` Differential so complementary data inputs and outputsare always available (so dont need extra inverters)

` Still static, since the output defining nodes are always

tied to Vdd or GND through a low resistance path

` Design is modular, all gates use the same topology,only the inputs are permuted

` Simple XOR makes it attractive for structures like

adders

` Fast (assuming number of transistors in series is small)

CMOS Logic

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CMOS Logic

` CPL Disadvantages

` Additional routing overhead for complementary signals` Stil l have static power dissipation problems

` VOH is very weak! Then we need an inverter at the

output

CMOS Logic

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` Differential Cascode Voltage Switch Logic (DCVSL)

`Compute both true and complementary outputs using a pair ofcomplementary NMOS pull-down network

` The PMOS transistors are driven by the output of the

complementary network

` No static power consumption

`Fast response

CMOS Logic

Inputs

Y Y

f f

CMOS Logic

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` Example: NAND/AND

CMOS Logic

Y AB=

BA

A

B

Y A B= +

Series

CMOS Logic

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` General Design

1111 1011

1101000111100010 0100

1000FCBA

CMOS Logic

+ + + +

++

+

_ _ _ _

__

_A

B

C

0 1

CMOS Logic

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` General Design

+_x

a b

u

x x

a b

uu ax bx= +

CMOS Logic

+_

x

u

u

+_

x

a b

1u

+_

a b

2u

+_x

a b

1u

2u

CMOS Logic

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` General Design

+ + + +

++

+

_ _ _ _

__

_A

B

C

0 1

CMOS Logic

+ +

++

+

_ _

__

_A

B

C

0 1

CMOS Logic

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`Example: XOR/XNOR

CMOS Logic

CMOS Logic

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` Rules of Thumb

` Step-up (alpha) ratio of 2.7 (e ) produces minimum power-delay product

` P vs. N (beta) ratio of 2 balances pull-up and pull-down

times and noise margins

` Approximately 75% of static logic are NAND stacks (limit

stack to 3-4, use ordering and tapering for speed)

` Glitches consume approximately 15% of overall chip power

` Crossover (short-circuit) current consumes ~ 10% of a

static chips total power (but is a function of input/output

slews, ie sizing)

CMOS Logic

Summary

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Summary

` This lecture describes the basic MOS Logic

Gates which require no clock or other periodicsignal for operation and also implementation of

them in three following levels

` Gate Level

` Transistor level

` Layout Level

Contents

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Contents

` Introduction

` Dynamic CMOS Logic` CMOS Domino Logic

` CD Domino Logic

` Dynamic CVSL` Sample-Set Differential Logic (SSDL)

` Summary

Introduction

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` As mentioned before Digital MOS circuits can be classifiedinto two categories:

` Static Circuits: require no clock or other periodic signal foroperation (except sequential logic). In these circuits at everypoint in time (except when switching) the output is connectedto either GND or Vdd via a low resistance path

` fan-in of N requires 2N devices (n N-type + n P-type)

` Dynamic Circuits: require periodic clock signals, synchronizedwith data signals, for proper operation even in combinationallogic. These circuits rely on the temporary storage of signalvalues on the (parasitic) capacitance of high impedance nodes

` requires only N + 2 transistors (n+1 N-type + 1 P-type)` takes a sequence of precharge and conditional evaluation

phases to realize logic functions

Introduction

Introduction

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` Why Dynamic Logic?

` In the area of high speed, higher Fan-in, extremely lowpower dissipation, other digital logic circuit have been

considered. In this lecture, two of these alternatives to

CMOS are described. The circuits are basically NMOS or

CMOS Gates with slight improvements. These are:

` Dynamic CMOS Logic

` CMOS Domino Logic

` Each of them have specific operating advantages over

NMOS or CMOS, but exhibit disadvantages in other areas

Introduction

Dynamic CMOS Logic

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` Dynamic Gates use a clocked PMOS pullup

` Two modes: precharge and evaluate

Precharge Evaluate

Y

Precharge

y g

Dynamic CMOS Logic

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` The Foot

` What if pulldown network is ON during precharge?` Use series evaluation transistor to prevent fight

AY

foot

precharge transistor

y g

Dynamic CMOS Logic

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y g


`To make the gate dynamic, aclock pulse is applied to the gate

of complementary P and N

channel devices. This gate

consists of an NMOS Logic circuit

whose output node is prechargedto Vdd by the PMOS, when the

clock is zero. The output node is

discharged by the NMOS

transistor connected to ground

when the clock is high

NMOS

LogicCircuit

CLKP

CLKN

CLK

Dynamic CMOS Logic

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Precharge (Clk = 0)Evaluate (Clk = 1)

y g

1

2

3

Me

Mp

LL


Dynamic CMOS Logic

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` Once the output of a dynamic gate is discharged, it cannotbe charged again until the next precharge operation

` Inputs to the gate can make at most one transition duringevaluation

` Output can be in the high impedance state during and afterevaluation (PDN off), state is stored on CL

y g

Dynamic CMOS Logic

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` Canonical Forms

Dynamic CMOS Logic

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` Properties of Dynamic Gates

`

Logic function is implemented by the PDN only should be smaller in area than static complementary CMOS

` Full swing outputs (VOL = GND and VOH = VDD)

` Nonratioed - sizing of the devices is not important for proper

functioning (only for performance)

` Faster switching speeds

reduced load capacitance due to lower number of transistors pergate (Cint) so a reduced logical effort

reduced load capacitance due to smaller fan-out (Cext)

no Isc

, so all the current provided by PDN goes into discharging

CL

Ignoring the influence of precharge time on the switching speedof the gate, tpLH = 0 but the presence of the evaluation transistor

slows down the tpHL

Dynamic CMOS Logic

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` Properties of Dynamic Gates

`

Power dissipation should be better consumes only dynamic power no short circuit powerconsumption since the pull-up path is not on when evaluating

lower CL- both Cint (since there are fewer transistors connectedto the drain output) and Cext (since there the output load is one

per connected gate, not two)

` But power dissipation can be significantly higherdue to

higher transition probabilities

extra load on CLK

` PDN starts to work as soon as the input signals exceed VTn,

so set VM, VIH and VIL all equal to VTn low noise margin (NML)

` Needs a precharge/evaluate clock

Dynamic CMOS Logic

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` Leakage Sources

`

Subthreshold conduction` Transistors cant abruptly turn

ON or OFF

` Reverse-biased PN junction

diode current

Is depends on doping levels And areaand perimeter of diffusion regions,

typically < 1 fA/m2` Gate Leakage

Carriers may tunnel thorough very thingate oxides

Negligible for older processes

VDD

0 0.3 0.6 0.9 1.2 1.5 1.8

10-9

10-6

10-3

100

103

106

109

tox

0.6 nm

0.8 nm

1.0 nm

1.2 nm

1.5 nm

1.9 nm

VDD trend

Dynamic CMOS Logic

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` Leakage Sources

` Output settles to an intermediate voltage determined by a resistive

divider of the pull-up and pull-down networks

` Once the output drops below the switching threshold of the fan-out

logic gate, the output is interpreted as a low voltage

-0.5

0.5

1.5

2.5

0 20 40

Time (ms)

V

oltage

(V)

CLK

Out

Dynamic CMOS Logic

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Leakage sources

CLK

VOut

Precharge

Evaluate

` Leakage Sources

` Subthreshold leakage is dominant in modern transistors

L

p

e

Dynamic CMOS Logic

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` Solution to Charge Leakage

LL

Me

Mp Mkp

Dynamic CMOS Logic

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` Charge Sharing

` Charge stored originally on CY is redistributed (shared) over CX

leading to static power consumption by downstream gates and

possible circuit malfunction

` When Vout = - Vdd (CX / (CX + CY )) the drop in Vout is large

enough to be below the switching threshold of the gate it drives

causing a malfunction

B = 0

A

Y

x

Cx

CY

A

x

Y

Charge sharing noise

= =+

Y

x Y dd

x Y

CV V V

C C

Dynamic CMOS Logic

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` Solution to Charge Redistribution

` Add secondary precharge transistors (at the cost of

increased area and power)

Typically need to precharge every other node

Secondary precharge transistors should be small because theirdiffusion capacitance slows the evaluation (increase delay)

Big load capacitance CY helps as well

B

A

Y

x

secondaryprechargetransistor

Dynamic CMOS Logic

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` Charge Sharing Example

` What is the worst case voltage drop on y? (Assume all

inputs are low during precharge and that all internal nodes

are initially at 0V)

Dynamic CMOS Logic

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` Charge Sharing Example

y

CLK

CLK

A A

B B B

CC

y = A B C

Ca =15fF

Cc =15fF

Cb =15fF

Cd =10fF

Loadinverter

a

b

dc

Cy =50fFy = A B C

Cd =10fFCd =10fF

Loadinverter

cB

( ) ( )( )( )

a c a c yVout Vdd C C C C C

2.5V 30 30 50 0.94V

= + + +

= + =

Dynamic CMOS Logic

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` Backgate Coupling

` Susceptible to crosstalk due to High impedance of the output node

Capacitive coupling Out2 capacitively couples with Out1 through the gate-source and gate-

drain capacitances of M4

CL1CL1

CLK

CLK

B=0

A=0

Out1Mp

Me

Out2

CL2CL2

In

Dynamic NAND Static NAND

=1=0

M1

M2M3

M4

M5M6

Dynamic CMOS Logic

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` Capacitive coupling means Out1 drops significantly so Out2

doesnt go all the way to ground

` Backgate Coupling

-1

0

1

2

3

0 2 4 6

Voltage

Time, ns

Clk

In

Out1

Out2

Due to backgate

Due to clk feedthrough

Dynamic CMOS Logic

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` Clock Feedthrough

` A special case of capacitivecoupling between the clock

input of the precharge transistor

and the dynamic output node

due to the gate to drain

capacitance

` So voltage of Out can rise above

Vdd. The fast rising (and falling

edges) of the clock couple to

Out

LL

Mp

Me

Dynamic CMOS Logic

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-0.5

0.5

1.5

2.5

0 0.5 1

In &Clk

Out

Time, ns

Voltag

e

Clock feedthrough

Clock feedthrough

` Clock Feedthrough

Dynamic CMOS Logic

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` Other Effects

` Capacitive coupling` Substrate coupling

` Minority charge injection

` Supply noise (Ground bounce)

` Floating output nodes

Dynamic CMOS Logic

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` Floating output nodes

`Solutions:

Only connect to gates

Add staticizer to refresh the charge

s

s

0

0

Dynamic CMOS Logic

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` Advantages:

` For n inputs, dynamic logic requires

n+2 transistors` have small area, high speed and

compact layouts

` Disadvantages:

` Circuit operation is more complex

due to the required clock

` The inputs can only change during

the precharge phase and must be

stable during the evaluate portion of

the cycle

` Need Monotonicity can not be cascaded

NMOS

Logic

Circuit

CLKP

CLKN

CLK

Dynamic CMOS Logic

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` Monotonicity

`Dynamic gates require monotonically rising inputsduring evaluation

Precharge Evaluate

Y

Precharge

A

Output should rise but does not

violates monotonicityduring evaluation

A

Dynamic CMOS Logic

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` Monotonicity Woes

` Dynamic gates produce monotonically falling outputs during

evaluation

` Illegal for one dynamic gate to drive another!

Precharge Evaluate

X

Precharge

A =1

Y shouldrise but cannot

Y

X monotonically falls duringevaluation

V

Dynamic CMOS Logic

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V

t

Clk

In

Out1

Out2V

VTn

Only 0 1 transitions allowed at inputs!

` Cascading

Dynamic CMOS Logic

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` Cascading

`Input going from high to low during evaluation

a is 5V when precharge b = 5V, c = 5V

During evaluation: Wanted: b 0V, c 5V But, b takes some time to drop to 0V

Consequently, c may fall to some unknown value

` Solution

` NP-CMOS

` NORA Logic

` Domino logic

a

cb

Dynamic CMOS Logic

` C OS

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` NP-CMOS

`Only 0 1 transitions allowed at inputs of PDN

` Only 1 0 transitions allowed at inputs of PUN

In1

In2 PDN

In3

Me

Mp

Clk

Clk Out1

In4 PUN

In5

Me

MpClk

Clk

Out2

(to PDN)

1 11 0

0 0

0 1

Dynamic CMOS Logic

` NORA L i

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` NORA Logic

`WARNING: Very sensitive to noise!

In1

In2 PDN

In3

Me

Mp

Clk

ClkOut1

In4 PUN

In5

Me

MpClk

Clk

Out2(to PDN)

1 11 0

0 00 1

to otherPDNs

to otherPUNs

` An e ample

Dynamic CMOS Logic

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` An example

Dynamic CMOS Logic

` D namic 4 Inp t NAND Gate

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In1

In2

In3

In4

Out

VDD

GND

` Dynamic 4 Input NAND Gate

` Power Consumption

Dynamic CMOS Logic

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1

2

3

e

p

LL

` Power Consumption

` Power only dissipated when previous Out = 0

` Power Consumption

Dynamic CMOS Logic

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011

001

010100

OutBA

` Power Consumption

` Dynamic Power Consumption is Data Dependent

Assume signal probabilities (Dynamic 2-input NOR Gate)

PA=1 = 1/2

PB=1 = 1/2

Then transition probability

P10 = Pout=0 =

` Switching activity can be higherin dynamic gates!

` Rules of Thumb

Dynamic CMOS Logic

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` Rules of Thumb` Dynamic logic is best for wide OR/NOR structure (e.g. bit-

lines), providing 50% delay improvement over static CMOS

` Dynamic logic consumes 2x power due to its phase activity

(unconditional pre-charging), not counting clock power

` Notes

Dynamic CMOS Logic

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` Notes

`

No need to implement the complement of the function,leading to smaller area

` We can avoid the long PMOS chains

` Handle the charge sharing problem and floating output

nodes

` Input transistors should not change from on to off

during evaluation

CMOS Domino Logic

` It is an extension of dynamic CMOS gates that allow

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` It is an extension of dynamic CMOS gates that allow

cascading of stages

` The simple modification entails incorporating a static

CMOS inverter at the output of each logic gate

A

W

B C

X Y Z

domino AND

dynamicNAND

staticinverter

In1In2 PDN

In3

Me

Mp

Clk

ClkOut1

In4 PDN

In5

Me

Mp

Clk

ClkOut2

Mkp

1 11 0

0 00 1

` Stage A should be precharged in 1 and evaluate in2

CMOS Domino Logic

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g p g 1 2

` Stage B should be precharged in 2 and evaluate in 1

` During precharge (clk=0), the output node of the dynamic

CMOS Domino Logic

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g p g ( ) p ygate is precharged high and the output node of the CMOS

inverter is low. Then subsequent stages will be turned offduring the precharge phase

` When the clk=1, the output of the driving gate willconditionally discharge, allowing the output of the inverterto conditionally go high. Each connected gate output canthen make a transition from low-to-high, in sequence

` There is no restriction on the number of logic stages that

can be cascaded provided that all stages can evaluateduring one clock pulse

` pc = 1 and ev = 2

CMOS Domino Logic

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n- network

ev

V

1

W

pc

2

X Y

` pc 1 and ev 2

cycle

1

2

precharge evaluate

input latched

here

output latched

here

pc = 1 ev = 2

` Wont work! If pc = 2 and ev = 1

CMOS Domino Logic

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p 2 1

cycle

1

2

precharge

evaluate

input latched

here

output latched

here

pc = 2 ev = 1

evaluate

precharge

CMOS Domino Logic

` Why Domino?

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y

` Like falling dominos!

` Produces monotonic outputs

CMOS Domino Logic

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p

Precharge Evaluate

W

Precharge

X

Y

Z

A

BC

C

AB

W XY

Z =X

ZH

H

A

W

B C

X Y Z

domino AND

dynamic

NAND

static

inverter

` Domino Optimizations

CMOS Domino Logic

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` Each domino gate triggers next one, like a string of dominos toppling

over` Gates evaluate sequentially but precharge in parallel Thus evaluation

is more critical than precharge

` HI-skewed static stages can perform logic

` Static inverter can be optimized to match fan-out

S0

D0

S1

D1

S2

D2

S3

D3

S4

D4

S5

D5

S6

D6

S7

D7

YH

` Leakage

CMOS Domino Logic

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` Dynamic node floats high during evaluation

Transistors are leaky (IOFF 0) Dynamic value will leak away over time

Formerly miliseconds, now nanoseconds!

` Use keeper to hold dynamic node

Must be weak enough not to fight evaluation

A

H

22

1 kX

Y

weak keeper

` Noise Sensitivity

CMOS Domino Logic

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` Dynamic gates are very sensitive to noise

Inputs: VIH Vtn Outputs: floating output susceptible noise

` Noise sources

Capacitive crosstalk

Charge sharing

Power supply noise

Feedthrough noise

And !

CMOS Domino Logic

` Designing with Domino Logic

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` If all the inputs come from other domino gates, then all the inputs will be low

during the precharge. You dont need to explicit evaluate transistor` Need to be a little careful. When precharge begins, the first gates output must

precharge before the next gate can precharge. Both evaluate and precharge

ripple in this scheme. But, if there is already a tall stack, transistor ratioing will

let precharge win anyway. (but you waste power until the precharge ripples)

` Example

CMOS Domino Logic

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` During precharge, x, y, z = 1, x, y = 0

` During evaluation, x = 0 when a = b = 1

` Therefore, z = a b c d

a

b

x

c

x

y

d

y z

` Advantages:` Large Fan-in, fewer transistors (n+4 transistors, whereas CMOS

CMOS Domino Logic

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g (requires 2n)

` Single clock can be used to precharge and evaluate all stages at thesame time

` It is attractive for high-speed circuits

` 1.5 2x faster than static CMOS

` Widely used in high-performance microprocessors

` Disadvantages:` Each logic block must incorporate a separate inverter

` Each block performs only non-inverting logic

` Monotonicity

` Leakage

` Charge sharing` Noise

` Dual Rail Domino

` Domino only performs noninverting

CMOS Domino Logic

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` Domino only performs noninverting

functions AND, OR but not NAND, NOR, or XOR

` Dual-rail domino solves this problem

Takes true and complementary inputs

Produces true and complementaryoutputs

invalid11

101

010

Precharged00

Meaningsig_lsig_h

Y_h

f

inputs

Y_l

f

` Example AND/NAND

` Given A h A l B h B l

CMOS Domino Logic

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` Given A_h, A_l, B_h, B_l

` Compute Y_h = A * B, Y_l = ~(A * B)

` Pulldown networks are conduction complements

Y_h

Y_l

A_h

B_hB_lA_l

= A*B= A*B

` Example XOR/XNOR

` S ti ibl t h t i t

CMOS Domino Logic

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` Sometimes possible to share transistors

Y_h

Y_l

A_l

B_h

= A xor B

B_l

A_hA_lA_h= A xnor B

` Rules of Thumb` Typical domino keepers have W/L = 5 20% of effective width

CMOS Domino Logic

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` Typical domino keepers have W/L = 5-20% of effective width

of evaluate tree

` Typical domino output buffers have a beta ratio of ~ 6:1 to

push the switch point higher for fast rise-time

` We noted that dynamic inputs never make 1 to 0

transitions while in evaluation

CD Domino Logic

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transitions while in evaluation

` Two solutions:

` Precharge outputs low using an inverting gate

(standard domino)

`Delay the evaluate clock until inputs settle (CDdomino)

` Self-timed dynamic logic family

`

CD Domino Logic

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`Consists of a dynamic gate, and an optionaldelay element for the clock signal

clk(i) clk(i+1)

delay

Out = a+b

Mpre

Meval

a b

clk(i) clk(i+1)

delay

Out = a+b

Mpre

Meval

a b

` Advantages` Uses single-rail circuits, rather than dual-rail for

CD Domino Logic

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` Uses single rail circuits, rather than dual rail for

standard domino` Provides both inverting and non-inverting functions

` High-speed, large fan-in NOR and OR circuits

CD Domino Logic

` Delay Matching` CD domino requires delay matching between the

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q y g

slowest dynamic gate at a level and a delay element` A 20% margin is typically added to the delay of the

fixed delay element to account for PVT variations

` Thus, 20% of the speed gain possible with CD domino

is not realized` Average speed gain of (60+20)% is theoretically

possible

` Use digitally programmable delay elements

(PDEs) to reduce the margin and attain a speedimprovement without affecting the reliability in

the presence of variations

` Clocking Scheme

` The circuits are fully levelized

CD Domino Logic

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` The circuits are fully levelized

` The delay element on each level is tuned to the

slowest gate at its level, plus a 20% margin

dynamic

gate

dynamicgate

dynamicgate

dynamicgate

dynamic

gate

dynamic

gate

fixed delay fixed delay fixed delayclk1 clk2 clk3 clk4gate level

1

gate level

3gate level

2

primary

inputs

(other gates)..(other gates)..

(other gates)..

dynamic

gate

dynamicgate

dynamicgate

dynamicgate

dynamic

gate

dynamic

gate

clk1 clk2 clk3 clk4gate level gate levelgate level




` Positive feedback does not exist

Dynamic CVSL

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{In }InC

F F

CNMOSLogic Array

` It is one type of Dynamic CVSL with positive feedback

` By this logic the low level output is guaranteed to zero in

Sample-Set Differential Logic (SSDL)

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evaluation phase

{In }In

C

F F

C

NMOS

Logic Array

Summary

` This lecture describes many basics CMOS Logic

Gates which require clock or other periodic

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q p

signal for operation

` These circuits rely on the temporary storage of

signal values on the (parasitic) capacitance of

high impedance nodes

Date post:	14-Apr-2018
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Mos Logic

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