MOS Models (5/23/00) Page 1
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
1.8 - MOSFET MODELS INTRODUCTION
Objective
The objective of this presentation is:
1.) Understand how the MOS transistor works
2.) Understand and apply the simple large signal model
3.) Understand and apply the small-signal model
Outline
• MOS Structure and Operation
• Large Signal Model
• Small-Signal Model
• Capacitance
• Short Channel Large Signal Model
• Subthreshold Large Signal Model
• Summary
MOS Models (5/23/00) Page 2
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
MOS STRUCTURE AND OPERATION Metal-Oxide-Semiconductor Structure
n+ n+
Polysilicon
p+
p- substrate
LightlyDoped p
HeavilyDoped n
HeavilyDoped p
LightlyDoped n
IntrinsicDoping Fig1.8-1
Bulk/Substrate Source Gate DrainThin Oxide(10-100nm
100Å-1000Å)
Metal
Terminals:
• Bulk - Used to make an ohmic contact to the substrate
• Gate - The gate voltage is applied in such a manner as to invert the doping of the material directlybeneath the gate to form a channel between the source and drain.
• Source - Source of the carriers flowing in the channel
• Drain - Collects the carriers flowing in the channel
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ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Formation of the Channel for an Enhancement MOS Transistor
Polysilicon
p+
p- substrate
Fig1.8-2
VB = 0 VG =VTVS = 0 VD = 0
n+ n+p+
p- substrate
VB = 0 VG < VTVS = 0 VD = 0
Polysilicon
p+
p- substrate
VB = 0 VG >VTVS = 0 VD = 0
Subthreshold (VG<VT)
Threshold (VG=VT)
Strong Threshold (VG>VT)
n+ n+
n+ n+
Inverted Region
Inverted Region
Polysilicon
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ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
The MOSFET Threshold Voltage
When the gate voltage reaches a value called the threshold voltage (VT), the substrate beneath the gatebecomes inverted (it changes from p-type to n-type).
VT = φMS +
-2φF - Qb
Cox +
QSS
Cox
whereφMS = φF(substrate) - φF(gate)
φF = Equilibrium electrostatic potential (Femi potential)
φF(PMOS) = - kTq ln(NA/ni) = -Vt ln(NA/ni)
φF(NMOS) = kTq ln(ND/ni) = Vt ln(ND/ni)
Qb ≈ 2qNAεsi(|-2φF+vSB|)
QSS = undesired positive charge present in the interface between the oxide and the bulk silicon
Rewriting the threshold voltage expression gives,
VT = φMS -2φF - Qb0
Cox -
QSSCox
- Qb - Qb0
Cox = VT0 + γ |-2φF + vSB | - |-2φF|
where
VT0 = φMS - 2φF - Qb0Cox
- QSSCox
and γ = 2qεsiNA
Cox
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ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Signs for the Quantities in the Threshold Voltage Expression
Parameter N-Channel P-ChannelSubstrate p-type n-typeφMS Metal − − n+ Si Gate − − p+ Si Gate + +φF − +Qb0,Qb − +Qss + +VSB + −γ + −
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ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Example 1 - Calculation of the Threshold Voltage
Find the threshold voltage and body factor γ for an n-channel transistor with an n+ silicon gate if tox =200 , NA = 3 × 1016 cm-3, gate doping, ND = 4 × 1019 cm-3, and if the positively-charged ions at theoxide-silicon interface per area is 1010 cm-2.
SolutionFrom above, φF(substrate) is given as
φF(substrate) = −0.0259 ln
3× 1016
1.45 × 101 0 = −0.377 V
The equilibrium electrostatic potential for the n+ polysilicon gate is found from as
φF(gate) = 0.0259 ln
4 × 1019
1.45 × 1010 = 0.563 V
Therefore, the potential φMS is found to be
φF(substrate) − φF(gate) = −0.940 V.
The oxide capacitance is given as
Cox = εox/tox = 3.9 × 8.854 × 10-14
200 × 10-8 = 1.727 × 10-7 F/cm2
The fixed charge in the depletion region, Qb0, is given as
Qb0 = − [2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 2 × 0.377 × 3 × 1016]1/2 = − 8.66 × 10-8 C/cm2.
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Example 1 - Continued
Dividing Qb0 by Cox gives −0.501 V. Finally, Qss/Cox is given as
QssCox
= 1010 × 1.60 × 10-19
1.727 × 10-7 = 9.3 × 10-3 V
Substituting these values for VT0 gives
VT0 = - 0.940 + 0.754 + 0.501 - 9.3 x 10-3 = 0.306 V
The body factor is found as
γ = 2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 3 × 1016
1/2
1.727 × 10-7 = 0.577 V1/2
MOS Models (5/23/00) Page 8
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
SIMPLE LARGE SIGNAL MOSFET MODEL
Large Signal Model Derivation
Derivation-
1.) Let the charge per unit area in the channel inversion
layer be
QI(y) = -Cox[vGS - v(y) - VT] (coulombs/cm2)
2.) Define sheet conductivity of the inversion layer per
square as
σS = µoQI(y)
cm2
v·s
coulombs
cm2 = ampsvolt =
1Ω/sq.
3.) Ohm's Law for current in a sheet is
JS = iDW = -σSEy = -σS
dvdy → dv =
-iDσSW dy =
-iDdyµoQI(y)W → iD dy = -WµoQI(y)dv
4.) Integrating along the channel for 0 to L gives
⌡⌠0
L
iDdy = - ⌡⌠0
vDS
WµoQI(y)dv = ⌡⌠0
vDS
WµoCox[vGS-v(y)-VT] dv
5.) Evaluating the limits gives
iD = WµoCox
L
(vGS-VT)v(y) - v2(y)
2
vDS 0
→ iD = WµoCo x
L
(vGS-VT)vDS - vDS2
2
n+ n+
yv(y)
dy
0 Ly y+dyp-Source Drain
+
-vGS
-iD+
vDS
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Saturation Voltage - V D S (sat)
Interpretation of the large signal model:iD
vDS = vGS - VT
Increasingvalues of vGS
Saturation RegionActive Region
vDS
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of the invertedparabolas.
diDdvDS
= µoCoxW
L [(vGS-VT) - vDS] = 0 → vD S (sat) = vG S - V T
Useful definitions:
µoCoxW
L = K’W
L = β
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ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Complete Large Signal Model
Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
iD = 0, vGS - VT < 0 (Ignores subthreshold currents)
2.) Active Region
iD = µoCoxW
2L [ ]2(vG S - V T ) - vD S vDS , 0 < vDS < vGS - VT
3.) Saturation Region
iD = µoCoxW
2L ( )vG S - V T 2 , 0 < vGS - VT < vDS
Output Characteristics of the MOSFET:
vDS = vGS - VT
iD /ID0
0.75
1.0
0.5
0.25
00 0.5 1.0 1.5 2.0 2.5
vGS-VTVGS0 - VT
= 0
vGS-VTVGS0 - VT
= 0.5
vGS-VTVGS0 - VT
= 0.707
vGS-VTVGS0 - VT
= 0.867
vGS-VTVGS0 - VT
= 1.0
Channel modulation effects
vDSVGS0 - VT
ActiveRegion Saturation Region
Cutoff Region
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ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Influence of V D S on the Output Characteristics
Channel modulation effect:
As the value of vDS increases, it causes the effective L to decrease which causes the current to increase.
Illustration:
Polysilicon
p+
p- substrateFig1.8-3
VG > VT VD > VDS(sat)
n+n+
DepletionRegion
Xd
B S
Leff
Note that Leff = L - Xd
Therefore the model in saturation becomes,
iD = K’W2Leff
(vGS-VT)2 →diD
dvDS = -
K’W2Leff
2 (vGS - VT)2 dLeffdvDS
= iD
Leff dXddvDS
≡ λiD
Therefore, a good approximation to the influence of vDS on iD is
iD ≈ iD(vDS=0) + diD
dvDS vDS = iD(vDS=0)(1 + λvDS) =
K’W2L (vGS-VT)2(1+λvDS)
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Influence of the Bulk Voltage on the Large Signal MOSFET Model
Illustration of the influence of the bulk:
VSB0 = 0V:
VSB1>0V:
VSB2 > VSB1:
Poly
p+ n+ n+
p-
+-
Bulk Source
Gate Drain
VDS>0VGS>VT
Substrate/Bulk
VSB0=0V
Poly
p+ n+ n+
p-
+-
Bulk Source
Gate Drain
VDS>0VGS>VT
Substrate/Bulk
VSB1
Poly
p+ n+ n+
p-
+-
Bulk Source
Gate Drain
VDS>0VGS>VT
Substrate/Bulk
VSB2
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Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-
vGS
iD Decreasing valuesof bulk-source voltage
VT0 VT1 VT2 VT3
VBS = 0
vDS vGS - VT
In general, the simple model incorporates the bulk effect into VT by the following empirically developed
equation-
VT(vBS) = VT0 + γ 2|φf| + |vBS | - γ 2|φf|
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MOSFET Schematic Symbols
Enhancement:
D
G
S
D
G
S
D
G
S
D
G
S
B
B
D
G
S
D
S
G
NMOS
PMOS
VBS ≠0V VBS=0V Simple
Fig1.8-4
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Summary of the Simple Large Signal MOSFET Model
N-channel reference convention:
Non-saturation-
iD = WµoCox
L
(vGS - VT)vDS - vDS2
2 (1 + λvDS)
Saturation-
iD = WµoCox
L
(vGS - VT)vDS(sat) - vDS(sat)2
2 (1 + λvDS) = WµoCox
2L (vGS - VT) 2 (1 + λvDS)
where:µo = zero field mobility (cm2/volt·sec)
Cox = gate oxide capacitance per unit area (F/cm2)
λ = channel-length modulation parameter (volts-1)
VT = VT0 + γ 2|φf | + |v B S | - 2|φf| VT0 = zero bias threshold voltage
γ = bulk threshold parameter (volts-0.5)
2|φf| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert current.
+
+
- -
+
-vBS
vDS
vGS
iD
D
B
S
G
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MOSFET
Constants for Silicon:
Constant Symbol Constant Description Value UnitsVGkni
ε0
εsi
εox
Silicon bandgap (27°C)BoltzmannÕs constantIntrinsic carrier concentration (27°C)
Permittivity of free space
Permittivity of silicon
Permittivity of SiO2
1.2051.381x10-23
1.45x1010
8.854x10-14
11.7 ε0
3.9 ε0
VJ/Kcm-3
f/cm
F/cm
F/cm
Model Parameters for a Typical CMOS Bulk Process (0.8µm CMOS n-well):
Parameter Parameter Typical Parameter ValueSymbol Description N-Channel P-Channel Units
VT0 Threshold Voltage(VBS = 0)
0.7 ± 0.15 −0.7 ± 0.15 V
K' TransconductanceParameter (in saturation)
110.0 ± 10% 50.0 ± 10% µA/V2
γ Bulk thresholdparameter
0.4 0.57 (V)1/2
λ Channel lengthmodulationparameter
0.04 (L=1 µm)
0.01 (L=2 µm)
0.05 (L = 1 µm)
0.01 (L = 2 µm)
(V)-1
2|φF| Surface potential atstrong inversion
0.7 0.8 V
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MOSFET SMALL SIGNAL MODELSmall-Signal Model
Complete schematic model:
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig. 4.2-4
B
vbs
+
-
G
S
B
D
G
S
B
D
S
D
where
gm ≡ diD
dvGS |Q
= β(VGS-VT) = 2βID gds ≡ diD
dvDS |Q
= λiD
1 + λ vD S ≈ λiD
and gmbs = ∂ιD∂vBS
Q =
∂iD
∂vGS
∂vGS
∂vBS
Q
=
- ∂iD∂vT
∂vT
∂vBS
Q
= gmγ
2 2|φF | - VB S = ηgm
Simplified schematic model:
rdsG
D
S
G
D
S
G
S
gmvgsvgs
+
-
vds
+
-
id
Fig. 4.2-2
D
S
Extremely important assumption:
gm ≈ 10gmbs ≈ 100gds
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Illustration of the Small-Signal Model Application
DC resistor:
DC resistance = vi
Q
= VI
• Useful for biasing - creating current from voltage andvice versa
Small-Signal Load (AC resistance):
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig. 4.2-4
B
vbs
+
-
G
S
B
D
G
S
B
D
S
D
AC resistance = vdsid
= 1
gm + gd s ≈
1gm
VT
i
vFig. 4-2-2B
ID
VDS
AC Resistance
DC Resistance
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Example 2 - Small-Signal Load Resistance
Find the small signal resistance of the MOS diodeshown using the parameters of Table 3.2-1.Assume that the W/L ratio is 10µm/1µm.
Solution
If we are going to include the bulk effect, we must first find the dc valueof the bulk-source voltage. Unfortunately, we do not know the thresholdvoltage because the bulk-source voltage is unknown. The best approach is toignore the bulk-source voltage, find the gate-source voltage and then iterate ifnecessary.
∴ VGS = 2Iβ + VT0 =
2·100110·10 + 0.7 = 1.126V
Thus let us guess at a gate-source voltage of 1.3V (to account for the bulk effect) and calculate the resultinggate-source voltage.
VT = VT0 + γ 2|φF | - (-3.7) - γ 2|φF| = 0.7 + 0.4 0.7+3.7 - 0.4 0.7 = 1.20V ⇒ VGS = 1.63V
Now refine our guess at VGS as 1.6V and repeat the above to get VT = 1.175V which gives VGS = 1.60V.
Therefore, VBS = -3.4V.
VDD = 5V
100µA
rac
Fig. 4.2-5
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Example 2 - Continued
The small signal model for this example is shown.
The ac input resistance is found by,
iac = gdsvac - gmvgs - gmbsvbs
= gdsvac + gmvs + gmbsvs = vac(gm+gmbs+gds)
∴ rac =
vaciac
= 1
gm+gmbs+gds
Now we must find the parameters which are,
gm = 2βID = 2·110·10·100 µS = 469µS, gds = 0.04V-1·100µA = 4µS,
and gmbs = 469µS·0.4
2 0.7+3.4 = 0.0987·469µS = 46.33µS
Finally,
rac = 106
469 + 46.33 + 4 = 1926Ω
If we had used the previous approximations of gm ≈ 10gmbs ≈ 100gds, then we could have simply let
rac ≈ 1
gm =
1469 = 2132Ω
Probably the most important result of this approximation is that we would not have to find VBS which tooka lot of effort for little return.
rds
G,D,B
S
gmvgs gmbsvbsvds = vgs
+
-
id
Fig. 4.2-6
rac
vac
iac
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Small-Signal Model for the Active Region
gm = ∂iD
∂vGS |Q
= K’WVDS
L (1+λVDS) ≈
K’W
L VDS
gmbs = ∂iD
∂vBS |Q
= K’Wγ VD S
2L 2φF - V B S
gds = ∂iD
∂vDS |Q
= K’W
L ( VGS - VT - VDS)(1+λVDS) + IDλ
1+λVDS
K’WL (VGS - VT - VDS)
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MOSFET CAPACITANCES
Types of Capacitance
Physical Picture:
SiO2
Bulk
Source DrainGate
CBS CBD
C4
C1 C2 C3
Fig1.8-5
FOX FOX
MOSFET Capacitances consist of:
• Depletion capacitance
• Charge storage or parallel plate capacitance
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MOSFET Depletion Capacitors
Model:
CBS = CJ·AS
1 - vB SPB
MJ
+ CJSW·PS
1 - vB SPB
MJSW
, vBS ≤ FC·PB
and
CBS = CJ·AS
( )1- FC1+MJ
1 - (1+MJ)FC + MJ VB SPB
+ CJSW·PS
( )1 - F C1+MJSW
1 - (1+MJSW)FC + MJSW VB SPB ,
vBS> FC·PB
where
AS = area of the sourcePS = perimeter of the sourceCJSW = zero bias, bulk source sidewall capacitanceMJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
SiO2
Polysilicon gate
Bulk
A B
CD
EF
GH
Drain bottom = ABCDDrain sidewall = ABFE + BCGF + DCGH + ADHE
Source Drain
Fig1.8-6
FC·PB
PB
vBS
CBS
vBS ≤ FC·PBvBS ≥ FC·PB
Fig1.8-6B
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Charge Storage (Parallel Plate) MOSFET Capacitances - C 1 , C 2 , C 3 and C 4
Bulk
LDMask
W
Oxide encroachment
ActualL (Leff)
Gate
Mask L
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
FOX
ActualW (Weff)
FOX
Fig1.8-7
Source
Gate
Drain
Gate-ChannelCapacitance (C2)
Channel-BulkCapacitance (C4)
Overlap capacitances:
C1 = C3 = LD·Weff·Cox = CGSO or CGDO (LD ≈ 0.015 µm for LDD structures)
Channel capacitances:
C2 = gate-to-channel = CoxWeff·(L-2LD) = CoxWeff·Leff
C4 = voltage dependent channel-bulk/substrate capacitance
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Charge Storage (Parallel Plate) MOSFET Capacitances - C 5
View looking down the channel from source to drain
Bulk
Overlap Overlap
Source/DrainGate
FOX FOXC5 C5
Fig1.8-8
C5 = CGBO
Capacitance values and coefficients based on an oxide thickness of 140 Å or Cox=24.7 × 10−4 F/m2:
Type P-Channel N-Channel UnitsCGSO 220 × 10−12 220 × 10−12 F/m
CGDO 220 × 10−12 220 × 10−12 F/m
CGBO 700 × 10−12 700 × 10−12 F/m
CJ 560 × 10−6 770 × 10−6 F/m2
CJSW 350 × 10−12 380 × 10−12 F/m
MJ 0.5 0.5MJSW 0.35 0.38
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Expressions for C GD , C G S and C G B
Cutoff Region:
CGB = C2 + 2 C 5 = Cox(Weff)(Leff) + 2CGBO(Leff)
CGS = C1 ≈ Cox(LD)Weff) = CGSO(Weff)
CGD = C3 ≈ Cox(LD)Weff) = CGDO(Weff)
Saturation Region:
CGB = 2C5 = CGBO(Leff)
CGS = C1 +(2/3)C2 = Cox(LD+0.67Leff)(Weff)
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 ≈ Cox(LD)Weff) = CGDO(Weff)
Active Region:
CGB = 2 C 5 = 2CGBO(Leff)
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
p+
p- substrate
Fig1.8-9
VB = 0 VG >VTVS = 0 VD >VG -VT
n+ n+p+
p- substrate
VB = 0 VG < VTVS = 0 VD > 0
Polysilicon
p+
p- substrate
VB = 0 VG >VTVS = 0 VD <VG -VT
Cutoff
Saturated
Active
Inverted Region
Inverted Region
Polysilicon
n+ n+
Polysilicon
n+ n+
CGD
CGB
CGS
CGS CGD
CGDCGS
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Illustration of C GD , C G S and C G B
0 vGS
CGS
CGS, CGD
CGDCGB
CGS, CGD
C2 + 2C5
C1+ 0.67C2
C1, C32C5
VT vDS +VT
Off Saturation Non-Saturation
vDS = constant vBS = 0
Capacitance
C1+ 0.5C2
Fig1.8-10
C4 Large
C4 Small
Comments on the variation of CBG in the cutoff region:
CBG = 1
1C2
+ 1
C4
+ 2C5
For vGS ≈ 0, CGB ≈ C2 + 2C5
(C4 is large because of the thin inversion layer in weak inversion where VGS is slightly less than VT))
For 0<vGS VT, CGB ≈ 2C5
(C4 is small because of the thicker inversion layer in strong inversion)
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Small-Signal Frequency Dependent Model
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig1.8-15B
vbs
+
- S
D
Cgd
Cgb
Cgs
Cbs
Cbd
The depletion capacitors are found by evaluating the large signal capacitors at the DC operating point.
The charge storage capacitors are constant for a specific region of operation.
Gainbandwidth of the MOSFET:
Assume VSB = 0 and the MOSFET is in saturation,
fT = 1
2π gm
Cgs + Cgd ≈
12π
gmCgs
Recalling that
Cgs ≈ 23 CoxWL and gm = µoCox
WL (VGS-VT)
gives
fT = 3
4π µo
L2 (VGS-VT)
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Summary of the MOSFET Large Signal Model
where,
rG, rS, rB, and rD are ohmic and contact resistances
iBD = Is
exp
vBD
Vt - 1 and iBS = Is
exp
vBS
Vt - 1
S
rSCGB
CGS CBS
iBS
iBD
vBD
vBS
+ -
+ - BrB
iD
CBDCGD
rD
D
rGG
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SHORT-CHANNEL MOSFET MODEL
Velocity Saturation
The most important short-channel effect in MOSFETs is the velocity saturation of carriers in thechannel. A plot of electron drift velocity versus electric field is shown below.
5x104
105
2x104
104
5x103
105 106 107
Electric Field (V/m)
Ele
ctro
n D
rift
Vel
ocity
(m
/s)
Fig1.8-11
An expression for the electron drift velocity as a function of the electric field is,
vd ≈ µnE
1 + E/Ec
where
vd = electron drift velocity (m/s)
µn = low-field mobility (≈ 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs
MOS Models (5/23/00) Page 31
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Short-Channel Model Derivation
As before,
JD = JS = iDW = QI(y)vd(y) → iD = W QI(y)vd(y) =
WQI(y)µnE
1 + E/Ec → iD
1 +
E EC
= WQI(y)µnE
Replacing E by dv/dy gives,
iD
1 +
1 EC
d vdy = WQI(y)µn
dvdy
Integrating along the channel gives,
⌡⌠
0
L
iD
1 +
1Ec
d vdy dy = ⌡⌠
0
vDS
WQI(y)µndv
The result of this integration is,
iD = µnCox
2
1 + 1Ec
vD S
L
WL [2(vGS - VT)vDS - vDS
2] = K’
2[1 + θ(vGS-VT)] WL [2(vGS - VT)vDS - vDS
2]
where θ = 1/LEc with dimensions of V-1.
The saturation voltage has not changed so substituting for vDS by vGS-VT gives,
iD = K’
2[1 + θ(vGS-VT)] WL [ vGS - VT]2
Note that the transistor will enter the saturation region for vDS < vGS - VT in the presence of velocitysaturation.
MOS Models (5/23/00) Page 32
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
The Influence of Velocity Saturation on the Transconductance Characteristics
The following plot was made for K’ = 110µA/V2 and W/L = 1:
0
200
400
600
800
1000
0.5 1 1.5 2 2.5 3
i D/W
(µA
/µm
)
vGS (V)
θ = 0
θ = 0.2
θ = 0.4
θ = 0.6
θ = 0.8θ = 1.0
Fig1.8-12
Note as the velocity saturation effect becomes stronger, that the drain current-gate voltage relationshipbecomes linear.
MOS Models (5/23/00) Page 33
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Circuit Model for Velocity Saturation
A simple circuit model to include the influence of velocity saturation is thefollowing:
We know that
iD = K’W2L (vGS’ -VT)2 and vGS = vGS’ + iD RSX or vGS’ = vGS - iDRXS
Substituting vGS’ into the current relationship gives,
iD = K’W2L (vGS - iDRSX -VT)2
Solving for iD results in,
iD = K’
2
1 + K’ WL RSX(vGS-VT)
WL (vGS - VT)2
Comparing with the previous result, we see that
θ = K’ WL RSX → RSX =
θLK’W =
1EcK’W
Therefore for K’ = 110µA/V2, W = 1µm and Ec = 1.5x106V/m, we get RXS = 6.06kΩ.
G
D
S
RSX
+
vGS
-
vGS'+
-
iD
Fig1.8-13
MOS Models (5/23/00) Page 34
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Output Characteristics of Short-Channel MOSFETs †
IBM, 1998, tox = 3.5nm
800
700
600
500
400
300
200
100
0-1.8 -1.2 -0.6 0.0 0.6 1.2 1.8
NFETLeff = 0.08µm
VGS=1.8V
VGS=1.4V
VGS=1.0V
VGS=0.6V
PFETLeff = 0.11µm
VGS=-1.8V
VGS=-1.4V
VGS=-1.0V
VGS=-0.6V
Drain Voltage (V)
Dra
in C
urre
nt (
µA/µ
m)
Fig1.8-14
† Su, L., et.al., “A High Performance Sub-0.25µm CMOS Technology with Multiple Thresholds and Copper Interconnects,” 1998 Symposium on VLSITechnology Digest of Technical Papers, pp. 18-19.
MOS Models (5/23/00) Page 35
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
SUBTHRESHOLD MOSFET MODEL
Weak inversion operation occurs when the applied gate voltage is below VT and pertains to when thesurface of the substrate beneath the gate is weakly inverted.
yyzzn+ n+
p-substrate/well
VGS
Diffusion Current
n-channel
Regions of operation according to the surface potential, φS.
φS < φF : Substrate not inverted
φF < φS < 2φF : Channel is weakly inverted (diffusion current)
2φF < φS : Strong inversion (drift current)
Drift current versus diffusion current in a MOSFET:
log iD
10-6
10-120 VT
VGS
Drift CurrentDiffusion Current
MOS Models (5/23/00) Page 36
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Large-Signal Model for Subthreshold
Model:
iD = Kx WL evGS/nVt(1 - e-vDS/Vt)(1 + λvDS)
where
Kx is dependent on process parameters and the bulk-source voltage
n ≈ 1.5 - 3
and
Vt = kTq
If vDS > 0, then
iD = Kx WL evGS/nVt (1 + λvDS)
Small-signal model:
gm = ∂iD
∂vGS |Q
= qIDnkT
gds = ∂iD
∂vDS |Q
IDVA
VGS=VT
VGS<VT
iD
vDS00 1V
Fig1.8-18
1µA
MOS Models (5/23/00) Page 37
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
SUBSTRATE CURRENT FLOW IN MOSFETS
Impact Ionization
Impact Ionization:
Occurs because high electric fields cause an impact which generates a hole-electron pair. The electronsflow out the drain and the holes flow into the substrate causing a substrate current flow.
Illustration:
Polysilicon
p+
p- substrate
Fig1.8-16
VG > VTVD > VDS(sat)
n+
DepletionRegion
B S
FixedAtom
Freehole
Freeelectron
A n+
MOS Models (5/23/00) Page 38
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
Model of Substrate Current Flow
Substrate current:
iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))]
where
K1 and K2 are process-dependent parameters (typical values are K1 = 5V-1 and K2 = 30V)
Schematic model:
D
G
S
B
iDB
Fig1.8-17
Small-signal model:
gdb = ∂iDB∂vDB
= K2 IDB
VDS - VDS(sat)
This conductance will have a negative influence on high-output resistance current sinks/sources.
MOS Models (5/23/00) Page 39
ECE 4430 - Analog Integrated Circuits and Systems © Phillip E. Allen 2000
SUMMARY
Simple Large-Signal Model
Non-saturation-
iD = WµoCox
L
(vGS - VT)vDS - vDS2
2 (1 + λvDS)
Saturation-
iD = WµoCox
2L (vGS - VT) 2 (1 + λvDS)
Small-Signal Model
gm ≡ diD
dvGS |Q
= β(VGS-VT) = 2βID gds ≡ diD
dvDS |Q
= λiD
1 + λ vD S ≈ λiD gmbs =
gmγ2 2|φF | - VB S
Capacitances
0 vGS
CGS
CGS, CGD
CGDCGB
CGS, CGD
C2 + 2C5
C1+ 0.67C2
C1, C32C5
VT vDS +VT
Off Saturation Non-Saturation
vDS = constant vBS = 0
Capacitance
C1+ 0.5C2
Fig1.8-10
C4 Large
C4 Small