Motivation for CDR: Deserializer (1)

EECS 270C / Spring 2009 Prof. M. Green / Univ. of California, Irvine 1

Motivation for CDR: Deserializer (1)

If input data were accompanied by a well-synchronized clock, deserialization could be done directly.

Input clock

Input data

channel

€

÷2

€

÷2

1:2DMUX

1:2DMUX

1:2DMUX


• Providing two high-speed channels (for data & clock) is expensive.

• Alignment between data & clock signals can vary due to different channel characteristics for the different frequency components. Hence retiming would still be necessary.

Clock

Data

Motivation for CDR (2)

input data ClockRecovery

circuit

retimed data

recovered clock

PLLs naturally provide synchronization between external and internal timing sources.A CDR is often implemented as a PLL loop with a special type of PD...


f

€

2Tb

€

Sx f( )

Return-to-Zero vs. Non-Return-to-Zero Formats

NRZ

RZ

1 0 1 1 0 1 0

Tb

RZ spectrum has energy at 1/Tb conventional phase detector can be used.

NRZ spectrum has null at 1/Tb ??

€

⇒

€

⇒

f

€

Sx f( )

€

1Tb

€

2Tb

€

3Tb


Phase Detection of RZ Signals

Vdata

VRCK

Vd

Vdata

VRCK

Vd

• Phase detection operates same as for clock signals for logic 1.

• Vd exhibits 50% duty cycle for logic 0.

• Kpd will be data dependent.


Phase Detection of NRZ Signals

Vdata

VRCK

Vd

Vdata

VRCK

Vd

Since data rate is half the clock rate, multiplying phase detection is ineffective.

• RZ signals can use same phase detector as clock signals

• RZ data path circuitry requires bandwidth that is double that of NRZ.

• Different type of phase detection required for NRZ signals.


Idea: Mix NRZ data with delayed version of itself instead of with the clock.

Example: 1010 data pattern (differential signaling)

€

12Tb

€

1Tb

€

•

€

•

€

•

€

•

€

•

€

•

€

•

€

•

€

•

X X

= =

Tb

€

32Tb

€

52Tb

fundamental generated

€

2Tb

€

12Tb

€

32Tb

€

52Tb


Operation of D Flip-Flips (DFFs)

CMOS transmission gate:

D

CK

CK

CK

CK

QI

latch:

D

CK

CK

CK

CK

QICK

CK CK

CK

Q

Master Slave

DFF:

Ideal waveforms:

D

CK

Q

D0 D1 D2

D0 D1 D2

Symbol:

D Q

No bubble Q changes following rising edge of CK


DFF Setup & Hold Time

tsetup thold

When a data transition occurs within the setup & hold region, metastability occurs.

D

CK

Q

At CK rising edge, the master latches and the slave drives.


DFF Clock-to-Q Delay

D

CK

CK

CK

CK

QICK

CK CK

CK

Q

Master Slave

D0 D1 D2

D0 D1 D2

D

CK

Q

tck-q

tck-q is determined by delays of transmission gate and inverter.


Din

RCK

P

Q

Delay between Din to Q is related to phase between Din & RCK

Realization of Data/Data Mixing :

Q

P

D0

D0

D1

€

⊕D1

D2

€

⊕D2

D3

€

⊕D3

D4

€

⊕

D1 D2 D3

D0 D1 D2 D3

Din

RCK

RCK early:

D0 D1 D2 D3

D0 D1 D2 D3

D0

D1

€

⊕D1

D2

€

⊕D2

D3

€

⊕D3

D4

€

⊕

RCK synchronized:

Same as Din, synchronized with RCK


Define zero phase difference as a data transition coinciding with RCK falling edge; i.e., RCK rising edge is in center of data eye.

€

Δφ2π

=ΔtTb

−12

Q

P

Din

RCK

RCK early (Δ < 0): RCK synchronized (Δ = 0):

Tb

Δt

Tb

Δt

€

Δt=TbΔφ2π

+12

⎡

⎣ ⎢

⎤

⎦ ⎥


Din

RCK

P

Q

Phase detector characteristic also depends on transition density:

0011… pattern:

€

VP =Vswing⋅Δt2Tb

−12

⎛

⎝ ⎜

⎞

⎠ ⎟

In general,

€

VP =Vswing⋅αΔtTb

−12

⎛

⎝ ⎜

⎞

⎠ ⎟ where α average transition density

0101… pattern:

Q

P

Din

RCK

€

VP =Vswing⋅ΔtTb

−12

⎛

⎝ ⎜

⎞

⎠ ⎟

Vswing


€

ΔtTb

=Δφ2π

+12

€

VPVswing

=α ΔtTc

−12

€

VPVswing

=α2π

Δφ+ (α −1)2

Both slope and offset of phase-voltage characteristicvary with transition density!

Constructing CDR PD Characteristic

-π +π

Δ

€

VPVswing

α = 0.25α = 0.5

α = 1

€

Kpd =α2π

€

Δφ =0 ⇒VPVswing

=α −12

slope:

intercept:

€

+12

€

−12


To cancel phase offset:

Din

RCK

P

Q

R

QR

D0 D1 D2 D3

D0 D1 D2 D3

Q

RCK

QR

R

C. R. Hogge, “A self-correcting clock recovery circuit,” IEEE J. Lightwave Tech., vol. 3, pp. 1312-1314, Dec. 1985.

Always 50% duty cycle;average value is

€

(α −1)⋅Vswing 2

Kpd still varies with α,but offset variation cancelled.

-π+π

€

VP −VRVswing

€

Δφ

+1/2

-1/2

α = 1

α = 0.5


Transconductance Block

ISS ISS

P+ P- R- R+

Iout+ Iout-


Due to inherent mixing operation, Hogge PD is not a good frequency detector. A frequency acquisition loop with a reference clock is usually needed:

J. Cao et al., “OC-192 transmitter and receiver in 0.18 CMOS,” JSSC. vol. 37, pp. 1768-1780, Dec. 2002.


Non-Idealities in Hogge Phase Detector:A. Clock-to-Q Delay (1)

Din

RCK

P

Q

R

QR

tck-Q

tck-Q

€

Din

€

RCK

€

Q

€

QR

€

P =Din ⊕Q

€

R =Q ⊕QR


Din

RCK

Q

QR

P

R

tck-Q

tck-Q

€

VP −VR

Vswing

€

Δφ

+α2

-α2os

€

φos =2π tck−QTb


Result is an input-referred phase offset:


Din

RCK

tck-Q

CDRDin

Dout

RCK

Phase offset moves RCK away fromcenter of data, making retiming lessrobust.




Din

RCK

P

Q

R

QR

tck-Q

tck-Q

Δt

Set

€

Δt≈tCK−Q

DΔt

Din

DΔt

RCK

Q

QR

P

R

Use a compensating delay:


Non-Idealities in Hogge Phase Detector:B. Delay Between P & R (1)

Din

RCK

P

Q

R

QR

Din

RCK

Q

QR

P

R

P and R are offset by 1/2 clock period


P

R

Din

RCK

P

Q

R

QR

Vcontrol

to VCO


Average value of Vcontrol is well-controlled, but resulting ripplecauses high-frequency jitter.


Idea: Based on R output, create compensating pulses:

Din

RCK

€

P

€

R

€

′ P

€

′ R

DFF

latch

latch

latch

Din

RCK

Q

QR

P (up)

R (dn)

Vcontrol

Standard Hogge/charge pump operation for single input pulse:



Din

RCK

€

P

€

R

€

′ P

€

′ R

DFF

latch

latch

latchQ4

Q3

Q2

Q1

Din

RCK

Q4

Q3

Q2

Q1

Vcontrol

P (up)

R (dn)

P’(dn)

R’(up)

Cancels out effect of next pulse



Other Nonidealities of Hogge PD (1)

PD

Dif

fere

ntia

l Out

put

(mV

)

0

-20

-40

-60

60

40

20

0 10p 20p 30p 40p 50p-30p-40p-50p

-20p -10p

Data Delay in regard to Clock (s)

response from ideal linear PD

simulated result of one linear PD


Effect of Transition Density:



Effect of DFF bandwidth limitation:



Effect of XOR bandwidth limitation:

Since the PD output signals are averaged, XOR bandwidth limitation has negligible effect.



Effect of XOR Asymmetry:



Binary Phase Detectors

Idea: Directly observe phase alignment between clock & data

Clock falling edge early:Decrease Vcontrol

Clock falling edge late:Increase Vcontrol

Clock falling edge centered:No change to Vcontrol

Ideal binary phase-voltage characteristic:

Δ

+1/2

-1/2

€

VPVswing

Also known as “bang-bang” phase detector


D Flip-Flop as Phase Detector

Early clock:Data transitions align

with clock low

Late clock:Data transitions align

with clock high

Din

RCK

Din

RCK

RCK

€

Din

VP

Realization using double-clocked DFF; note that RCK/Din connections are reversed:

VPRCK

€

Din

€

Din

€

Din

=

Top (bottom) DFF detects on Din rising (falling) edge; DFF selected by opposite Din edge to avoid false transitions due to clock-q delay.


What happens if =0?

tsetup

thold

D

CK

Q

• If transition at D input occurs within setup/hold time, metastable operation results.

• Q output can “hang’’ for an arbitrarily long time if zero crossings of D & CK occur sufficiently close together.

• Metastable operation is normally avoided in digital circuit operation(!)


Dog Dish Analogy

???

A dog placed equidistant between two dog dishes will starve (in theory).


Non-Idealities in Binary DFF Phase Detector

1. Metastable operation difficult to characterize & simulate, varies widely over processing/temperature variations. Kpd (and therefore jitter transfer function parameters) are difficult to analyze. Exact value of Kpd depends on metastable behavior and varies with input jitter.

2. Large-amplitude pattern-dependent variation is present in phase detector output while locked.

3. During long runs phase detector output remains latched, resulting in VCO frequency changing continuously:

VP

RCK

€

Din

€

fvco


Idea: Change VCO frequency for only one clock period

VP

RCK

€

Din

RCK early RCK late

Circuit realization should sample data with clock (instead of clock with data)while maintaining bang-bang operation.


Alexander Phase Detector

RCK

€

Din

Q1Q2

Q3 Q4

UP

DN

€

Din

RCKQ1

Q2

Q3

Q4

UP

DN

RCK early

Q1 leads Q3; Q2/Q4 in phase

RCK late

Q3 leads Q1; Q1/Q4 in phase


Simulation Results: Alexander PD

DFF outputs

VCO controlvoltage


Binary PDLinear PD

Simulation Comparison: Linear vs. Binary

• very small freq. acquisition range• low steady-state jitter

• high freq. acquisition range• high steady-state jitter

Vcontrol Vcontrol


Half-Rate CDRs

To relax speed requirements for a given fabrication technology, a half-rate clock signal can be recovered:

Din

RCK

RCK2

input data

full-rate recovered clock

half-rate recovered clock

• Can be used in in applications (e.g., deserializer) where full-rate clock is not required.

• Duty-cycle distortion will degrade bit-error ratio & jitter tolerance compared to full-rate versions.


Idea 1: Input data can be immediately demultiplexed with half-rate clock

Din

RCK2

DA

DB

Din

RCK2

DA

DB

D0 D1 D2 D3 D4

D0 D2 D4

D1 D3

synchronized withclock transitions


Din

RCK2latch latch

latch latch

DAXA

XB DB

Splitting D flip-flopsinto individual latches:

synchronized with RCK2DB

RCK2

Din

XA

XB

DA

synchronized withboth RCK2 & Din

These pulse widths contain phase information.


DB

RCK2

Din

XA

XB

DA

€

P =X A ⊕ XB

€

R =DA ⊕DB

RCK2

Din

P R

XA

XB

DA

DB€

×1

2

Complete Linear Half-Rate PD

J. Savoj & B. Razavi, “A 10Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” JSSC, vol. 36, pp. 761-768, May 2001.


Idea 2: Observe timing between Din, RCK and quadrature RCKQ

Din

RCK

RCKQ

S0 S1 S2

Clock late

Din

RCK

RCKQ

S0 S1 S2

Clock early

S0, S2 sampled with RCK transitions S1 sampled with RCKQ transitions

Phase logic:

€

S0 ⊕S1 =0( ) and S1 ⊕S2 =1( ) ⇒

€

S0 ⊕S1 =1( ) and S1 ⊕S2 =0( ) ⇒

€

S0 ⊕S1 =0( ) and S1 ⊕S2 =0( ) ⇒

clock early

clock late

no transition


Din

RCK

RCKQ

DI

DQ

VPD

Din

RCK

RCKQ

DI

DQ

VPD

Din

RCK

RCKQ

DI

DQ

VPD

Clock early Clock late

J. Savoj & B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase detector,” JSSC, vol. 38, pp. 13-21, Jan. 2003.


DLL-Based CDRs

fref CMUphase generator

phaseMUX

VC

C

PDDin

Dout

retimer

fck• CMU JBW can be optimized

to minimize fck jitter.

• No VCO inside CDR loop; less jitter generation.

• Can be arranged to have faster lock time.

CDR loop


Fast-Lock CDR for Burst-Mode Operation

Gated ring oscillator:EN

EN high: 7-stage ring oscillatorEN low: no oscillation

CDR based on 2 gated ring oscillators:

Din

RCK

Each ring oscillation waveform is forced to sync with one of the Din phases.

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Motivation for CDR: Deserializer (1)

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