MPEG decoder Case -...

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September 4, 2002. Course 290A

MPEG decoder Case

K.A. VissersUC Berkeley

Chamleon Systems Inc.and

Pieter van der WolfPhilips Research

Eindhoven, The Netherlands

2


Outline

• Introduction• Consumer Electronics• Kahn Process Networks Revisited• MPEG application• Mapping• Design space exploration• Conclusions

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Consumer Electronics

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• Cost (< $100 for electronics of TV)• Low power consumption (no fan / mobile)• Large series (> 0.5 million pieces)• Robustness (no hazards, no reboots)• Real-time constraints (no loss of data, guaranteed

response)• Both control and signal processing• Increasing requirements for computation &

communication (more functions, higher resolutions)• Wide range of information appliances• Large portfolio of semiconductor products

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Trend towards multi-functional multi-standard products– web browsing– e-mail– high-speed modem (xDSL)– teletext– EPG– graphics– MPEG-2– picture rate conversion (50-100 Hz)– video scaling– picture enhancement– etc.

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Video Processing

Requirements for computation & communicationStandard resolution TV:• PAL: 720 x 576 @ 25 frames/sec• NTSC: 720 x 480 @ 30 frames/sec10.4 million samples/secluminance (y) and chrominance (u and v, subsampled)typically 8-10 bits for luminance, 8 bits for chrominance

Say in TV system 100 - 1000 operations / pixel:• 1 - 10 billion operations / sec• 1 - 10 Gbyte / sec internal bandwidthHigh definition TV (1920 X 1080 @ 30): factor 6 more

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TM-xxxxD$

I$

TriMedia CPU

DEVICE I/P BLOCK

DEVICE I/P BLOCK

DEVICE I/P BLOCK

.

.

.

DVP System Silicon

VLIW Media Processor:• 100 to 300+ MHz• 32-bit or 64-bit

NexperiaSystem Busses• PI bus• Memory bus• 32-128 bit

PI B

US

SDRAM

MMI

DV

P M

EM

OR

Y B

US

DEVICE I/P BLOCK

PRxxxxD$

I$

MIPS CPU

DEVICE I/P BLOCK.

.

.DEVICE I/P BLOCK

PI B

US

General Purpose RISC Processor• 50 to 300+ MHz• 32-bit or 64-bitLibrary of Device Blocks• Image

coprocessors• DSPs• UART• 1394• USB

•…and more

TriMediaTMMIPSTM

Philips NexperiaTM

Flexible architecture for digital video applications

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NexperiaTM

ScalabilityVLIW

SDRAM

MMI

TriMedia CPU + Device blocks whencontrol functions are

minimal

MIPS CPU +Trimedia CPU replacing some Device blocks

RISC

SDRAM

VLIWMMI

• Single architecture, multiple product configurations– Processor core options - TM32, TM64, MIPS32, MIPS64 ...– Device block options

• Highly programmable to weakly programmable

MIPS CPU +Device blocks +

Software

RISC

SDRAM

MMI

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Design Problem

VLIWcpu

I$

video-in

video-out

audio-in

SDRAM

audio-out

PCI bridge

Serial I/O

timers MPEG

D$

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MPEG2 decoding

Audio and Video,• Audio completely done in software on VLIW• Video:

– describe in Kahn Process Networks– Test for compliance with the standards:

• ranging from H263 to HDTV!

– Map on software + dedicated hardware

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MPEG2 decoding status

IP content in Philips Semiconductors:NX8500 family: single chip HDTV decoder

(audio + Video):– dedicated MPEG2 video decoder– specialized Video Output– many other features

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Methodology

In Research:• Describe the full functionality of the MPEG2

video decoding.• Mapping and performance analysis

Compare with the actual Semiconductors results in ICs

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Steps

• Download the Berkeley MPEG decoder• Remove errors• Remove global variables• Split in separate processes

– natural partitioning– insert read, write and execute statements– profile and run

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Application Modeling: Yapi

Y-api: An C++ api for Kahn Process Networks:Expose parallelism and communication

ProcessFIFO Read

Write

A C

B Execute

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Workload analysis

Computation and Communication workload

FIFO

A C

B

Operation

A-up 56952

Count

A-down 1834

Operation

B-filter 58786

Count

Operation

C-join 34815

Count

C-pass 9834

C-skip 7274

58786 58786

34815

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MPEG decoding

• Take a stream of encoded bits• Separate the headers and parse for parameters• Variable length decoding• On blocks of 16x 16 pixels do:

– Inverse scan quantization– Inverse Discrete Cosine Transform– Add to the motion compensated block

• Reorder images IPBB -> IBBP

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Motion-compensation

n

n-1

n-1/2

picture number

-D/2

D/2

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Mpeg2 video decoder

Model of MPEG2 video decoder in Yapi

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Design Problem

VLIWcpu

I$

video-in

video-out

audio-in

SDRAM

audio-out

PCI bridge

Serial I/O

timers MPEG

D$

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Mpeg2 mapping

Dedicated Mpeg coprocessor: pipe with fifo buffers and blocking semantics

Software on the VLIW

Video In

Video Out

Memory

Memory

Dedicated Mpeg coprocessor

Memory

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Mpeg2 mapping for SD!

Dedicated Mpeg coprocessor: pipe with fifo buffers and blocking semantics


Video In

Video Out

Memory

Memory


Memory

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Mapping and performance analysis

Process

FIFO

Read

Write

A C

BExecuteApplication

model (YAPI)

R(1)

W(3)E(C-join)

R(2)W(2)E(B-filter)

R(1)

X YAbstract

MemAbstract bus model

Architecturemodel processor

model

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MPEG2 mapping

Data dependant: different video streams:• Computation on the VLIW and coprocessors• Communication on the bus and internally in

the Mpeg2 decoderExploration Questions:Bus load, burst size of the communication,latency of the memory interface

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Exploration results: bus waits

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

20000

0 10 20 30 40 50 60 70cycle

SU stalls for bus

"int_SU_o2.dat"

Storage Unit

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0

500

1000

1500

2000

2500

0 10 20 30 40 50 60 70cycle

VInput stalls for bus

"int_VIn_o1.dat"

Exploration results: bus waits

Video In

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Design Space Exploration

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Lessons learned

• Models of the concurrency matter• Quantifying design choices is key• Match of Model of Computation and

Model of Architecture• Tools required: Mapping, Simulation and

Design Space Exploration support• Raise the level of abstraction for

exploration

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References

• Pieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei, and Kees Vissers, "An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology" In: Proc. 7th Int. Workshop on Hardware/Software Codesign (CODES'99), Rome, Italy, May 3-5 1999.

• E.A. de Kock, G. Essink, W.J.M. Smits, P. van der Wolf, J.-Y Brunel, W.M. Kruijtzer, P. Lieverse, K.A. Vissers. “YAPI: Application Modeling for Signal Processing Systems” In: Proc. 37th DAC, Los Angeles, June 2000.

• Http://ptolemy.eecs.berkeley.edu/~vissers

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