MSP430 eZ430-rf2500

Guillaume Salagnac

November 29, 2011

1

Embedded Systems

WikipediaAn embedded system is a computer system designed for specific controlfunctions within a larger system, often with real-time computing constraints.It is embedded as part of a complete device often including hardware andmechanical parts.

2

Consumer Electronics

3

ez430-RF2500 SLAU227A.pdf p.2

2

1. eZ430-RF2500 Overview. Wireless Made Easy.

The eZ430-RF2500 is a complete USB-based MSP430 wireless development tool providing all the hardware and software to evaluate the MSP430F2274 microcontroller and CC2500 2.4-GHz wireless transceiver.

The eZ430-RF2500 uses the IAR Embedded Workbench Integrated Development Environment (IDE) or Code Composer Essentials (CCE) to write, download, and debug an application. The debugger is unobtrusive, allowing the user to run an application at full speed with both hardware breakpoints and single stepping available while consuming no extra hardware resources.

The eZ430-RF2500T target board is an out-of-the box wireless system that may be used with the USB debugging interface, as a stand-alone system with or without external sensors, or may be incorporated into an existing design.

The new USB debugging interface enables the eZ430-RF2500 to remotely send and receive data from a PC using the MSP430 Application UART.

eZ430-RF2500 features:

• USB debugging and programming interface featuring a driverless installation and application backchannel

• 21 available development pins

• Highly integrated, ultra-low-power MSP430 MCU with 16-MHz performance

• Two general-purpose digital I/O pins connected to green and red LEDs for visual feedback

• Interruptible push button for user feedback

Figure 1. eZ430-RF2500

MSP430F2274

18 Accessible Pins

Chip Antenna

CC25002x LEDsPushbutton

USB Powered

Spy Bi-Wire &

MSP430 Appliation UART

4

ez430-RF2500 SLAU227A.pdf p.3

3

Figure 2. eZ430-RF2500 Battery Board

2. Kit Contents, eZ430-RF2500

• The hardware includes:

• Two eZ430-RF2500T target boards

• One eZ430-RF USB debugging interface

• One AAA battery pack with expansion board (batteries included)

• One MSP430 Development Tool CD-ROM containing documentation and new development software for eZ430-RF2500:

• MSP430x2xx Family User’s Guide, SLAU144

• eZ430-RF2500 User’s Guide, SLAU227

• Code Composer Essentials (CCE), SLAC063

• IAR Embedded Workbench (KickStart Version), SLAC050

• eZ430-RF2500 Sensor Monitor (Code and Visualizer), SLAC139

NOTE: Please visit Texas Instrument’s website for latest versions www.ti.com/msp430

5

Low-power Operation

Power

Time

1mW

0.1µW

6

Outline

1 Introduction

2 Schematics and Pinout

3 Internal structure

4 Digital Input/Output

5 Interrupts

6 Managing time

7 Serial Communication

8 Analog Input/Output

9 Conclusion

7

Target board schematics SLAU227A.pdf p.16

16

Figure 10. eZ

430-RF

2500T, T

arget Board and B

attery Board, S

chematic

8

Target board PCB layout SLAU227A.pdf p.17

17

Figure 11. eZ430-RF, USB Debugger, PCB Components Layout

Figure 12. eZ430-RF, USB Debugger, PCB Layout

Figure 13. eZ430-RF2500T, Target Board, PCB Layout

Top Layer Bottom Layer

9

Debugger board schematics SLAU227A.pdf p.14

14

13. eZ430-R

F2500 Schem

atics

F

igure 8. eZ430-R

F, U

SB

Debugging Interface, S

chematic

10

Debugger board schematics SLAU227A.pdf p.15

15

F

igure 9. eZ430-R

F, U

SB

Debugging Interface, S

chematic

11

MSP430F2274 device pinout SLAS504B.pdf p.5

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

MSP430x22x4 device pinout, RHA package

1DVSS

P1

.5/T

A0/

TM

S

P1.0/TACLK /ADC 10CLK

P1.1/TA 0

P1

.2/T

A1

P1

.3/T

A2

P1

.4/S

MC

LK

/TC

K

13

P2.4/TA 2/A4/VREF+/VeREF+/OA1I0

P2.

5/R

osc

DV

CC

TE

ST

/SB

WT

CK

P1

.6/T

A1/

TD

I/TC

LK

2

3

4

5

6

7

8

10

9

12 14 15 16 17 18 19

30

29

28

27

26

25

24

23

21

22

3839 37 36 35 34 33 32

XOUT /P2.7

XIN /P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK /A0/OA 0I0

P2.1/TAINCLK /SMCLK /A1/OA 0O

P2.2/TA 0/A2/OA 0I1

P3.0/UCB 0STE /UCA 0CLK /A5

P3.1/UCB 0SIMO /UCB 0SDA

DV

CC

P1.

7/T

A2/

TD

O/T

DI

P2.3/TA 1/A3/VREF!/VeREF!/OA 1I1/OA1O

P3.7/A7/OA 1I2

P3.6/A6/OA 0I2

P3.5/UCA 0RXD /UCA 0SOMI

P3.4/UCA 0TXD /UCA 0SIMO

AV

CC

AV

SS

P3.

2/U

CB

0S

OM

I/UC

B0

SC

L

P3

.3/U

CB

0CL

K/U

CA

0S

TE

P4

.0/T

B0

P4

.1/T

B1

P4

.2/T

B2

P4

.3/T

B0

/A1

2/O

A0

O

P4

.4/T

B1

/A1

3/O

A1

O

P4

.5/T

B2

/A1

4/O

A0

I3

P4.6/TBOUTH/A15/OA 1I3

P4.7/TBCLK

12

MSP430F2274 Functional Block Diagram SLAS504B.pdf p.6

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

MSP430x22x2 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

MSP430x22x4 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

OA0, OA1

2 Op Amps

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

13

MSP430 16-bit Memory Map SLAU144D.pdf p.1-4

14

Outline

1 Introduction

2 Schematics and Pinout

3 Internal structure

4 Digital Input/Output

5 Interrupts

6 Managing time

7 Serial Communication

8 Analog Input/Output

9 Conclusion

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

MSP430x22x2 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

MSP430x22x4 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

OA0, OA1

2 Op Amps

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

15

GPIO Port Registers

P1DIR: direction, 0=in, 1=outP1OUT: set outputP1IN: read input

16

Figure 10. eZ

430-RF

2500T, T

arget Board and B

attery Board, S

chematic

16

Example

char *P5OUT = (char*) 0x0042;

*P5OUT = 0x13;

volatile unsigned char P5OUT = asm("0x0042");P5OUT = 0x13;

#include <io.h>P5OUT = 0x13;

17

GPIO Port Schematics Example (from another MSP430)

TI eZ430-RF2500

Schéma FET

Brochage et E/S!Brochage du MSP430f2274!Pilotage des Entrées / Sorties!Mapping mémoire desMSP430

!Exemple de port(MSP430f149)

!Exemple de port(MSP430f149)

Exemple

Suite

- p. 11/14

Exemple de port (MSP430f149)

input/output schematic (continued)

port P3, P3.1, input/output with Schmitt−trigger

P3.1/SIMO0

P3IN.1

Pad Logic

EN

D

P3OUT1

P3DIR.1

P3SEL.1

(SI)MO0

0

1

0

1

DCM_SIMO

SYNCMM

STESTC

From USART0

SI(MO)0To USART0

0: Input1: Output

P3SEL: 0=GPIO, 1=another peripheral

18

Pin Sharing SLAS504B.pdf p.9

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

Terminal Functions, MSP430x22x4

TERMINAL

NAMEDA RHA

I/ODESCRIPTION

NAMENO. NO.

I/ODESCRIPTION

P1.0/TACLK/ADC10CLK

31 29 I/O General-purpose digital I/O pinTimer_A, clock signal TACLK inputADC10, conversion clock

P1.1/TA0 32 30 I/O General-purpose digital I/O pinTimer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit

P1.2/TA1 33 31 I/O General-purpose digital I/O pinTimer_A, capture: CCI1A input, compare: OUT1 output

P1.3/TA2 34 32 I/O General-purpose digital I/O pinTimer_A, capture: CCI2A input, compare: OUT2 output

P1.4/SMCLK/TCK

35 33 I/O General-purpose digital I/O pin / SMCLK signal outputTest Clock input for device programming and test

P1.5/TA0/TMS

36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 outputTest Mode Select input for device programming and test

P1.6/TA1/TDI/TCLK

37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 outputTest Data Input or Test Clock Input for programming and test

P1.7/TA2/TDO/TDI†

38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 outputTest Data Output or Test Data Input for programming and test

P2.0/ACLK/A0/OA0I0 8 6 I/O General-purpose digital I/O pin / ACLK outputADC10, analog input A0 / OA0, analog input I0

P2.1/TAINCLK/SMCLK/A1/OA0O

9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLKSMCLK signal outputADC10, analog input A1 / OA0, analog output

P2.2/TA0/A2/OA0I1

10 8 I/O General-purpose digital I/O pinTimer_A, capture: CCI0B input/BSL receive, compare: OUT0 outputADC10, analog input A2 / OA0, analog input I1

P2.3/TA1/A3/VREF!/VeREF!/OA1I1/OA1O

29 27 I/O General-purpose digital I/O pinTimer_A, capture CCI1B input, compare: OUT1 outputADC10, analog input A3 / negative reference voltage output/inputOA1, analog input I1 / OA1, analog output

P2.4/TA2/A4/VREF+/VeREF+/OA1I0

30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 outputADC10, analog input A4 / positive reference voltage output/inputOA1, analog input I0

P2.5/ROSC

3 40 I/O General-purpose digital I/O pinInput for external DCO resistor to define DCO frequency

XIN/P2.6 6 3 I/O Input terminal of crystal oscillatorGeneral-purpose digital I/O pin

XOUT/P2.7 5 2 I/O Output terminal of crystal oscillatorGeneral-purpose digital I/O pin

P3.0/UCB0STE/UCA0CLK/A5

11 9 I/O General-purpose digital I/O pinUSCI_B0 slave transmit enable / USCI_A0 clock input/outputADC10, analog input A5

P3.1/UCB0SIMO/UCB0SDA

12 10 I/O General-purpose digital I/O pinUSCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode

P3.2/UCB01SOMI/UCB0SCL

13 11 I/O General-purpose digital I/O pinUSCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode

P3.3/UCB0CLK/UCA0STE

14 12 I/O General-purpose digital I/O pinUSCI_B0 clock input/output / USCI_A0 slave transmit enable

P3.4/UCA0TXD/UCA0SIMO

25 23 I/O General-purpose digital I/O pinUSCI_A0 transmit data output in UART mode, slave in/master out in SPI mode

19

GPIO Port Schematics Example (from another MSP430)

TI eZ430-RF2500

Schéma FET

Brochage et E/S!Brochage du MSP430f2274!Pilotage des Entrées / Sorties!Mapping mémoire desMSP430

!Exemple de port(MSP430f149)

!Exemple de port(MSP430f149)

Exemple

Suite

- p. 12/14

Exemple de port (MSP430f149)

" Ports 1 et 2 avec interruptions" Registres PxIFG (flag) et PxIE (interrupt enable)

input/output schematicport P1, P1.0 to P1.7, input/output with Schmitt−trigger

P1.0/TACLK ..

P1IN.x

Module X IN

Pad Logic

InterruptFlag

EdgeSelect

Interrupt

P1SEL.xP1IES.x

P1IFG.x

P1IE.xP1IRQ.x

EN

D

SetEN

Q

P1OUT.x

P1DIR.x

P1SEL.x

Module X OUT

Direction ControlFrom Module

0

1

0

1P1.7/TA2

20

GPIO Example

#include <io.h>

#define BIT_GREEN (1 << 1)#define BIT_RED (1 << 0)

void wait(unsigned int n){int i;for(i=0;i<n;i++){asm(" nop;");asm(" nop;");

}}

int main(void){unsigned char b;P1DIR |= (BIT_GREEN | BIT_RED);P1SEL &= ~(BIT_GREEN | BIT_RED);P1OUT &= ~(BIT_GREEN | BIT_RED);b = 0x01;while (1){wait(50000); wait(50000);wait(50000); wait(50000);P1OUT = b;b <<= 1;if (b == 0x4)

b = 0x01;}return 0;

}

21

Bitwise Operators in C...illustrated with non-C syntax

A = 0b01101001

~A = 0b10010110

A<<2 = 0b10100100

A<<2 = 0b00011010

A|= 0b00000010 => A=0b01101011

A&=~0b00001000 => A=0b01100001

A^= 0b10001000 => A=0b11100001

22

Outline

1 Introduction

2 Schematics and Pinout

3 Internal structure

4 Digital Input/Output

5 Interrupts

6 Managing time

7 Serial Communication

8 Analog Input/Output

9 Conclusion

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

MSP430x22x2 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

MSP430x22x4 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

OA0, OA1

2 Op Amps

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

23

Interrupts

An interrupt can only occur when bothbit General Interrupt Enable (GIE) set in status registerInterrupt Enable bit set in specific peripheral register

e.g. PxIE in ports 1 and 2

Acknowledgement isimplicit for single-source interruptsnecessary for multiple-source interrupts

e.g. PxIFG in port 1 and 2

Interrupt nesting is disabled by defaultGIE is cleared upon entering ISR

24

ISR Exampleusing GCC intrisincs

interrupt (PORT1_VECTOR) PORT1_ISR(void){

if (P1IFG & (P1IE & (1<<2) )){SWITCH_RED_LED();

}

P1IFG=0;}

25

MSP430 16-bit Memory Map SLAU144D.pdf p.1-4

26

MSP430F2274 Peripherals mapping SLAS504B.pdf p.22

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

PERIPHERALS WITH BYTE ACCESS (continued)

Basic Clock System+ Basic clock system control 3Basic clock system control 2Basic clock system control 1DCO clock frequency control

BCSCTL3BCSCTL2BCSCTL1DCOCTL

053h058h057h056h

Port P4 Port P4 resistor enablePort P4 selectionPort P4 directionPort P4 outputPort P4 input

P4RENP4SELP4DIRP4OUTP4IN

011h01Fh01Eh01Dh01Ch

Port P3 Port P3 resistor enablePort P3 selectionPort P3 directionPort P3 outputPort P3 input

P3RENP3SELP3DIRP3OUTP3IN

010h01Bh01Ah019h018h

Port P2 Port P2 resistor enablePort P2 selectionPort P2 interrupt enablePort P2 interrupt edge selectPort P2 interrupt flagPort P2 directionPort P2 outputPort P2 input

P2RENP2SELP2IEP2IESP2IFGP2DIRP2OUTP2IN

02Fh02Eh02Dh02Ch02Bh02Ah029h028h

Port P1 Port P1 resistor enablePort P1 selectionPort P1 interrupt enablePort P1 interrupt edge selectPort P1 interrupt flagPort P1 directionPort P1 outputPort P1 input

P1RENP1SELP1IEP1IESP1IFGP1DIRP1OUTP1IN

027h026h025h024h023h022h021h020h

Special Function SFR interrupt flag 2SFR interrupt flag 1SFR interrupt enable 2SFR interrupt enable 1

IFG2IFG1IE2IE1

003h002h001h000h

27

Outline

1 Introduction

2 Schematics and Pinout

3 Internal structure

4 Digital Input/Output

5 Interrupts

6 Managing time

7 Serial Communication

8 Analog Input/Output

9 Conclusion

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

MSP430x22x2 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

MSP430x22x4 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

OA0, OA1

2 Op Amps

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

28

Oscillators and clocks

29

Basic Clock Module SLAU144D.pdf p.5-3!"#$% &'(%) *(+,'-. /012(+,%1$(0

!"#!"#$% &'(%) *(+,'-.

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32

Timers

A timer is a 16-bit counter whichcounts cycles from a selectable clock sourcein a certain way (up, down, continuous)

Can be used in two ways :memorize its value on certain events (capture mode)

ortrigger an interrupt when reaching a given value (compare mode)

Each timer has two interrupt lines:implicit acknowledgement: TxCCR0 vectorack. must be done by software: TxIV vector

33

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Outline

1 Introduction

2 Schematics and Pinout

3 Internal structure

4 Digital Input/Output

5 Interrupts

6 Managing time

7 Serial Communication

8 Analog Input/Output

9 Conclusion

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

MSP430x22x2 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

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Emulation(2BP)

XOUT

JTAGInterface

Flash

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ACLK

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MDB

MAB

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Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

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MSP430x22x4 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

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MCLK

SMCLK

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3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

OA0, OA1

2 Op Amps

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

39

Serial Communication

Examples of serial protocols:Morse code, USB, Firewire, USB, Ethernet, RS232, I2C, SPI...

The MSP430F2274 has two UARTs (both interrupt-capable):USCI_A0: UART, I2C, SPI, IrDAUSCI_B0: SPI, I2C

Asynchronous communication (UART) :Both ends have to agree on the communication protocol:encoding, frame length, reference frequency, ...

40

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41

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42

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43

USCI Block Diagram: I2C Mode SLAU144D.pdf p.17-4

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44

Outline

1 Introduction

2 Schematics and Pinout

3 Internal structure

4 Digital Input/Output

5 Interrupts

6 Managing time

7 Serial Communication

8 Analog Input/Output

9 Conclusion

MSP430x22x2, MSP430x22x4MIXED SIGNAL MICROCONTROLLER

SLAS504B ! JULY 2006 ! REVISED JULY 2007

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251!1443

MSP430x22x2 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

MSP430x22x4 functional block diagram

Basic ClockSystem+

RAM

1kB512B512B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16!Bit

Timer_A3

3 CCRegisters

16MHzCPU

incl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

32kB16kB8kB

ACLK

XIN

MDB

MAB

Spy!Bi Wire

Timer_B3

3 CCRegisters,Shadow

Reg

USCI_A0:UART/LIN,IrDA, SPI

USCI_B0:SPI, I2C

OA0, OA1

2 Op Amps

ADC1010!Bit

12Channels,Autoscan,

DTC

Ports P1/P2

2x8 I/OInterrupt

capability,pull!up/down

resistors

Ports P3/P4

2x8 I/Opull!up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

NOTE: See port schematics section for detailed I/O information.

45

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46

Conclusion: MSP430 eZ430-rf2500

Development platformcheapvery limited resources

Microcontroller architectureall peripherals are memory-mappedlow-power modes

Not presented: CC2500 Radio Modulewireless communication

47