Multi-Project Reticle Design & Wafer Dicing

under Uncertain Demand

Andrew B Kahng, UC San DiegoIon Mandoiu, University of ConnecticutXu Xu, UC San DiegoAlex Zelikovsky, Georgia State University

2Images courtesy of EuroPractice and CMP

Multi-Project Wafers Mask set cost: >$1M for 90 nm technology Share cost of mask tooling between multiple designs!

Prototyping Low volume production

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Design Flow for MPW

Die Sizes + Production Volumes

Project Partitioning

Project Cloning

Reticle Floorplaning

Shotmap Definition

Dicing Plan Definition

Reticle, Wafer Shotmap, Wafer Dicing Plans

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Design Flow for MPW

Die Sizes + Production Volumes

Project Partitioning

Project Cloning

Reticle Floorplaning

Shotmap Definition

Dicing Plan Definition

Reticle, Wafer Shotmap, Wafer Dicing Plans

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Standard wafer dicing MPW dicing

Why is Dicing a Problem? Side-to-side dicing! Correctly sliced out dies

Cut lines along all four edges No cut line partitioning the die

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Side-to-side Dicing Problem

Given: Production volume for each die Reticle floorplan Wafer shot-map

Find: Horizontal and vertical dicing

plans for each wafer

To Minimize: #wafers required to meet

production volumes

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1 2

43

1 2

43

1 2

43

Dicing Strategies

Wafer Dicing Plan (DP): all horizontal and vertical cut lines used to cut a wafer

Row/Column DP: cut lines through row/column of reticle images

Single wafer dicing plan (SDP) [ISPD04] [KahngR04] The same wafer DP used for all wafers Different DPs used for different rows/cols in a wafer

Multiple wafer dicing plans (MDP) Restricted MDP: the same DP used for all rows/cols of a wafer Graph coloring based heuristic in [Xu et al. 04]

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Independent Dies

1 2

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Maximal Independent Sets: {1, 4} {2} {3}

Under restricted MDP dicing, all reticle images on wafer yield the same set of dies

Independent set: set of dies that that can be simultaneously diced from a reticle image Only maximal independent sets are of interest!

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ILP for Restricted MDP

:Subject to

:Minimize pw nn

IyxN

xn

yn

DDNyDIQ

II

IIp

IIw

CDI

max

)(),(

otherwise 0 ,0 if 1

set indep. dice toused wafers#

II

I

yx

Iy

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CMP Floorplan

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9 wafers with SDP

SDP vs. MDP

5 wafers with MDP

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4-Part Dicing

Partition each wafer into 4 parts then dice each part separately using side-to-side cuts

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Design Flow for MPW

Die sizes + Production Volumes

Project Partitioning

Project Cloning

Reticle Floorplaning

Shotmap Definition

Dicing Plan Definition

Reticle, Wafer Shotmap, Wafer Dicing Plans

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Shotmap Definition Problem

Reticle Floorplan

Shotmap #1

Shotmap #2

?

Simple grid-based shotmap definition algorithm yields an average reduction of 13.6% in #wafers

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Design Flow for MPW

Die sizes + Production Volumes

Project Partitioning

Project Cloning

Reticle Floorplaning

Shotmap Definition

Dicing Plan Definition

Reticle, Wafer Shotmap, Wafer Dicing Plans

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Given: Die sizes & production volumes Maximum reticle size

Find: Placement of dies within the reticle

To Minimize: Production cost (reticle cost, #wafers, …)

Reticle Floorplaning Problem

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Reticle Floorplaning Methods

Key challenge: cost estimation

Previous approaches Simulated annealing [ISPD04] Grid-packing [Andersson et al. 04, KahngR04] Integer programming [WuL05]

Our approach: Hierarchical Quadrisection (HQ)

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Hierarchical Quadrisection Floorplan

At most one die assigned to each region at lowest level Region widths/heights easily computed from die assignment HQ mesh more flexible than grid

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HQ Algorithm

Random initial assignment improved using simulated annealing SA moves: region exchange, die rotation Max reticle size enforced throughout the algorithm

Hierarchical structure enables quick cost estimation

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Reticle Area = 2.30 (vs. 2.45)

HQ Floorplan of CMP Testcase

4 wafers with MDP (vs. 5)

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Design Flow for MPW

Die sizes + Production Volumes

Project Partitioning

Project Cloning

Reticle Floorplaning

Shotmap Definition

Dicing Plan Definition

Reticle, Wafer Shotmap, Wafer Dicing Plans

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Project Cloning

Motivation Die-to-die inspection [Xu et al.] Reduced wafer cost when there is large variation in production

demands

Post-processing approach [WuL05] Insert clones in white space left on reticle

Our approach Before floorplaning: number of clones proportional to square root of

production volume; clones arranged in clone arrays During floorplaning: clone arrays assigned to single cell in HQ;

new SA moves: add/delete clone array row/column After floorplaning: insert additional clone array rows/columns

without increasing cell size

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Design Flow for MPW

Die sizes + Production Volumes

Project Partitioning

Project Cloning

Reticle Floorplaning

Shotmap Definition

Dicing Plan Definition

Reticle, Wafer Shotmap, Wafer Dicing Plans

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Schedule Aware Partition

More decision knobs: fabrication scheduleI will not pay you

after JuneBut, money will be saved if waiting for

other orders…?

Project Partitioning Problem Given: Reticle size, set of projects Find: Partition of projects into reticles To minimize: Sum of manufacturing cost and delay cost

[BACUS05] Schedule-aware partitioning leads to an average cost reduction of 63.8% vs. schedule-blind partitioning

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Demand Uncertainty

Customer demands (over reticle life period) may not be fully known at design time

Only rough customer demand distribution available (e.g., min/max demand)

MPW become even more attractive in this context: sharing of demand misprediction risks

Online wafer dicing combined with production of larger wafer lots can bring further economies of scale (see paper)

Feasible when there are no IP protection issues

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Given: Die sizes Maximum reticle size Distribution of customer orders

Find: Placement of dies within the reticle

To Minimize: Expected #wafers required to meet customer orders over a fixed time horizon

Robust Reticle Floorplaning

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Compared Algorithms

HQ with production volume set to the expected customer demand

HQ+Cloning with production volume set to the expected customer demand

Distribution-driven simulated annealing Use expected production cost for evaluating SA moves Monte-Carlo simulation used to estimate expected cost

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Robustness Results - Normal

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Robustness Results – Uniform

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Conclusions & Future Research

Improved MPW design flow Schedule-aware partitioning: 60% average cost reduction Project cloning: 10% average wafer cost reduction HQ reticle floorplan: 15% average wafer cost reduction Wafer shot-map definition: 13% average wafer cost reduction MDP wafer dicing: 60% average wafer cost reduction

Future work Multi-layer reticle design