NAMITEC Colloquium Campinas - 2010 Analysis and design of CMOS analog building blocks1 Analysis and...

NAMITEC ColloquiumCampinas - 2010

Analysis and design of CMOS analog building blocks 1

Analysis and Design of CMOS

Analog Building Blocks

Márcio Cherem Schneider

Universidade Federal de Santa Catarina



Contents1. The intrinsic gain stage

2. The source-coupled pair

3. The two-transistor current mirror

4.A self-biased current source



Summary of main design equations

21 1S

m ft

Ig i

n

20/ 2, , , SH ox t T EI C n n V V

/S SHI I W L A EV V L

D F R S f rI I I I i i

Saturation

/md ds D Ag g I V

Technology parameters

Size- and bias-related transistor parameters

0.35 um CMOS technology

70 nA

25 nA SHN

SHP

I

I

1 3DSsat t fV i

( )( ) ( )1 1 1 ln 1 1P S D

f r f rt

V Vi i

UICM

0G TP

V VV

n

Saturation voltage

Forward and reverse currents


Analysis and design of CMOS analog building blocks

From UICM we find the dc voltage VTH at the input:

4

THE INTRINSIC GAIN STAGE - 1

M1,M2 in saturation

Class A amplifier:

SR->SR+.

Vmax

Vmin

maximum output swing

VDSsat1

VDSsat2

VDD

VDD

vo

viVTH

vo=vi

Av

L B DI I I DI

BI

viVDD0

LI

1 11

; BD B F f

S

II I I i

I

011 1

1

1 2 ln 1 1TH Tf f

t

V Vi i

n

1 21 2

B Bds ds

A A

I Ig g

V V 1 1

021 d

m mV

o sds

g gA

g g g

1 2

1 1+

1

A A AV V V

1 2 1 2 , ,A AV V L L01 1

2

1 1A

Vt f

VA

n i

VDD

VI

M1

+

IB

CL

ID

IL

M2

~3 if0

|AV0|dB

Low-frequency gain versus inversion level



VO

VDD

VI

M+

IB

CL

ID

IL

CLgogmvgvi

+

vg vo

1o m i oV m

i i o L

v G v ZA g

v v g sC

V-I converter (transconductor) followed by an I-V converter

(output impedance)

m mG g is the transconductance

oZ is the output impedance

|AV|dB

ub0

-20 dB/dec

|AV0|

0

1

1 // ; /

V Vb

b o L u m L

A As

g C g C

Voltage gain vs frequency




VO

VDD

VI

M1

+

IB

CL

ID

IL

CLgogmvgvi

+

vg vo

0

1

1E

Vt

V LA

n ECF

minD WI m tI I g n / 1 1 / 2D WI WI fECF I I I i

1

2m

ox t

gW

L C ECF

Power-area tradeoff

How long can L be?

Sizing and biasing: W, L, IB

ECFCIN and transit time are both proportional to L2 (for constant W/L)!




VO

VDD

VI

M1

+

IB

CL

ID

IL

2 2 14 4 1ch F m c

ms msox

i K g fkTg kTg

f WLC f f

2chi

Bias-dependent factor

Thermal 1/fMOST noise model

2F

c Tt

Kf f

nq

Corner frequency

2 1/ 21

3 1 1fi

1/2 (WI) 2/3 (SI)

2000T

cf

f 0.35 um CMOS technology

2 /chi f

cf f

Noise current generator

Input-referred noise model

2 2

2

21n ch

m

be i

f g f

i

2ne

Noiseless MOST

- +




VSS

IT

+vG1

-

M1 M2

I1 I2

+vG2

-

First order analysis: Ideal current source M1 & M2 in saturation I1 & I2 independent of drain voltage;

1 2

1 2

1 2 0S S S

r r

n n n

I I I

i i

1 2

1 2

1 2

T

OD

G G id

I I I

I I I

V V V

1 1 2 2

/ /

/ / t T S od OD S

S S

i I I i I I

i I I i I I

Normalization

THE SOURCE-COUPLED PAIR -1

1 12 2

ln 1 1 1 12 2

id t od t od

t

t od t od

V i i i i

n

i i i i

1 2 1 2 t odi i i i i i

0 84 12-4-8-12

1

it=1000100

10<1

I1/IT

I2/IT

id

t

V

n



VSS

IT

+vG1

-

M1 M2

I1 I2

+vG2

-

02 01 2 1; T T T S S SV V V I I I

2ST

G OS Tm S

IIV V V

g I

Offset voltage VOS = VG =VG2- VG1 such that

ID= I2- I1=0

Simple model

0( , )f G T Si function V V V

0S mD

G TD S D

I gIV V

I I I

The differential input voltage at the input required for ID =0 is

THE SOURCE-COUPLED PAIR - 2

D S f rI I i i ir =0 (sat)

0

D Dm

T G

dI dIg

dV dV



VSS

IT

+vG1

-

M1 M2

I1 I2

+vG2

- 2 22 2

22ST

OS Tm S

IIV V

g I

2ST

G OS Tm S

IIV V V

g I

22 22

2; SVT IS

TS

IA AV

WL I WL

Pelgrom’s

model

22 2

2

2VT IST

OSm

A AIV

WL g WL

1 1

2 2fT D

tm m

iI In

g g

Uncorrelated VT & IS

Notes:

ISA A

0.35 um CMOS technology

5 10 mV m

1 2 % mVTA

A

THE SOURCE-COUPLED PAIR - 3

(I) (II)

(I) is dominant over (II) for

21 1 VT

ft IS

Ai

n A

575 for 32 mV

8 mV m, 2 % m

f t

VT

i n

A A



THE TWO-TRANSISTOR CURRENT MIRROR - 1VDD

ii

+vG

-

iovo

+-

M1 M2

1:1

M1: iv converterM2: vi converter

Basic principle VG1=VG2; VS1=VS2; vout>VDsat ioii

iD

vD

locus vD=vG

vG

vo

iD1

iD2

, 1 / D S G T S D A D DsatI I f V V V V V V V

o i o i o i

i i A E

i i v v v vi

i i V V L

Error due to difference in VD’s Error due to mismatch

00

0

1

D D DS T

D D S T

S mT

S D

I I II V

I I I V

I gV

I I

2 22 22

2 2

1D Sm mT VT IS

D D S D

I Ig gV A A

I I I WL I



1 1 1 2 2 1 2

1 1 1 1 2 1

gs gb gs gb db

gs gb db ovd

C C C C C C C

C A C C C C

1:A

1 1 20

2 2 20

o

i

i mv

o ds dbi

Y g s C C

Y g s C C

2mg v1

1

m

ds

g

g

ii

+v-

io

C1

C2

iiio

M1 M2

VDD

1

1

1

1 2o

i mg T

I CA As

I s g f

iin

io

M1 M2i1

i21:A

2

2 2 2 22 21 2

1 1

2 2 2 2 21 1

m mo in

m m

o in

g gi i i i A

g g

i A i i Ai

Uncorrelated noise sourcesNoise analysis

ac analysis

The effect of M1 on noise is A times greater than that of M2

THE TWO-TRANSISTOR CURRENT MIRROR - 2



Gain-of-two current mirrors

VDD

IIIO

1/2:1

W/L

W/L

W/L

VDD

II IO

1:2

W/L

W/LW/L

CURRENT MIRROR: GAIN SCHEMES

VDD

ii io==Aii

......

VDD

ii io==ii/A

......

Gain=A

Gain= 1/A

ii

io==ii/(NM)

.....

.

......N

M

Gain=1/(NM)



A SELF-BIASED CURRENT SOURCE – 1

21 2 2

1

11 1f f f

Si i i

S N

2

2 2

2

1 11 1 ln

1 1

fXf f

t f

iVi i

i

2 2

1 1 2( ) ( 1)

S f x

S f f x

I i NI

I i i N I

Applying UICM to both M1 & M2

2 1f ri i

Sat.

Triode

2 xI NI

SELF-CASCODE MOSFET (SCM)



V-I CHARACTERISTICS OF THE SCM

2

2 2

2

1 11 1 ln

1 1

ln

fXf f

t f

X t

iVi i

i

V

In WI:

2

1

11 1

S

S N

Sat.

Triode

I2=NIx




VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)1

9 ln( )ref S tV V JK

1 B. Gilbert, AICSP vol. 38, pp. 83-101, Feb. 2004

When both M8 & M9 operate in WI:

898 8

8

1 11 1 ln

1 1

fref Sf f

t f

JKiV VJKi i

i




A self-biased current source

Vx

VFCMVx




VFCM

A SBCS – 5: DESIGN

2

1

11 1 1 1 1 3

S

S N

1 30 11 30 1 10 ln 2.93

1 10 1X

t

V

M1 &M2 in MI: if2 = 10 S2= S1, N = 1

2

2 2

2

1 11 1 ln

1 1

fXf f

t f

iVi i

i

Let us choose

M3 &M4 in WI: if3(4) <<1

2.93ln 18.7X

t

Ve

4 4

3 3

118.7 1 1 8.85

1

S S

S S

Output current: Iref=10 nA

ISHn-channel100 nA, ISHp-channel40 nA

=1

=10 nA

2 2 2 2 110 nA 1 nA 0.01 S f SI i I S S Let us choose if3=0.187 4 3 4 3/ 1 2 / 0.01f fi i S S 4 4 4 410 nA 1 A 10S f SI i I S

43 1.13

8.85

SS



A SBCS – 6: DESIGN

S if ir

M1 0.01 10 0

M2 0.01 30 10

M3 1.13 0.187 0.01

M4 10 0.01 0

M8, M8(a) 1 0. 1 0

M9, M9(a) 1 0. 1 0

MP (all) 2.5 0.1 0

4 10S

VFCM

=1

=10 nA

2 1 0.0S

2.93X tV 2.93X tV 3 1.13S 1 1 0.0S

Summary



A SBCS – 7 : IOUT vs. VDD AT CONSTANT T



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NAMITEC Colloquium Campinas - 2010 Analysis and design of CMOS analog building blocks1 Analysis and...

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