NAVSEA AD6640 Total Dose Test Report - NASA · Test Report Final Report Prepared for: NASA GSFC/J&T...

NAVSEA AD6640 Total DoseTest Report

Final Report

Prepared for:NASA GSFC/J&TCode 562.1GreenBelt, MD 20771

Prepared by:NAVSEA Crane - Surface Warfare Center DivisionJohn P. Bings, October 30, 2001Code 6054, Building 2088300 Highway 361Crane, IN 47522-5001

Surface Warfare Center

Summary

NAVSEA Crane Division performed total dose testing on a total of five Analog Devices AD6640,12 bit ADC’s; three parts were statically biased, two dynamically biased. Results of the total dosetesting indicate:• AD6640 experienced no functional or parametric failures up to 30krad(Si).• Two AD6640s were tested to 100krad(Si) and no functional or parametric failures were

observed.• No significant changes in aperture uncertainty jitter were noted up to 30krad(Si), nor for the

two devices tested up to 100krad(Si).

Introduction

Purpose

This testing was performed to provide parametric and radiation hardness performanceinformation on the AD6640 ADC for NASA.

Background

The AD6640 is a commercial 12 bit, 65 MHz monolithic ADC manufactured by Analog DevicesInc. on their XFCB 1.5 process. The units are packaged in a 44 terminal Plastic Thin QuadFlatpack (TQFP). A total of 2 Analog Devices evaluation boards were used for testing. Theevaluation boards were pre-manufactured, unpopulated boards made by ADI to aid customers inevaluation of their product. The evaluation boards were modified for use in Co-60 and populatedby NAVSEA Crane Division.

Test Samples

A total of five AD6640’s (serial numbers 1, 3, 4, 6 and 7) were tested. All devices had a datecode of 9951.

Table 1 gives a summary of the AD6640 specifications of interest.

AD6640Resolution 12 bitsSpeed 65 MSPSPower Consumption (max) 865 mWAnalog Input 2.0 V peak-peakDNL ±0.5LSB (typical)SINAD 68 dB at 2.2 MHzENOB 11.0 bits typical at 2.2 MHzAperture Uncertainty (Jitter) 0.3 ps rms typical, <1.0ns for NASA testing

Table 1 – AD6640 Specifications of interest(Refer to AD6640 Specification Sheet in Appendix B for further information.)

Facilities

All testing was performed at NAVSEA Crane Code 6054, using a Shepherd Model 484 Cobalt-60tunnel irradiator.

Test Setup

The electrical testing was done on a customized ADC test bench. The ADC test bench utilized aHP6626A System DC Power Supply, two HP 8644(A&B) Synthesized Signal Generators, a HP3458A Multimeter and an HP8131A Pulse Generator. A HP16500B Logic Analyzer was addedfor high-speed data capture facilitating aperture uncertainty (jitter) measurements. An HP82000ATE was used for parametric tests as well as some dynamic functional testing. ADI providedevaluation boards that served as a test fixture to route power, input and output signals betweenthe test device and the acquisition system. A picture of a populated test board used for bias andtesting is shown in Figure 1. Two fully populated boards were used and the three additional partstested were swapped into these populated boards. All parts were retained for possible futuretesting and analysis, if required.

Figure 1 - Populated Evaluation Board

Three parts were tested with a static bias applied during irradiation and the remaining two partswere tested with a dynamic bias applied. Static bias devices were irradiated with nominal DCpower applied and the clock, and all other inputs grounded. Dynamic bias used the samenominal DC power as the static bias condition, a 62.5 MHz Encode clock signal and a 1 MHz, 1.7volt peak-to-peak amplitude sinusoidal input signal.

The parameters tested were signal-to-noise and distortion (SINAD), effective number of bits(ENOB), aperture uncertainty jitter, total harmonic distortion (THD) and Differential Non-Linearity(DNL). Functional power supply currents and the DC Parameters were measured using anHP82000.

Aperture uncertainty (jitter) is a calculated value of two separate measured values. The AnalogDevices application note containing the procedure for calculating aperture uncertainty (jitter) canbe found in Appendix C.

Bias conditions used for total dose tests:

Static Bias for parts #1 and #6: DVdd = +3.3V; AVdd = +5.0V Clock = GND Ain = GND

Dynamic Bias for parts #3, #4 and #7: DVdd = +3.3V; AVdd = +5.0V Clock = 62.5 MHz Ain = 1.0226 MHz

Voltage output low (Vol) and voltage output high (Voh) were measured at two separate currentloads shown as follows:

Voh -> -6mA Vol -> 6mAVoh2 -> -4mA Vol2 -> 4mA

Power supply currents were monitored during irradiation. All testing was performed using a doserate of 49.5 rad(Si)/sec. The dose increments of interest were 2.5, 5.0, 7.5, 10, 20, 30 and 100krad (Si).

Test Results

AD6640

No significant degradation was observed on all devices up to 30krad(Si) for all measuredparameters. Two of the five tested devices were taken up to 100krad(Si) and again showed nosignificant degradation in any measured parameter. Figure 2 shows the Effective Number of Bits(ENOB) versus total dose and Figure 3 shows the Aperture Uncertainty Jitter versus total dose.Figures 4 and 5 show Differential Nonlinearity (DNL) maximum and minimum versus total dose.As can be seen from these graphs, there was no significant degradation to 100krad(Si).

Total Dose (rad(Si))100 103 104 105

Eff

ecti

ve N

um

ber

of

Bit

s

10

11

12Part #1 - Static BiasPart #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias

Dose Rate = 49.5 rad(Si)/sec

Figure 2

The apparent spike on devices 1 and 3 in Figure 3 was caused by a minor timing problem withthe hardware used to capture the data and was unrelated to radiation exposure. This timingissue showed up as a higher calculated aperture uncertainty.


Ap

ertu

re U

nce

rtai

nty

Jit

ter

(ps

rms)

1

2

3

4

5

6

7

8

9

10

Part #1 - Static BiasPart #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias


Figure 3


Min

imu

m D

iffe

ren

tial

No

n L

inea

rity

(L

SB

)

-1

0

1

Part #1 - Min DNLPart #3 - Min DNLPart #4 - Min DNLPart #6 - Min DNLPart #7 - Min DNL


Figure 4


Max

imu

m D

iffe

ren

tial

No

n L

inea

rity

(L

SB

)

-1

0

1

Part #1 - Max DNLPart #3 - Max DNLPart #4 - Max DNLPart #6 - Max DNLPart #7 - Max DNL


Figure 5

Appendix A contains graphs of all the device parameters measured by this test. The DCparametric data graphs showing Vol, Voh, Vol2 and Voh2 show no significant change with devicedose. The parametric data for Device 1 was taken at a digital supply voltage of 5.0V whichappears as a higher Vol, Voh, Vol2 and Voh2 for that device, however its change with device dosewas also insignificant. The parametric data graphs shown are the average of 12 measurementstaken on the device pins and the variances in these data are shown representationally by errorbars. The graphs of Analog and Digital supply currents likewise show no significant shift withdevice dose.

Conclusions

Since the AD6640 was built on Analog Devices’ high speed complimentary bipolar process(XFCB) it is not surprising there was no significant degradation in any measured parameter forthis total dose test. Even when taken to 100krad(Si) no parameter showed any significantchange. No additional testing of the AD6640 is suggested.

Any questions or comments should be directed to John Bings, 812-854-1672,[email protected] or John Seiler, 812-854-2074, [email protected] acknowledgement and thanks to Mark Savage for his help with these graphs.

Appendix AAll Graphs


Eff

ecti

ve N

um

ber

of

Bit

s

10

11

12Part #1 - Static BiasPart #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias



Ap

ertu

re U

nce

rtai

nty

Jit

ter

(ps

rms)

1

2

3

4

5

6

7

8

9

10

Part #1 - Static BiasPart #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias



Min

imu

m D

iffe

ren

tial

No

n L

inea

rity

(L

SB

)

-1

0

1

Part #1 - Min DNLPart #3 - Min DNLPart #4 - Min DNLPart #6 - Min DNLPart #7 - Min DNL



Max

imu

m D

iffe

ren

tial

No

n L

inea

rity

(L

SB

)

-1

0

1

Part #1 - Max DNLPart #3 - Max DNLPart #4 - Max DNLPart #6 - Max DNLPart #7 - Max DNL



An

alo

g S

up

ply

Cu

rren

t (A

)

0.1350

0.1355

0.1360

0.1365

0.1370

0.1375

0.1380

0.1385

0.1390

0.1395

0.1400Part #1 - Static BiasPart #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias



Dig

ital

Su

pp

ly C

urr

ent

(A)

0.010

0.012

0.014

0.016

0.018

0.020

0.022

0.024

0.026

0.028

0.030Part #1 - Static BiasPart #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias



Vo

l(mV

)

350

400

450

500

550

600

650

700

750

800



Vo

l(mV

)

350

400

450

500

550

600

650

700

750

800Part #1 - Static Bias (DVcc=5.0)Part #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias


Vo

h(m

V)

2400

2700

3000

3300

3600

3900

4200

4500

4800

5100

5400


2400

2700

3000

3300

3600

3900

4200

4500

4800

5100

5400Part #1 - Static Bias DVcc=5.0Part #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias



Vo

l2(m

V)

300

330

360

390

420

450

480

510

540

570

600



Vo

l2(m

V)

300

330

360

390

420

450

480

510

540

570

600Part #1 - Static Bias DVcc=5.0Part #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias


Vo

h2(

mV

)

2500

2800

3100

3400

3700

4000

4300

4600

4900

5200

5500

5800



Vo

h2(

mV

)

2500

2800

3100

3400

3700

4000

4300

4600

4900

5200

5500

5800Part #1 - Static Bias DVcc=5.0 Part #3 Dynamic BiasPart #4 Dynamic BiasPart #6 Static BiasPart #7 Dynamic Bias


To

tal H

arm

on

ic D

isto

rtio

n (

dB

)

-90

-88

-86

-84

-82

-80

-78

-76

-74

-72

-70Part #1 - Static BiasPart #3 - Dynamic BiasPart #4 - Dynamic BiasPart #6 - Static BiasPart #7 - Dynamic Bias


Appendix BAD6640 Specification Sheet

a 12-Bit, 65 MSPSIF Sampling A/D Converter

FEATURES

65 MSPS Minimum Sample Rate

80 dB Spurious-Free Dynamic Range

IF-Sampling to 70 MHz

710 mW Power Dissipation

Single +5 V Supply

On-Chip T/H and Reference

Twos Complement Output Format

3.3 V or 5 V CMOS-Compatible Output Levels

APPLICATIONS

Cellular/PCS Base Stations

Multichannel, Multimode Receivers

GPS Anti-Jamming Receivers

Communications Receivers

Phased Array Receivers

FUNCTIONAL BLOCK DIAGRAM

ADCATH3

DACADC

TH2BUF TH1

MSB LSB

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DIGITAL ERROR CORRECTION LOGIC

7

GND

6

AIN

AIN

VREF

ENCODEENCODE

+2.4VREFERENCE

INTERNALTIMING

AVCC DVCC

AD6640

PRODUCT DESCRIPTIONThe AD6640 is a high speed, high performance, low power,monolithic 12-bit analog-to-digital converter. All necessaryfunctions, including track-and-hold (T/H) and reference areincluded on-chip to provide a complete conversion solution.The AD6640 runs on a single +5 V supply and provides CMOS-compatible digital outputs at 65 MSPS.

Specifically designed to address the needs of multichannel,multimode receivers, the AD6640 maintains 80 dB spurious-free dynamic range (SFDR) over a bandwidth of 25 MHz.Noise performance is also exceptional; typical signal-to-noiseratio is 68 dB.

The AD6640 is built on Analog Devices’ high speed complemen-tary bipolar process (XFCB) and uses an innovative multipassarchitecture. Units are packaged in a 44-terminal Plastic ThinQuad Flatpack (TQFP) specified from –40°C to +85°C.

PRODUCT HIGHLIGHTS1. Guaranteed sample rate is 65 MSPS.2. Fully differential analog input stage specified for frequencies

up to 70 MHz; enables “IF Sampling.”3. Low power dissipation: 710 mW off a single +5 V supply.4. Digital outputs may be run on +3.3 V supply for easy inter-

face to digital ASICs.5. Complete Solution: reference and track-and-hold.6. Packaged in small, surface mount, plastic 44-terminal TQFP.

AD6640

REV. 0

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1998

DC SPECIFICATIONSTest AD6640AST

Parameter Temp Level Min Typ Max Units

RESOLUTION 12 Bits

ACCURACYNo Missing Codes +25°C I GUARANTEEDOffset Error Full VI –10 3.5 +10 mVGain Error Full VI –10 4.0 +10 % FSDifferential Nonlinearity (DNL)1 +25°C I –1.0 ± 0.5 +1.5 LSBIntegral Nonlinearity (INL)1 Full V ± 1.25 LSB

TEMPERATURE DRIFTOffset Error Full V 50 ppm/°CGain Error Full V 100 ppm/°C

POWER SUPPLY REJECTION (PSRR) Full V ± 0.5 mV/V

REFERENCE OUT (VREF)2 Full V 2.4 V

ANALOG INPUTS (AIN, AIN)3

Analog Input Common-Mode Range4 Full V VREF ± 0.05 VDifferential Input Voltage Range Full V 2.0 V p-pDifferential Input Resistance Full IV 0.7 0.9 1.1 kΩDifferential Input Capacitance +25°C V 1.5 pF

POWER SUPPLYSupply Voltage

AVCC Full VI 4.75 5.0 5.25 VDVCC Full VI 3.0 3.3 5.25 V

Supply CurrentIAVCC (AVCC = 5.0 V) Full VI 135 160 mAIDVCC (DVCC = 3.3 V) Full VI 10 20 mA

POWER CONSUMPTION Full VI 710 865 mW

NOTES1ENCODE = 20 MSPS2If VREF is used to provide a dc offset to other circuits, it should first be buffered.3The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels VREF ± 0.5 volts. The input signals should be 180 degrees out of phase toproduce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.

4Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).Specifications subject to change without notice.

DIGITAL SPECIFICATIONSTest AD6640AST

Parameter Temp Level Min Typ Max Units

LOGIC INPUTS (ENC, ENC)1

Encode Input Common-Mode Range2 Full IV 0.2 2.2 VDifferential Input Voltage Full IV 0.4 V p-pSingle-Ended Encode 10 V p-p

Logic Compatibility3 TTL/CMOSLogic “1” Voltage Full VI 2.0 5.0 VLogic “0” Voltage Full VI 0 0.8 VLogic “1” Current (VINH = 5 V) Full VI 500 650 800 µALogic “0” Current (VINL = 0 V) Full VI –400 –320 –200 µA

Input Capacitance +25°C V 2.5 pF

LOGIC OUTPUTS (D11–D0)4

Logic Compatibility CMOSLogic “1” Voltage (DVCC = +3.3 V) Full VI 2.8 DVCC – 0.2 VLogic “0” Voltage (DVCC = +3.3 V) Full VI 0.2 0.5 VLogic “1” Voltage (DVCC = +5.0 V) Full IV 4.5 DVCC – 0.3 VLogic “0” Voltage (DVCC = +5.0 V) Full IV 0.35 0.5 VOutput Coding Twos Complement

NOTES1Best dynamic performance is obtained by driving ENC and ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power isshown in Figure 18 under Typical Performance Characteristics.

2For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimumdifferential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that theinput voltage on either encode pin does not go below 0 V. The maximum value insures that the input voltage on either encode pin does not go below 2.0 V or above AVCC (e.g.,for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).

3ENC or ENC may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that TTL or CMOS clock sourceswill work. When driving only one encode input, bypass the complementary input to GND with 0.01 µF.

4Digital output load is one LCX gate.Specifications subject to change without notice.

REV. 0

(AVCC = +5 V, DVCC = +3.3 V; TMIN = –408C, TMAX = +858C)

–2–

AD6640–SPECIFICATIONS

(AVCC = +5 V, DVCC = +3.3 V; TMIN = –408C, TMAX = +858C)

SWITCHING SPECIFICATIONS1

Test AD6640ASTParameter (Conditions) Temp Level Min Typ Max Units

Maximum Conversion Rate Full VI 65 MSPSMinimum Conversion Rate2 Full IV 6.5 MSPSAperture Delay (tA) +25°C V 400 psAperture Uncertainty (Jitter) +25°C V 0.3 ps rmsENCODE Pulsewidth High3 +25°C IV 6.5 nsENCODE Pulsewidth Low +25°C IV 6.5 nsOutput Delay (tOD) DVCC +3.3 V/5.0 V4 Full IV 8.5 10.5 12.5 ns

NOTES1All switching specifications tested by driving ENCODE and ENCODE differentially.2A plot of Performance vs. Encode is shown in Figure 16 under Typical Performance Characteristics.3A plot of Performance vs. Duty Cycle (Encode = 65 MSPS) is shown in Figure 17 under Typical Performance Characteristics.4Outputs driving one LCX gate. Delay is measured from differential crossing of ENC, ENC to the time when all output data bits are within valid logic levels.

Specifications subject to change without notice.

AC SPECIFICATIONS1

Test AD6640ASTParameter (Conditions) Temp Level Min Typ Max Units

SNRAnalog Input 2.2 MHz +25°C V 68 dB@ –1 dBFS 15.5 MHz +25°C I 64 67.7 dB

31.0 MHz +25°C V 67.5 dB69.0 MHz +25°C V 66 dB

SINADAnalog Input 2.2 MHz +25°C V 68 dB@ –1 dBFS 15.5 MHz +25°C I 63.5 67.2 dB

31.0 MHz +25°C V 67.0 dB69.0 MHz +25°C V 65.5 dB

Worst Harmonic2 (2nd or 3rd)Analog Input 2.2 MHz +25°C V 80 dBc@ –1 dBFS 15.5 MHz +25°C I 74 80 dBc

31.0 MHz +25°C V 79.5 dBc69.0 MHz +25°C V 78.5 dBc

Worst Harmonic2 (4th or Higher)Analog Input 2.2 MHz +25°C V 85 dBc@ –1 dBFS 15.5 MHz +25°C I 74 85 dBc

31.0 MHz +25°C V 85 dBc69.0 MHz +25°C V 84 dBc

Multitone SFDR (w/Dither)3

Eight Tones @ –20 dBFS Full V 90 dBFS

Two-Tone IMD Rejection4

F1, F2 @ –7 dBFS Full V 80 dBc

Analog Input Bandwidth5 +25°C V 300 MHz

NOTES1All ac specifications tested by driving ENCODE and ENCODE differentially.2For a single test tone at –1 dBFS, the worst case spectral performance is typically limited by the direct or aliased 2nd or 3rd harmonic. If a system is designed suchthat the 2nd and 3rd harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst Harmonic (4th or Higher) includes4th and higher order harmonics and all other spurious components. Reference Figure 12 for more detail.

3See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. To measure SFDR, eight tones from 14 MHz to 18 MHz(0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR.

4F1 = 14.9 MHz, F2 = 16 MHz.5Specification is small signal bandwidth. Plots of Performance versus Analog Input Frequency are shown in Figures 10, 11 and 12. Sampling wide bandwidths(5 MHz–15 MHz) should be limited to 70 MHz center frequency.

Specifications subject to change without notice.

REV. 0 –3–

AD6640

(AVCC = +5 V, DVCC = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –408C, TMAX = +858C)

(AVCC = +5 V, DVCC = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –408C, TMAX = +858C)

AD6640

–4– REV. 0

ABSOLUTE MAXIMUM RATINGS1

Parameter Min Max Units

ELECTRICALAVCC Voltage 0 7 VDVCC Voltage 0 7 VAnalog Input Voltage 0 AVCC VAnalog Input Current 25 mADigital Input Voltage (ENCODE) 0 AVCC VDigital Output Current –10 10 mA

ENVIRONMENTAL2

Operating Temperature Range(Ambient) –40 +85 °C

Maximum Junction Temperature +150 °C Lead Temperature (Soldering, 10 sec) +300 °C Storage Temperature Range (Ambient) –65 +150 °CNOTES1Absolute maximum ratings are limiting values to be applied individually, andbeyond which the serviceability of the circuit may be impaired. Functionaloperability is not necessarily implied. Exposure to absolute maximum ratingconditions for an extended period of time may affect device reliability.

2Typical thermal impedances (44-terminal TQFP); θJA = 55°C/W.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD6640AST –40°C to +85°C (Ambient) 44-Terminal TQFP (Thin Quad Plastic Flatpack) ST-44AD6640ST/PCB Evaluation Board with AD6640AST

EXPLANATION OF TEST LEVELSTest LevelI – 100% production tested.II – 100% production tested at +25°C, and sample tested at

specified temperatures. AC testing done on samplebasis.

III – Sample tested only.IV – Parameter is guaranteed by design and characterization

testing.V – Parameter is a typical value only.VI – All devices are 100% production tested at +25°C; sample

tested at temperature extremes.

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD6640 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

AD6640

REV. 0 –5–

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1, 2, 36, 37, 40, 41 DVCC +3.3 V/+5 V Power Supply (Digital). Powers output stage only.3 ENCODE Encode Input. Data conversion initiated on rising edge.4 ENCODE Complement of ENCODE. Drive differentially with ENCODE or bypass to

Ground for single-ended clock mode. See Encoding the AD6640 section.5, 6, 13, 14, 17, 18, 21,22, 24, 34, 35, 38, 39 GND Ground.7 AIN Analog Input.8 AIN Complement of Analog Input.9 VREF Internal Voltage Reference. Nominally +2.4 V. Bypass to Ground with

0.1 µF + 0.01 µF microwave chip capacitor.10 C1 Internal Bias Point. Bypass to ground with 0.01 µF capacitor.11, 12, 15, 16, 19, 20 AVCC +5 V Power Supply (Analog).23 NC No Connect.25 D0 (LSB) Digital Output Bit (Least Significant Bit).26–33 D1–D8 Digital Output Bits.42, 43 D9–D10 Digital Output Bits.44 D11 (MSB)1 Digital Output Bit (Most Significant Bit).

NOTE1Output coded as twos complement.

PIN CONFIGURATION

3

4

5

6

7

1

2

10

11

8

9

40 39 3841424344 36 35 3437

29

30

31

32

33

27

28

25

26

23

24

12 13 14 15 16 17 18 19 20 21 22

PIN 1

TOP VIEW(Not to Scale)

AV

CC

AV

CC

AV

CC

AV

CC

AV

CC

D8

D7

D6

D5

D4

D3

D2

AD6640

DVCC

DVCC

ENCODE

ENCODE

GND

GND

AIN

NC = NO CONNECT

VREF

C1

AVCC

D1

D0 (LSB)

GND

NC

D11

(M

SB

)

GN

D

GN

D

GN

D

GN

D

D10

GN

D

GN

D

GN

D

GN

D

GN

D

D9

DV

CC

DV

CC

DV

CC

DV

CC

GN

D

AIN

AD6640

–6– REV. 0

DEFINITION OF SPECIFICATIONSAnalog Bandwidth (Small Signal)The analog input frequency at which the spectral power of thefundamental frequency (as determined by the FFT analysis) isreduced by 3 dB.

Aperture DelayThe delay between a differential crossing of ENCODE andENCODE and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter)The sample-to-sample variation in aperture delay.

Differential NonlinearityThe deviation of any code from an ideal 1 LSB step.

Encode Pulsewidth/Duty CyclePulsewidth high is the minimum amount of time that the EN-CODE pulse should be left in logic “1” state to achieve ratedperformance; pulsewidth low is the minimum time ENCODEpulse should be left in low state. At a given clock rate, thesespecs define an acceptable Encode duty cycle.

Integral NonlinearityThe deviation of the transfer function from a reference linemeasured in fractions of 1 LSB using a “best straight line”determined by a least square curve fit.

Minimum Conversion RateThe encode rate at which the SNR of the lowest analog signalfrequency drops by no more than 3 dB below the guaranteedlimit.

Maximum Conversion RateThe encode rate at which parametric testing is performed.

Output Propagation DelayThe delay between a differential crossing of ENCODE andENCODE and the time when all output data bits are withinvalid logic levels.

Power Supply Rejection RatioThe ratio of a change in input offset voltage to a change inpower supply voltage.

Signal-to-Noise-and-Distortion (SINAD)The ratio of the rms signal amplitude (set at 1 dB below fullscale) to the rms value of the sum of all other spectral compo-nents, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)The ratio of the rms signal amplitude (set at 1 dB below fullscale) to the rms value of the sum of all other spectral compo-nents, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)The ratio of the rms signal amplitude to the rms value of thepeak spurious spectral component. The peak spurious compo-nent may or may not be a harmonic. May be reported in dBc(i.e., degrades as signal levels is lowered), or in dBFS (alwaysrelated back to converter full scale).

Two-Tone Intermodulation Distortion RejectionThe ratio of the rms value of either input tone to the rmsvalue of the worst third order intermodulation product; re-ported in dBc.

Two-Tone SFDRThe ratio of the rms value of either input tone to the rms valueof the peak spurious component. The peak spurious componentmay or may not be an IMD product. May be reported in dBc(i.e., degrades as signal levels is lowered), or in dBFS (alwaysrelated back to converter full scale).

Worst HarmonicThe ratio of the rms signal amplitude to the rms value of theworst harmonic component, reported in dBc.

REV. 0 –7–REV. 0 –7–

Equivalent Circuits–AD6640

450V

BUF T/H

BUF

450V

BUF T/H

AIN

AIN

VREF

AVCCVCH

AVCCVCH

VCL

VCL

Figure 2. Analog Input Stage

AVCC

AVCC

TIMINGCIRCUITSR2

8kVR2

8kV

R117kV

R117kV

ENCODE ENCODE

AVCC

Figure 3. Encode Inputs

AVCC

AVCC

C1

CURRENTMIRROR

VREF

AVCC

Figure 4. Compensation Pin, C1

VREF

DVCC

DVCC

CURRENTMIRROR

D0–D11

CURRENTMIRROR

Figure 5. Digital Output Stage

VREF

AVCC

0.5mA

2.4V

AVCC

Figure 6. 2.4 V Reference

NDIGITAL OUTPUTS

(D11–D0)N – 1N – 2

tA

N + 1

tOD

ANALOGINPUTS

ENCODE INPUTS(ENCODE)

N

AIN

AIN

Figure 1. Timing Diagram

AD6640

–8– REV. 0

–Typical Performance Characteristics

FREQUENCY – MHz

0

60

100

dc 32.5

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB

6.5 13.0 19.5 26.0

40

80

20

120

ENCODE = 65MSPSAIN = 2.2MHz

4 8 953 762

Figure 7. Single Tone at 2.2 MHz

FREQUENCY – MHz

0

60

100

dc 32.5

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB

6.5 13.0 19.5 26.0

40

80

20

120


4 8 9 5 3 7 6 2


FREQUENCY – MHz

0

60

100

dc 32.5

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB

6.5 13.0 19.5 26.0

40

80

20

120


4 8 9 5 3762


ANALOG INPUT FREQUENCY – MHz0 707

WO

RS

T C

AS

E H

AR

MO

NIC

– d

Bc

14 21 28 35 42 49 56 63

81

79

78

77

80

T = +25 C

T = –40 C, +85 C

ENCODE = 65MSPS TEMP = –40 C, +25 C, & +85 C

Figure 10. Harmonics vs. AIN

ANALOG INPUT FREQUENCY – MHz0 707

SN

R –

dB

14 21 28 35 42 49 56 63

69

67

66

65

68

ENCODE = 65MSPS TEMP = –40 C, +25 C, & +85 C

T = +25 C

T = –40 C

T = +85 C

Figure 11. Noise vs. AIN

ENCODE = 65MSPS

ANALOG INPUT FREQUENCY – MHz

90

80

301 10010

SN

R, H

AR

MO

NIC

S –

dB

, dB

c

60

50

40

70

2 4 20 40 200 300

WORST OTHER SPUR

HARMONICS (2nd, 3rd)

SNR

Figure 12. Harmonics, Noise vs. AIN

AD6640

REV. 0 –9–

FREQUENCY – MHz

0

60

100

dc 32.5

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB

6.5 13.0 19.5 26.0

40

80

20

120

ENCODE = 65MSPSAIN = 15.0, 16.0MHzNO DITHER

Figure 13. Two Tones at 15.0 MHz & 16.0 MHz

ANALOG INPUT POWER LEVEL – dBFS

100

0–80 0–70

WO

RS

T C

AS

E S

PU

RIO

US

– d

Bc

and

dBF

S

–60 –50 –40 –30 –20 –10

90

60

40

20

10

80

70

50

30

ENCODE = 65MSPS AIN = 31.0MHz

dBFS

dBc

SFDR = 80dB REFERENCE LINE

Figure 14. Single Tone SFDR

INPUT POWER LEVEL (F1 = F2) – dBFS

100

0–80 0–70

WO

RS

T C

AS

E S

PU

RIO

US

– d

Bc

and

dBF

S

–60 –50 –40 –30 –20 –10

90

60

40

20

10

80

70

50

30

ENCODE = 65MSPS F1 = 15.0MHz F2 = 16.0MHz

SFDR = 80dB REFERENCE LINE

dBFS

dBc

Figure 15. Two Tone SFDR

SAMPLE RATE – MSPSdc 808

SN

R, W

OR

ST

CA

SE

SP

UR

IOU

S –

dB

, dB

c

16 24 32 40 48 56 64 72

80

70

65

60

75

AIN = 19.5MHz

SNR

WORST SPUR

85

Figure 16. SNR, Worst Spurious vs. Encode

ENCODE DUTY CYCLE – %25 7530

SN

R, W

OR

ST

FU

LL S

CA

LE S

PU

RIO

US

– d

B, d

Bc

35 40 45 50 55 60 65 70

90

65

55

45

75

85

80

70

60

50

40

35

30

ENCODE = 65MSPS AIN = 2.2MHz

WORST SPUR

SNR

Figure 17. SNR, Worst Spurious vs. Duty Cycle

ENCODE POWER – dBm–15 15–12S

NR

, WO

RS

T F

ULL

SC

ALE

SP

UR

IOU

S –

dB

, dB

c

–9 –6 –3 0 3 6 9 12

90

65

55

45

75

85

80

70

60

50

40

35

30

ENCODE = 65MSPS WORST SPUR

SNR

2.2MHz

2.2MHz

69MHz

69MHz

Figure 18. SNR, Worst Spurious vs. Encode Power

AD6640

–10– REV. 0

dc

0

–80

–120

–40

–100

–20

–60

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB ENCODE = 65MSPS

AIN = 19.5MHz @ –36dBFS NO DITHER

65 13.0 19.5 26.0 32.5FREQUENCY – MHz

Figure 19. 16K FFT without Dither


100

0–80 0–70

WO

RS

T C

AS

E S

PU

RIO

US

– d

Bc

–60 –50 –40 –30 –20 –10

90

60

40

20

10

80

70

50

30

ENCODE = 65MSPSAIN = 19.5MHzNO DITHER

SFDR = 80dBREFERENCE LINE

Figure 20. SFDR without Dither

50 7555 60 65 70FREQUENCY – MHz

0

–80

–120

–40

–100

–20

–60

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB ENCODE = 50MSPS

AIN = 65.5, 68.5MHzNO DITHER

–60

–90

–120

–30

0

ANALOG IFFILTER MASK

ALIASEDSIGNALS

Figure 21. IF-Sampling at 70 MHz without Dither

0

–80

–120

–40

–100

–20

–60

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB

ENCODE = 65MSPSAIN = 19.5MHz @ –36dBFSDITHER = –32.5dBm

dc 65 13.0 19.5 26.0 32.5FREQUENCY – MHz

Figure 22. 16K FFT with Dither


100

0–80 0–70

WO

RS

T C

AS

E S

PU

RIO

US

– d

Bc

–60 –50 –40 –30 –20 –10

90

60

40

20

10

80

70

50

30

ENCODE = 65MSPSAIN = 19.5MHzDITHER = –32.5dBm

SFDR = 80dBREFERENCE LINE

Figure 23. SFDR with Dither

50 7555 60 65 70FREQUENCY – MHz

0

–80

–120

–40

–100

–20

–60

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB

ENCODE = 50MSPSAIN = 65.5MHz, 68.5MHzDITHER = –32.5dBm

–60

–90

–120

–30

0


ALIASEDSIGNALS

Figure 24. IF-Sampling at 70 MHz with Dither

AD6640

REV. 0 –11–

THEORY OF OPERATIONThe AD6640 analog-to-digital converter (ADC) employs a two-stage subrange architecture. This design approach ensures12-bit accuracy, without the need for laser trim, at low power.

As shown in the functional block diagram, the AD6640 hascomplementary analog input pins, AIN and AIN. Each analoginput is centered at 2.4 volts and should swing ± 0.5 voltsaround this reference (ref. Figure 2). Since AIN and AIN are180 degrees out of phase, the differential analog input signal is2 volts peak-to-peak.

Both analog inputs are buffered prior to the first track-and-hold,TH1. The high state of the ENCODE pulse places TH1 inhold mode. The held value of TH1 is applied to the input of a6-bit coarse ADC. The digital output of the coarse ADC drivesa 6-bit DAC; the DAC is 12 bits accurate. The output of the 6-bit DAC is subtracted from the delayed analog signal at theinput of TH3 to generate a residue signal. TH2 is used as ananalog pipeline to null out the digital delay of the coarse ADC.

The 6-bit coarse ADC word and 7-bit residue word are addedtogether and corrected in the digital error correction logic togenerate the output word. The result is a 12-bit parallel digitalCMOS-compatible word, coded as twos complement.

APPLYING THE AD6640Encoding the AD6640Best performance is obtained by driving the encode pins dif-ferentially. However, the AD6640 is also designed to interfacewith TTL and CMOS logic families. The source used to drivethe ENCODE pin(s) must be clean and free from jitter. Sourceswith excessive jitter will limit SNR (reference Equation 1 under“Noise Floor and SNR”).

0.01mF

TTL OR CMOSSOURCE

ENCODE

ENCODE

AD6640

Figure 25. Single-Ended TTL/CMOS Encode

The AD6640 encode inputs are connected to a differential inputstage (see Figure 3 under EQUIVALENT CIRCUITS). Withno input signal connected to either ENCODE pin, the voltagedividers bias the inputs to 1.6 volts. For TTL or CMOS usage,the encode source should be connected to ENCODE, Pin 3.ENCODE should be decoupled using a low inductance or mi-crowave chip capacitor to ground.

If a logic threshold other than the nominal 1.6 V is required, thefollowing equations show how to use an external resistor, Rx, toraise or lower the trip point (see Figure 3; R1 = 17 kΩ, R2 = 8 kΩ).

Vl =

5R2RxR1R2 + R1Rx + R2Rx

to lower logic threshold.

0.01mF

ENCODESOURCE ENCODE

ENCODE

AD6640RX

Vl

+5V

R1

R2

Figure 26. Lower Logic Threshold for Encode

Vl =5R2

R2 + R1RX

R1+ RX

to raise logic threshold.

0.01mF

ENCODESOURCE ENCODE

ENCODE

AD6640

RX

Vl

+5V

R1

R2

AVCC

Figure 27. Raise Logic Threshold for Encode

While the single-ended encode will work well for many applica-tions, driving the encode differentially will provide increasedperformance. Depending on circuit layout and system noise, a1 dB to 3 dB improvement in SNR can be realized. It is notrecommended that differential TTL logic be used however,because most TTL families that support complementary outputsare not delay or slew rate matched. Instead, it is recommendedthat the encode signal be ac-coupled into the ENCODE andENCODE pins.

The simplest option is shown below. The low jitter TTL signalis coupled with a limiting resistor, typically 100 ohms, to theprimary side of an RF transformer (these transformers are inex-pensive and readily available; part number in Figure 28 is fromMini-Circuits). The secondary side is connected to the EN-CODE and ENCODE pins of the converter. Since both encodeinputs are self-biased, no additional components are required.

TTL ENCODE

ENCODE

AD6640

100V T1–1T0.1mF

Figure 28. TTL Source – Differential Encode

A clean sine wave may be substituted for a TTL clock. In thiscase, the matching network is shown below. Select a transformerratio to match source and load impedances. The input impedanceof the AD6640 encode is approximately 11 kΩ differentially.Therefore “R,” shown in the Figure 29, may be any value that isconvenient for available drive power.

AD6640

–12– REV. 0

ENCODE

ENCODE

AD6640R

T1–1TSINESOURCE

Figure 29. Sine Source – Differential Encode

If a low jitter ECL clock is available, another option is to ac-couple a differential ECL signal to the encode input pins asshown below. The capacitors shown here should be chip ca-pacitors but do not need to be of the low inductance variety.

ENCODE

ENCODE

AD6640ECLGATE

0.1mF

0.1mF

–VS

510V 510V

Figure 30. Differential ECL for Encode

As a final alternative, the ECL gate may be replaced by an ECLcomparator. The input to the comparator could then be a logicsignal or a sine signal.

ENCODE

ENCODE

AD6640

0.1mF

0.1mF

–VS

50V

AD96687 (1/2)

510V510V

Figure 31. ECL Comparator for Encode

Driving the Analog InputBecause the AD6640 operates from a single +5 volt supply, theanalog input voltage range is offset from ground by 2.4 volt.Each analog input connects through a 450 ohm resistor to the2.4 volt bias voltage and to the input of a differential buffer(Figure 32). This resistor network on the input properly biasesthe followers for maximum linearity and range. Therefore, theanalog source driving the AD6640 should be ac-coupled to theinput pins. Since the differential input impedance of the AD6640is 0.9 kΩ, the analog input power requirement is only –3 dBm,simplifying the drive amplifier in many cases.

AD6640450V

+2.4VREFERENCE

AIN

0.01mF

450V

BUF

BUF

BUF

AIN

VREF

0.1mF

Figure 32. Differential Analog Inputs

To take full advantage of this high input impedance, a 20:1transformer would be required. This is a large ratio and couldresult in unsatisfactory performance. In this case, a lowerstep-up ratio could be used. For example, if RT were set to260 ohms, along with a 4:1 transformer, the input would matchto a 50 ohm source with a full-scale drive of +4 dBm (Figure33). Note that the external load resistor, RT, is in parallel withthe AD6640 analog input resistance of 900 ohms. The externalresistor value can be calculated from the following equation:

RT =1

1Z

–1

900

where Z is the desired impedance (200 Ω for a 4:1 transformerwith 50 Ω input source).

AIN

0.01mF

AIN

VREF

0.1mF

RT

1:4

ANALOGINPUT

SIGNALAD6640

Figure 33. Transformer-Coupled Analog Input Signal

If the lower drive power is attractive, a combination transformermatch and LC match could be employed that would use a 4:1transformer with an LC as shown in Figure 34. This solution isuseful when good performance in the third Nyquist zone isrequired. Such a requirement arises when digitizing high inter-mediate frequencies in communications receivers.

AIN

0.01mF

AIN

VREF

0.1mF

1:4

AD6640–j125V

+j100VANALOGSIGNAL

AT–3dBm

Figure 34. Low Power Drive Circuit

In applications where gain is needed but dc-coupling is notnecessary, an extension of Figure 34 is recommended. A50 ohm gain block may be placed in front of the LC matchingnetwork. Such gain blocks are readily available for commercialapplications. These low cost modules can have excellent NF andintermodulation performance. This circuit is especially good forthe “IF” receiver application previously mentioned.

In applications where dc-coupling is required the followingcircuit can be used (Figure 35). It should be noted that theaddition of circuitry for dc-coupling may compromise performancein terms of noise, offset and dynamic performance. This circuitrequires an inverting and noninverting signal path. Additionally,an offset must be generated so that the analog input to each pinis centered near 2.4 volts. Since the input is differential, smalldifferences in the dc voltage at each input can translate into anoffset for the circuit. The same holds true for gain mismatch.Therefore, some means of adjusting the gain and offset between

AD6640

REV. 0 –13–

the device. A full-scale transition can cause up to 120 mA(12 bits × 10 mA/bit) of current to flow through the digitaloutput stages. The series resistor will minimize the outputcurrents that can flow in the output stage. These switchingcurrents are confined between ground and the DVCC pin. Stan-dard TTL gates should be avoided since they can appreciablyadd to the dynamic switching currents of the AD6640.

Layout InformationThe schematic of the evaluation board (Figure 36) represents atypical implementation of the AD6640. The pinout of theAD6640 facilitates ease of use and the implementation of highfrequency/high resolution design practices. All of the digitaloutputs are on one side while the other sides contain all of theinputs. It is highly recommended that high quality ceramic chipcapacitors be used to decouple each supply pin to ground di-rectly at the device. Depending on the configuration used forthe encode and analog inputs, one or more capacitors are requiredon those input pins. The capacitors used on the ENCODE andVREF pins must be a low inductance chip capacitor as referencedpreviously in the data sheet.

A multilayer board is recommended to achieve best results. Careshould be taken when placing the digital output runs. Becausethe digital outputs have such a high slew rate, the capacitiveloading on the digital outputs should be minimized. Circuittraces for the digital outputs should be kept short and connectdirectly to the receiving gate (broken only by the insertion of theseries resistor). Digital data lines should be kept clear of analogand encode traces.

Evaluation BoardsThe evaluation board for the AD6640 is very straightforward,consisting of power, signal inputs and digital outputs. Theevaluation board includes the option for an onboard clock oscil-lator for the encode.

Power to the analog supply pins is connected via banana jacks.The analog supply powers the crystal oscillator and the AVCC

pins of the AD6640.

The DVCC power is supplied via J3, the digital interface. Thisdigital supply connection also powers the digital gates on thePCB. By maintaining separate analog and digital power supplies,degradation in SNR and SFDR is kept to a minimum. Totalpower requirement is approximately 200 mA. This configurationallows for easy evaluation of different logic families (i.e., con-nection to a 3.3 volt logic board).

The analog input is connected via J2 and is transformer-coupledto the AD6640 (see Driving the Analog Input). The onboardtermination resistor is 270 Ω. This resistor, in parallel with theAD6640’s input resistance (900 Ω), provides a 50 Ω load to theanalog source driving the 1:4 transformer. If a different inputimpedance is required, replace R16 by using the followingequation

R16 =1

1Z

− 1900

where Z is desired input impedance (200 Ω for a 4:1 trans-former with 50 Ω source).

the sides should be implemented. The addition of small valueresistors between the AD9631 and the AD6640 will preventoscillation due to the capacitive input of the ADC.

62VSIGNALSOURCE

AD963115V

467V

0.1mF

OP279(1/2)OP279

(1/2) 750V

1000V

78V

350VAD6640

AIN

VREF

425V

467V

0.1mF 0.01mF

127V

350V

AD9631

15VAIN

350V

Figure 35. DC-Coupled Analog Input Circuit

Power SuppliesCare should be taken when selecting a power source. Linearsupplies are strongly recommended as switching supplies tend tohave radiated components that may be “received” by theAD6640. Each of the power supply pins should be decoupled asclosely to the package as possible using 0.1 µF chip capacitors.

The AD6640 has separate digital and analog +5 V pins. Theanalog supplies are denoted AVCC and the digital supply pinsare denoted DVCC. Although analog and digital supplies may betied together, best performance is achieved when the suppliesare separate. This is because the fast digital output swings cancouple switching noise back into the analog supplies. Note thatAVCC must be held within 5% of 5 volts; however the DVCC

supply may be varied according to output digital logic family(i.e., DVCC should be connected to the same supply as the digi-tal circuitry). The AD6640 is specified for DVCC = 3.3 V as thisis a common supply for digital ASICs.

Output LoadingCare must be taken when designing the data receivers for theAD6640. It is recommended that the digital outputs drive aseries resistor (e.g. 348 ohms) followed by a gate like the74LCX574. To minimize capacitive loading, there should onlybe one gate on each output pin. An example of this is shown inthe evaluation board schematic shown in Figure 36. The digitaloutputs of the AD6640 have a constant rise time output stage.The output slew rate is about 1 V/ns when DVCC = +5 V. Atypical CMOS gate combined with PCB trace and through holewill have a load of approximately 10 pF. Therefore as each bitswitches, 10 mA

10 pF × 1V

1ns

of dynamic current per bit will flow in or out of

AD6640

–14– REV. 0

The analog input range of the PCB is ±0.5 volts (i.e., signal ac-coupled to AD6640).

The encode signal may be generated using an onboard crystaloscillator, U1. The oscillator is socketed and may be replacedby an external encode source via J1. If an external source isused, it should be a high quality TTL source. A transformerconverts the single-ended TTL signal to a differential clock (seeEncoding the AD6640). Since the encode is coupled with atransformer, a sine wave could have been used; note, however,that U5 requires TTL levels to function properly.

Table I. AD6640ST/PCB Bill of Material

Item Quantity Reference Description1 2 +5 VA, GND Banana Jack2 11 C7–C9, C11–C17, C19 Ceramic Chip Capacitor 0805, 0.1 µF3 2 C4, C6 Tantalum Chip Capacitor 10 µF4 1 J3 40-Pin Double Row Male Header5 3 J1, J2, J4 BNC Coaxial PCB Connector6 1 R1 Surface Mount Resistor 1206, 348 Ω7 25 R2–R14, R20–R25, R30–R35 Surface Mount Resistor 1206, 348 Ω8 1 R15 Surface Mount Resistor 1206, 100 Ω9 1 R16 Surface Mount Resistor 1206, 270 Ω10 2 T1, T2 Surface Mount Transformer Mini-Circuits T4–1T, 1:4 Ratio11 1 U1 Clock Oscillator (Optional)12 1 DUT AD6640AST 12-Bit–65 MSPS ADC Converter13 2 U3, U4 74LCX574 Octal Latch14 1 U5 74LVQ00 Quad Two Input NAND Gate15 1 C1, C18 Ceramic Chip Capacitor 0508, 0.01 µF Low Inductance16 2 C2, C3 Ceramic Chip Capacitor 0508, 0.1 µF Low Inductance17 2 CR1, CR2 1N2810 Schottky Diode

AD6640 output data is latched using 74LCX574 (U3, U4)latches following 348 ohm series resistors. The resistors limitthe current that would otherwise flow due to the digital outputslew rate. The resistor value was chosen to represent a timeconstant of ~25% of the data rate at 65 MHz. This reduces slewrate while not appreciably distorting the data waveform. Data islatched in a pipeline configuration; a rising edge generates thenew AD6640 data sample, latches the previous data at the con-verter output, and strobes the external data register over J3.

NOTE: Power and ground must be applied to J3 to power thedigital logic section of the evaluation board.

AD6640

REV. 0 –15–

29

30

31

32

33

27

28

25

26

24

23

3

4

5

6

7

2

10

11

8

9

1

40 39 3841424344 36 35 3437

12 13 14 15 16 17 18 19 20 21 22

2

9

8

7

6

3

4

5

12

13

14

15

16

17

18

19

74LCX574(DVCC)

8D

7D

5D

1D

4D

6D

3D

2D

5Q

6Q

7Q

8Q

2Q

3Q

4Q

1Q

OECK

B06

B07

B08

B09

B10

B11

11 1

2

9

8

7

6

3

4

5

12

13

14

15

16

17

18

19

U474LCX574

(DVCC)

8D

7D

5D

1D

4D

6D

3D

2D

5Q

6Q

7Q

8Q

2Q

3Q

4Q

1Q

OECK

B00

B01

B02

B03

B04

B05

11 1

NC = NO CONNECT

GND

GND

GN

D

DVCC

DVCC

3

2

1

4

6

T4–1T100V

1

23

U574LVQ00

(+5VA)

56

4BUFLAT

ANALOGINPUT

+5V ANALOG SUPPLY

+5VA

GNDCOMMON

0.1mF

1:4

0.01mF

GN

D

GN

D

GN

D

GN

D

DVCC

C610mF

+ C70.1mF

C110.1mF

C120.1mF

C130.1mF

C150.1mF

C160.1mF

+5VAC410mF

+ C80.1mF

C90.1mF

C170.1mF

AV

CC

AV

CC

AV

CC

AV

CC

AV

CC

DUTAD6640

DVCC

ENCODE

ENCODE

AIN

VREF

C1

AVCC

GN

D

GN

D

GN

D

GN

D

D10 D9

DV

CC

DV

CC

DV

CC

DV

CC

GN

D

348V

348V

348V

348V

348V

348V

348V

348V

348V

348V

348V

348V

0.01mF

D8

D7

D6

D5

D4

D3

D2

D1

GND

NC

(LSB) D0

D11

DVCC

+5VA

3

2

1

4

6

T4–1T

1:4

TWO COMPLEMENTBUFFERED OUTPUTS

E1

E2

270V

0.1mF

+5VA348V

J1

J2

ENCODEINPUT

0.1mF

123456789

1011121314151617181920

3130292827262524232221

323334353637383940

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

DVCC (+3.3V OR +5.0V)

B11B10B09B08B07B06B05B04

B03B02B01B00

GNDGNDGNDGNDGND

348V

348V

348V

348V

348V

348V

348V

348V

348V

348V

348V

348V

BUFLAT

348V

AIN

J4

J3

DVCC

Figure 36. AD6640ST/PCB Schematic

AD6640

–16– REV. 0

Figure 37. AD6640ST/PCB Top Side Silkscreen

Figure 38. AD6640ST/PCB Bottom Side Silkscreen

Figure 39. AD6640ST/PCB Top Side Copper

Figure 40. AD6640ST/PCB Bottom Side Copper (Positive)

NOTE: Evaluation boards are often updated, consult factory for latest version.

AD6640

REV. 0 –17–

Figure 41. AD6640ST/PCB Ground Layer (Negative) Figure 42. AD6640ST/PCB “Split” Power Layer (Negative)

AD6640

–18– REV. 0

DIGITAL WIDEBAND RECEIVERSIntroductionSeveral key technologies are now being introduced that mayforever alter the vision of radio. Figure 43 shows the typicaldual conversion superheterodyne receiver. The signal picked upby the antenna is mixed down to an intermediate frequency (IF)using a mixer with a variable local oscillator (LO); the variableLO is used to “tune-in” the desired signal. This first IF ismixed down to a second IF using another mixer stage and afixed LO. Demodulation takes place at the second or third IFusing either analog or digital techniques.

ADCs

VARIABLE

IF1 IF2

FIXED

NARROWBANDFILTER

NARROWBANDFILTER I

Q

LNA

RFe.g. 900MHz

SHARED ONE RECEIVER PER CHANNEL

Figure 43. Narrowband Digital Receiver Architecture

If demodulation takes place in the analog domain then tradi-tional discriminators, envelop detectors, phase locked loops orother synchronous detectors are generally employed to strip themodulation from the selected carrier.

However, as general purpose DSP chips such as the ADSP-2181become more popular, they will be used in many baseband-sampled applications like the one shown in Figure 43. Asshown in the figure, prior to ADC conversion, the signal mustbe mixed down, filtered, and the I and Q components separated.These functions are realizable through DSP techniques, how-ever several key technology breakthroughs are required: highdynamic range ADCs such as the AD6640, new DSPs (highlyprogrammable with onboard memory, fast), digital tuners andfilters such as the AD6620, wide band mixers and amplifiers.

WIDEBANDADC

FIXED

WIDEBANDMIXER

WIDEBANDFILTERLNA

RFe.g. 900MHz

SHARED

"n" CHANNELSTO DSP

12.5MHz(416 CHANNELS)

CHANNEL SELECTION

DIGITAL TUNER/FILTERDSP

DIGITAL TUNER/FILTERDSP

Figure 44. Wideband Digital Receiver Architecture

Figure 44 shows such a wideband system. This design showsthat the front end variable local oscillator has been replaced witha fixed oscillator and the back end has been replaced with awide dynamic range ADC, digital tuner and DSP. This tech-nique offers many benefits.

First, many passive discrete components have been eliminatedthat formed the tuning and filtering functions. These passivecomponents often require “tweaking” and special handlingduring assembly and final system alignment. Digital compo-nents require no such adjustments; tuner and filter characteristicsare always exactly the same. Moreover, the tuning and filteringcharacteristics can be changed through software. Since software

is used for demodulation, different routines may be used todemodulate different standards such as AM, FM, GMSK or anyother desired standard. In addition, as new standards arise ornew software revisions are generated, they may be field installedwith standard software update channels. A radio that performsdemodulation in software as opposed to hardware is oftenreferred to as a soft radio because it may be changed or modifiedsimply through code revision.

System DescriptionIn the wideband digital radio (Figure 44), the first down conver-sion functions in much the same way as a block converter does.An entire band is shifted in frequency to the desired interme-diate frequency. In the case of cellular base station receivers,5 MHz to 30 MHz of bandwidth are down-converted simulta-neously to an IF frequency suitable for digitizing with a wide-band analog-to-digital converter. Once digitized the broadbanddigital data stream contains all of the in-band signals. Theremainder of the radio is constructed digitally using specialpurpose and general purpose programmable DSP to performfiltering, demodulation and signal conditioning not unlike theanalog counter parts.

In the narrowband receiver (Figure 43), the signal to be receivedmust be tuned. This is accomplished by using a variable localoscillator at the first mix down stage. The first IF then uses anarrow band filter to reject out of band signals and conditionthe selected carrier for signal demodulation.

In the digital wideband receiver (Figure 44), the variable localoscillator has been replaced with a fixed oscillator, so tuningmust be accomplished in another manner. Tuning is performeddigitally using a digital down conversion and filter chip fre-quently called a channelizer. The term channelizer is usedbecause the purpose of these chips is to select one channel outof many within the broadband spectrum present in the digitaldata stream of the ADC.

DECIMATIONFILTER

LOW-PASSFILTER

DIGITALTUNER

COS

SINDECIMATION

FILTERLOW-PASS

FILTER

DATA

I

Q

Figure 45. AD6620 Digital Channelizer

Figure 45 shows the block diagram of a typical channelizer, suchas the AD6620. Channelizers consist of a complex NCO (Nu-merically Controlled Oscillator), dual multiplier (mixer), andmatched digital filters. These are the same functions that wouldbe required in an analog receiver, however implemented indigital form. The digital output from the channelizer is thedesired carrier, frequently in I & Q format; all other signals havebeen filtered and removed based on the filtering characteristicsdesired. Since the channelizer output consists of one selectedRF channel, one tuner chip is required for each frequency re-ceived, although only one wideband RF receiver is needed forthe entire band. Data from the channelizer may then be pro-cessed using a digital signal processor such as the ADSP-2181or the SHARC® processor, the ADSP-21062. This data maythen be processed through software to demodulate the informa-tion from the carrier.

SHARC is a registered trademark of Analog Devices, Inc.

AD6640

REV. 0 –19–

System RequirementsFigure 46 shows a typical wideband receiver subsystem basedaround the AD6640. This strip consists of a wideband IF filter,amplifier, ADC, latches, channelizer and interface to a digitalsignal processor. This design shows a typical clocking schemeused in many receiver designs. All timing within the system isreferenced back to a single clock. While this is not necessary, itdoes facilitate PLL design, ease of manufacturing, system test,and calibration. Keeping in mind that the overall performancegoal is to maintain the best possible dynamic range, many con-siderations must be made.

One of the biggest challenges is selecting the amplifier used todrive the AD6640. Since this is a communications application,it is common to directly sample an intermediate frequency (IF)signal. As such, IF gain blocks can be implemented instead ofbaseband op amps. For these gain block amplifiers, the criticalspecifications are third order intercept point and noise figure. Abandpass filter will remove harmonics generated within theamplifier, but intermods should be better than the performanceof the A/D converter. In the case of the AD6640, amplifierintermods must be better than –80 dBFS when driving full-scale power. As mentioned earlier, there are several amplifiersto choose from and the specifications depend on the endapplication. Figure 47 shows a typical multitone test.

FREQUENCY – MHz

0

–80

–120

–40

–100

–20

–60

dc 32.56.5

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB

13.0 19.5 26.0

ENCODE = 65MSPS

Figure 47. Multitone Performance

Two other key considerations for the digital wideband receiverare converter sample rate and IF frequency range. Since per-formance of the AD6640 converter is largely independent ofboth sample rate and analog input frequency (Figures 10, 11and 16), the designer has greater flexibility in the selection ofthese parameters. Also, since the AD6640 is a bipolar device,

power dissipation is not a function of sample rate. Thus there isno penalty paid in power by operating at faster sample rates. Allof this is good because, by carefully selecting input frequencyrange and sample rate, some of the drive amplifier and ADCharmonics can actually be placed out-of-band.

For example, if the system has second and third harmonics thatare unacceptably high, by carefully selecting the encode rate andsignal bandwidth, these second and third harmonics can beplaced out-of-band. For the case of an encode rate equal to60 MSPS and a signal bandwidth of 7.5 MHz, placing the fun-damental at 7.5 MHz places the second and third harmonics outof band as shown in the table below.

Table II.

Encode Rate 60 MSPSFundamental 7.5 MHz–15 MHzSecond Harmonic 15 MHz–30 MHzThird Harmonic 22.5 MHz–30 MHz, 30 MHz–15 MHz

Another option can be found through bandpass sampling. If theanalog input signal range is from dc to FS/2, then the amplifierand filter combination must perform to the specification re-quired. However, if the signal is placed in the third Nyquistzone (FS to 3 FS/2), the amplifier is no longer required to meetthe harmonic performance required by the system specificationssince all harmonics would fall outside the passband filter. Forexample, the passband filter would range from FS to 3 FS/2.The second harmonic would span from 2 FS to 3 FS, well out-side the passband filter’s range. The burden then has been passedoff to the filter design provided that the ADC meets the basicspecifications at the frequency of interest. In many applications,this is a worthwhile tradeoff since many complex filters caneasily be realized using SAW and LCR techniques alike at theserelatively high IF frequencies. Although harmonic performanceof the drive amplifier is relaxed by this technique, intermodula-tion performance cannot be sacrificed since intermods must beassumed to fall in-band for both amplifiers and converters.

Noise Floor and SNROversampling is sampling at a rate that is greater than twice thebandwidth of the signal desired. Oversampling does not haveanything to do with the actual frequency of the sampled sig-nal, it is the bandwidth of the signal that is key. Bandpass or“IF” sampling refers to sampling a frequency that is higher thanNyquist and often provides additional benefits such as downconversion using the ADC and replacing a mixer with a track-and-hold. Oversampling leads to processing gains because the

PRESELECTFILTER LNA

5–15MHzPASSBAND 348V

CMOSBUFFER

D11

D0

+3.3V (D)+5V (A)

AD6640

AIN

ENCODE

ENCODE

M/N PLLSYNTHESIZER

LODRIVE

REFIN

1900MHz

REFERENCECLOCK

65.00MHz

12

AD6620(REF. FIG 45)

I & QDATA

CLK

ADSP-2181

NETWORKCONTROLLERINTERFACE

AIN

Figure 46. Simplified Wideband PCS Receiver

AD6640

–20– REV. 0

faster the signal is digitized, the wider the distribution of noise.Since the integrated noise must remain constant, the actualnoise floor is lowered by 3 dB each time the sample rate isdoubled. The effective noise density for an ADC may be calcu-lated by the equation:

V NOISE rms / Hz = 10−SNR /20

4 FS

For a typical SNR of 68 dB and a sample rate of 65 MSPS, thisis equivalent to 25 nV/√Hz. This equation shows the relation-ship between SNR of the converter and the sample rate FS.This equation may be used for computational purposes to deter-mine overall receiver noise.

The signal-to-noise ratio (SNR) for an ADC can be predicted.When normalized to ADC codes, the following equation accu-rately predicts the SNR based on three terms. These are jitter,average DNL error and thermal noise. Each of these termscontributes to the noise within the converter.

Equation 1:

SNR = –20 log 2 πFANALOG tJ rms( )2+

1+ ε212

2

+VNOISE rms

212

2

1/2

FANALOG = analog input frequency

t J rms = rms jitter of the encode (rms sum of encode sourceand internal encode circuitry)

ε = average DNL of the ADC (typically 0.51 LSB)

VNOISE rms = V rms thermal noise referred to the analog input ofthe ADC (typically 0.707 LSB)

Processing GainProcessing gain is the improvement in signal-to-noise ratio(SNR) gained through oversampling and digital filtering. Mostof this processing gain is accomplished using the channelizerchips. These special purpose DSP chips not only provide chan-nel selection and filtering but also provide a data rate reduction.The required rate reduction is accomplished through a processcalled decimation. The term decimation rate is used to indicatethe ratio of input data rate to output data rate. For example, ifthe input data rate is 65 MSPS and the output data rate is1.25 MSPS, then the decimation rate is 52.

Large processing gains may be achieved in the decimation andfiltering process. The purpose of the channelizer, beyond tun-ing, is to provide the narrowband filtering and selectivity thattraditionally has been provided by the ceramic or crystal filtersof a narrowband receiver. This narrowband filtering is thesource of the processing gain associated with a wideband re-ceiver and is simply the ratio of the passband to whole bandexpressed in dB. For example, if a 30 kHz AMPS signal isbeing digitized with an AD6640 sampling at 65 MSPS, the ratiowould be 0.015 MHz/32.5 MHz. Expressed in log form, theprocessing gain is –10 × log (0.015 MHz/32.5 MHz) or 33.4 dB.

Additional filtering and noise reduction techniques can beachieved through DSP techniques; many applications do useadditional process gains through proprietary noise reductionalgorithms.

Overcoming Static Nonlinearities with DitherTypically, high resolution data converters use multistagetechniques to achieve high bit resolution without large com-parator arrays that would be required if traditional “flash” ADCtechniques were employed. The multistage converter typicallyprovides better wafer yields meaning lower cost and much lowerpower. However, since it is a multistage device, certain portionsof the circuit are used repetitively as the analog input sweepsfrom one end of the converter range to the other. Although theworst DNL error may be less than an LSB, the repetitive natureof the transfer function can play havoc with low level dynamicsignals. Spurious signals for a full-scale input may be –80 dBc.However at 36 dB below full scale, these repetitive DNL errorsmay cause spurious-free dynamic range (SFDR) to fall below80 dBFS as shown in Figure 20.

A common technique for randomizing and reducing the effectsof repetitive static linearity is through the use of dither. Thepurpose of dither is to force the repetitive nature of static linear-ity to appear as if it were random. Then, the average linearityover the range of dither will dominate SFDR performance. Inthe AD6640, the repetitive cycle is every 15.625 mV p-p.

To ensure adequate randomization, 5.3 mV rms is required;this equates to a total dither power of –32.5 dBm. This willrandomize the DNL errors over the complete range of theresidue converter. Although lower levels of dither such as thatfrom previous analog stages will reduce some of the linearityerrors, the full effect will only be gained with this larger dither.Increasing dither even more may be used to reduce some of theglobal INL errors. However, signals much larger than the mVsproposed here begin to reduce the usable dynamic range of theconverter.

Even with the 5.3 mV rms of noise suggested, SNR would belimited to 36 dB if injected as broadband noise. To avoid thisproblem, noise may be injected as an out-of-band signal. Typically,this may be around dc but may just as well be at FS/2 or atsome other frequency not used by the receiver. The bandwidthof the noise is several hundred kilohertz. By band-limiting andcontrolling its location in frequency, large levels of dither maybe introduced into the receiver without seriously disruptingreceiver performance. The result can be a marked improvementin the SFDR of the data converter.

Figure 23 shows the same converter shown earlier but with thisinjection of dither (reference Figure 20).

AD600

A

A

REF

2.2kV

1mF

0.1mF

39V 390V

16kV

+15V

NC202NOISEDIODE

(NoiseCom)+5V

–5V1kV

2kV

OP27

OPTIONAL HIGHPOWER DRIVE

CIRCUIT

LOW CONTROL(0–1 VOLT)

Figure 48. Noise Source (Dither Generator)

AD6640

REV. 0 –21–

The simplest method for generating dither is through the use ofa noise diode (Figure 48). In this circuit, the noise diode NC202generates the reference noise that is gained up and driven by theAD600 and OP27 amplifier chain. The level of noise may becontrolled by either presetting the control voltage when thesystem is set up, or by using a digital-to-analog converter (DAC)to adjust the noise level based on input signal conditions. Oncegenerated, the signal must be introduced to the receiver strip.The easiest method is to inject the signal into the drive chainafter the last down conversion as shown in Figure 49.

NOISE SOURCE

(REF. FIGURE 48)

LPF

AIN

0.01mF

AIN

VREF

0.1mF

AD6640

COMBINER

BPF

FROMRF/IF

IF AMP

Figure 49. Using the AD6640 with Dither

Receiver ExampleTo determine how the ADC performance relates to overall re-ceiver sensitivity, the simple receiver in Figure 50 will be exam-ined. This example assumes that the overall down conversionprocess can be grouped into one set of specifications, instead ofindividually examining all components within the system andsumming them together. Although a more detailed analysisshould be employed in a real design, this model will provide agood approximation.

In examining a wideband digital receiver, several considerationsmust be applied. Although other specifications are important,receiver sensitivity determines the absolute limits of a radioexcluding the effects of other outside influences. Assuming thatreceiver sensitivity is limited by noise and not adjacent signalstrength, several sources of noise can be identified and theiroverall contribution to receiver sensitivity calculated.

RF/IF AD6640 CHANNELIZER

REF IN

DSP

ENC

61.44MHz

GAIN = 30dBNF = 10dB

BW =12.5MHzSINGLE CHANNEL

BW = 30kHz

Figure 50. Receiver Analysis

The first noise calculation to make is based on the signal band-width at the antenna. In a typical broadband cellular receiver,the IF bandwidth is 12.5 MHz. Given that the power of noise ina given bandwidth is defined by Pn = kTB, where B is band-width, k = 1.38 × 10–23 is Boltzman’s constant and T = 300kis absolute temperature, this gives an input noise power of5.18 × 10–14 watts or –102.86 dBm. If our receiver front end hasa gain of 30 dB and a noise figure of 10 dB, then the total noisepresented to the ADC input becomes –62.86 dBm (–102.86 + 30+ 10) or 0.16 mV rms. Comparing receiver noise to dither re-quired for good SFDR, we see that in this example, our receiversupplies about 3% of the dither required for good SFDR.

Based on a typical ADC SNR specification of 68 dB, theequivalent internal converter noise is 0.140 mV rms. There-fore total broadband noise is 0.21 mV rms. Before process-ing gain, this is an equivalent SNR (with respect to full scale)of 64.5 dB. Assuming a 30 kHz AMPS signal and a samplerate of 61.44 MSPS, the SNR through processing gain is in-creased by approximately 33 dB to 97.5 dB. However, if eightstrong and equal signals are present in the ADC bandwidth,then each must be placed 18 dB below full scale to preventADC overdrive. Therefore we give away 18 dB of range andreduce the carrier-to-noise ratio (C/N) to 79.5 dB.

Assuming that the C/N ratio must be 10 dB or better foraccurate demodulation, one of the eight signals may be reduced by66.5 dB before demodulation becomes unreliable. At this point,the input signal power would be –90.5 dBm. Referenced to theantenna, this is –120.5 dBm.

To improve sensitivity, several things can be done. First, thenoise figure of the receiver can be reduced. Since front endnoise dominates the 0.16 mV rms, each dB reduction in noisefigure translates to an additional dB of sensitivity. Second, pro-viding broadband AGC can improve sensitivity by the range ofthe AGC. However, the AGC would only provide useful im-provements if all in-band signals are kept to an absolute minimalpower level so that AGC can be kept near the maximum gain.

This noise limited example does not adequately demonstrate thetrue limitations in a wideband receiver. Other limitations suchas SFDR are more restrictive than SNR and noise. Assume thatthe analog-to-digital converter has an SFDR specification of–80 dBFS or –76 dBm (Full scale = +4 dBm). Also assumethat a tolerable carrier-to-interferer (C/I) (different from C/N)ratio is 18 dB. This means that the minimum signal level is–62 dBFS (–80 plus 18) or –58 dBm. At the antenna, this is–88 dBm. Therefore, as can be seen, SFDR (single or multi-tone) would limit receiver performance in this example. How-ever, as shown previously, SFDR can be greatly improvedthrough the use of dither (Figures 19, 22). In many cases, theaddition of the out-of-band dither can improve receiver sensitiv-ity nearly to that limited by thermal noise.

AD6640

–22– REV. 0

IF Sampling, Using the AD6640 as a Mix-Down StageSince performance of the AD6640 extends beyond the basebandregion into the third Nyquist zone, the converter has many usesas a mix-down converter in both narrowband and widebandapplications. This application is called bandpass sampling. Do-ing this has several positive implications in terms of the selectionof the IF drive amplifier. Not only is filtering a bit easier, theselection of drive amplifiers is extended to classical IF gainblocks. In the third Nyquist zone and above, the second andthird harmonics are easily filtered with a bandpass filter. Nowonly in-band spurs that result from third order products areimportant.

In narrowband applications, harmonics of the ADC can beplaced out-of-band. One example is the digitization of a201 MHz IF signal using a 17.333 MHz clock. As shown inFigure 51, the spurious performance has diminished due tointernal slew rate limitations of the ADC. However, the SNR ofthe converter is still quite good. Subsequent digital filtering witha channelizer chip such as the AD6620 will yield even better SNR.

For multicarrier applications, third order intercept of the driveamplifier is important. If the input network is matched to theinternal 900 ohm input impedance, the required full-scale drivelevel is –3 dBm. If spurious products delivered to the ADC arerequired to be below –90 dBFS, the typical performance of theADC with dither applied, then the required third order interceptpoint for the drive amplifier can be calculated.

For multicarrier applications, the AD6640 is useful up to about80 MHz analog in. For single channel applications, the AD6640is useful to 200 MHz as shown from the bandwidth charts. Ineither case, many common IF frequencies exist in this range offrequencies. If the ADC is used to sample these signals, they willbe aliased down to baseband during the sampling process inmuch the same manner that a mixer will down-convert a signal.For signals in various Nyquist zones, the following equationsmay be used to determine the final frequency after aliasing.

f1NYQUISTS = fSAMPLE − fSIGNAL

f 2NYQUISTS = abs ( fSAMPLE − fSIGNAL )

f 3NYQUISTS = 2 × fSAMPLE − fSIGNAL

f 4NYQUISTS = abs (2 × fSAMPLE − fSIGNAL )

Using the converter to alias down these narrowband or widebandsignals has many potential benefits. First and foremost is theelimination of a complete mixer stage along with amplifiers,filters and other devices, reducing cost and power dissipation. Insome cases, the elimination of two IF stages is possible.

Figures 21 and 24 in Typical Performance Characteristics illus-trate a multicarrier, IF Sampling System. By using dither, allspurious components are forced below 90 dBFS (Figure 24).The dashed line illustrates how a 5 MHz bandpass filter couldbe centered at 67.5 MHz. As discussed earlier, this approachgreatly reduces the size and complexity of the receiver’s RF/IFsection.

FREQUENCY – MHz

0

60

198 207

PO

WE

R R

ELA

TIV

E T

O A

DC

FU

LL S

CA

LE –

dB

199.8 201.6 203.4 205.2

40

80

20

100

ALIASED2ND HARMONIC

ALIASED3RD HARMONIC


ALIASEDSIGNALS

Figure 51. IF-Sampling a 201 MHz Input

RECEIVE CHAIN FOR A PHASED ARRAY CELLULARBASE STATIONThe AD6640 is an excellent digitizer for beam forming inphased array antenna systems. The price performance of theAD6640 followed by AD6620 channelizers allows for a verycompetitive solution. Phase array base stations allow bettercoverage by focusing the receivers’ sensitivity in the directionneeded. Phased array systems allow for the electronic beam toform on the receive antennas.

A typical phased array system may have eight antennas as shownin Figure 52. Since a typical base station will handle 32 calls,each antenna would have to be connected to 32 receivers. Ifdone with analog or traditional radios, the system grows quiterapidly. With a multicarrier receiver, however, the design isquite compact. Each antenna will have a wideband down-converter with one AD6640 per receiver. The output of eachAD6640 would drive 32 AD6620 channelizers, which are phaselocked in groups of eight—one per antenna. This allows eachgroup of eight AD6620’s to tune and lock onto a different user.When the incoming signal direction is determined, the relativephase of each AD6620 in the group can be adjusted such theoutput signals sum together in a constructive manner, givinghigh gain and directivity in the direction of the caller. This ap-plication would not be possible with traditional receiver designs.

AD6640

REV. 0 –23–

Figure 52. Receive Chain for a Phased Array Cellular Base Station with Eight Antennas and 32 Channels

AD6640

COMMON LO

ANTENNA 1

EIGHT WIDEBAND FRONT ENDS AD6620 (1)

SYNC 1

ANTENNA 2

AD6620s (32 CHANNELS)AD6640

AD6640

ANTENNA 3

ANTENNA 4


AD6640

ANTENNA 5

ANTENNA 6


ANTENNA 8


SUMADSP-21xx

(32)

SUMADSP-21xx

(31)

SUMADSP-21xx

(30)

SUMADSP-21xx

(3)

SUMADSP-21xx

(2)

SUMADSP-21xx

(1)

32 CHANNELS OUTEACH CHANNEL IS SUMMATIONFROM EIGHT ANTENNA'S

COMBINE SIGNALSFROM EIGHT ANTENNA'S

AD6620 (2)

AD6620 (3)

AD6620 (30)

AD6620 (31)

AD6620 (32)

AD6620 (1)

SYNC 1

AD6620 (2)

AD6620 (3)

AD6620 (30)

AD6620 (31)

AD6620 (32)

AD6620 (1)

SYNC 1

AD6620 (2)

AD6620 (3)

AD6620 (30)

AD6620 (31)

AD6620 (32)

AD6640

ANTENNA 7

AD6620 (1)

SYNC 1

AD6620 (2)

AD6620 (3)

AD6620 (30)

AD6620 (31)

AD6620 (32)

AD6640

–24– REV. 0

C31

41–8

–1/9

8P

RIN

TE

D IN

U.S

.A.

AD6640AST OUTLINE DIMENSIONSDimensions shown in inches and (mm)

44-Terminal Plastic Thin Quad Flatpack(ST-44)

TOP VIEW(PINS DOWN)

1

33

34

44

11

12

23

22

0.018 (0.45)0.012 (0.30)

0.031 (0.80)BSC

0.394(10.0)

SQ

0.472 (12.00) SQ

0.057 (1.45)0.053 (1.35)

0.006 (0.15)0.002 (0.05)

SEATINGPLANE

0.063 (1.60)MAX

0.030 (0.75)0.018 (0.45)

Appendix CAnalog Devices Application Note

REV. 0

a AN-501APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com

Aperture Uncertainty

One of the key concerns when performing IF sampling isthat of aperture jitter or aperture uncertainty. The termsaperture jitter and aperture uncertainty are frequentlyinterchanged in text. In this application, they have thesame meaning. Aperture uncertainty is the sample-to-sample variation in the encode process. Aperture uncer-tainty has three residual effects: the first is an increase insystem noise, the second is an uncertainty in the actualphase of the sampled signal itself and third isintersymbol interference. To achieve required noise per-formance, aperture uncertainty of less than 1 ps isrequired when IF sampling. In terms of phase accuracyand intersymbol interference, the effects of apertureuncertainty are small. In a worst case scenario of 1 psrms at an IF of 250 MHz, the phase uncertainty of error is0.09 degrees rms. This is quite acceptable even for ademanding specification such as GSM. The focus of thisanalysis will therefore be on overall noise contributiondue to aperture uncertainty.

dV

ENCODE

dt

Figure 1. RMS Jitter vs. RMS Noise

In a sine wave, the maximum slew rate is at the zerocrossing. At this point, the slew rate is defined by thefirst derivative of the sine function evaluated at t = 0.

v (t ) = A sin(2 π ft )ddt v (t ) = A 2 πf cos(2 π ft ) (1)

evaluated at t = 0, the cosine function evaluates to 1 andthe equation simplifies to:

ddt v (t ) = A 2 πf = tJITTER (2)

The units of slew rate are volts per second and yieldshow fast the signal is slewing through the zero crossingof the input signal. In a sampling system, a referenceclock is used to sample the input signal. If the sampleclock has aperture uncertainty, an error voltage is gener-ated. This error voltage can be determined by multiply-ing the input slew rate by the jitter.

VERROR = Slew Rate × tJITTER (3)

By analyzing the units, it can be seen that this yields unitof volts. Usually, aperture uncertainty is expressed inseconds rms and, therefore, the error voltage would bein volts rms. Additional analysis of Equation 3 showsthat as analog input frequency increases, the rms errorvoltage also increases in direct proportion to the aper-ture uncertainty.

Contribution to Overall System Performance

In IF sampling converters, clock purity is of extremeimportance. As with the mixing process, the input signalis multiplied by a local oscillator or in this case, a sam-pling clock. Since multiplication in time is convolution inthe frequency domain, the spectrum of the sample clockis convolved with the spectrum of the input signal. Sinceaperture uncertainty is wideband noise on the clock, itshows up as wideband noise in the sampled spectrumas well. And since an ADC is a sampling system, thespectrum is periodic and repeated around the samplerate. This wideband noise therefore degrades the noise

Aperture Uncertainty and ADC System Performance

by Brad Brannon

–2–

AN-501

REV. 0

floor performance of the ADC. The theoretical SNR foran ADC, as limited by aperture uncertainty, is deter-mined by the following equation.

SNR ( f t rms)analog JITTER= − [ ]20 log 2 π (4)

If Equation 4 is evaluated for an analog input of 201 MHzand 0.7 ps rms “jitter,” the theoretical SNR is limitedto 61 dB. Therefore, systems that require very highdynamic range and very high analog input frequenciesalso require a very low jitter encode source. When usingstandard TTL/CMOS clock oscillators modules, 0.7 ps rmshas been verified for both the ADC and oscillator. Betternumbers can be achieved with low noise modules.

When considering overall system performance, a moregeneralized equation may be used. This equation buildson the previous equation but includes the effects ofthermal noise and differential nonlinearity.

SNR 20 log (2 f t rms)1 e2

V rms2

analog JITTER2

N

2noise

N

2 1/2

= − + +

+

π (5)

fanalog = analog IF FrequencytJITTER rms = aperture uncertaintyε = average DNL of converter (~ 0.4 LSB)Vnoise rms = thermal noise in LSBsN = number of bits

Although this is a simple equation, it provides muchinsight into the noise performance that can be expectedfrom a data converter.

Measurement of Sub-Picosecond Aperture Uncertainty

Aperture uncertainty is easily measured by looking atdegraded SNR performance as a function of analoginput frequency. Since SNR degrades as analog inputfrequency increases due to jitter, two FFTs are requiredfor the calculation. The first FFT should be done at a suf-ficiently low analog frequency where the effects of aper-ture uncertainty are negligible. Record the SNRexcluding all harmonics and higher order spurs. Thensolve Equation 5, above, for general converter perfor-mance by assuming that thermal noise is rolled up intothe quantization noise and jitter is neglected. This givesthe equation below.

ε = 2N ×10–SNR

20 –1 (6)

SNR is the low frequency SNRN is the number of converter bitsε = average DNL (+ thermal noise)

Then an FFT is done at very high frequency. The high fre-quency should be chosen to be near the 3 dB bandwidthof the converter. Again, the SNR without harmonicsshould be measured.

At this high frequency, we can assume that jitter is acontributor to noise. From the previous data measure-ment we know the average quantization and thermalnoise; we can solve the general form equation for jitteras shown.

t rms

fJITTER

SNR

N

IF=

+

1012

2

20

2 2–

–ε

π (7)

SNR is the high frequency SNRN is the number of converter bitsε = average DNL from above and thermal noisefIF is the IF analog input frequency

Putting the Calculations to the Test

The following data was collected using the AD9042ST/PCB evaluation board. No modifications were made.The clock oscillator (M1280, manufactured by MF Elec-tronics) supplied with the evaluation board was used togenerate the encode signal which was delivered to theAD9042 differentially via a transformer (Mini-CircuitsT1-1). The analog input was generated by a Rohde &Schwarz synthesizer. For more information about theevaluation board, please see the AD9042 data sheet.

–110.00

–100.00

–90.00

–80.00

–70.00

–60.00

–50.00

–40.00

–30.00

–20.00

–10.00

0.00

Figure 2. 2.3 MHz FFT

Figure 2 is a 16K FFT of the AD9042 sampling a 2.3 MHzsine wave at 40.96 MSPS. Since we must exclude higherorder harmonics from the SNR calculation, × representsthe unintegrated noise floor, or the mean noise floor.Instead of integrating all of the noise spikes, this num-ber is summed across the entire spectrum, thus elimi-nating the higher (and lower) order harmonics. UsingEquation 8:

SNR = –(–108 + 10 log (8192)) (8)

SNR is found to be 69 dB. When this is used tosolve Equation 6 for ε the average DNL (and thermalnoise) for this converter is 0.4533 LSBs.

–3–

AN-501

REV. 0

–110.00

–100.00

–90.00

–80.00

–70.00

–60.00

–50.00

–40.00

–30.00

–20.00

–10.00

0.00

2

3

4

Figure 3. 201 MHz FFT

Next, the degradation in SNR must be found as a func-tion of analog input frequency. Figure 3 is the sameAD9042 and clock, but running an analog input fre-quency of 201 MHz. This time the unintegrated noisefloor has risen by almost 10 dB. Integrating with thisvalue of x yields an SNR of 60 dB. Using this SNR andthe previous solution for ε, the jitter can be found as fol-lows using Equation 7:

t rms

10 –1 0 4533

2

2 201 100.74 ps rmsJITTER

–6020

2

12

2

6=

+

×=

.

π (9)

Therefore, the combined aperture uncertainty for theAD9042 plus the clock oscillator is found to be less thanthree quarters of a picosecond rms. At this time, it is notpossible to determine which part is from the ADC andwhich from the clock oscillator; however, these simplemeasurements indicate that it is possible to measurevery small aperture uncertainty numbers using readilyavailable hardware and simple numeric calculations.

ROHDE &SCHWARZ

BANDPASSFILTER

AD9042EVALUATION

BOARDAD9042ST/PCB

HIGH SPEEDCACHE

MEMORY

FFTPROCESSOR

Figure 4. Aperture Uncertainty Measurement Setup

Many applications require that a master clock be distrib-uted to many different sources. Many systems havemultiple ADCs such as cellular basestations or ultra-sound equipment. The question quickly arises, however,how much jitter is introduced into a system when placedin a distribution system. The first option in distributingan ADC clock is to use logic gates to fan out the encodesignal, but this rapidly increases the amount of jitterintroduced into the system.

By using the technique described above, the jitter pergate (74xx00) for several logic families was measuredand summarized below.

Table I.

Jitter Equivalent NF

74LS00 4.94 2874ACT00 0.99 1574HCT00 2.20 21.84

Table I shows that the 74ACT00 gate delivers the low-est jitter of almost 1 ps rms. In many applications,even this is unacceptable. For receiver applications,the equivalent noise figure is shown for reference(valid at 201 MHz analog input only). Thus when usinglogic gates for ADC clock distribute, they must beused minimally or not at all.

Recent ADC developments require differential clockdrive. With this comes the ability to drive the encodewith a sinusoidal signal instead of a square wave.

ENCODE

ENCODE

AD9042R

T1-1TSINESOURCE

Figure 5. Transformer Differential Encode

As shown above, a sine source can be distributed toencode the ADC. Sine sources can easily be distributedusing power dividers and transformers to match imped-ances. Since ADC encode pins are high impedance, verylittle power is required to encode the devices and thus,when driving multiple devices, low encode drive poweris required. Since the sine source is spectrally pure,fewer problems can be expected in receiver applicationswith harmonics of the ADC encode clock.

The chart following, Figure 6, is a useful guide forquickly determining jitter requirements based on analoginput frequency and converter bits. This chart is fromAnalog Devices' publication, High Speed Design Seminar(ISBN 0-916550-07-9).

0

10

20

30

40

50

60

70

80

90

100

110

4

8

10

6

14

12

1 2 3 5 7 10 20 30 50 70 100FREQUENCY OF FULL SCALE SINE WAVE INPUT – MHz

SN

R –

dB

EN

OB

ta = 0.5ps SNR = 20 log101

2fta

ta = 1ps

ta = 2ps

ta = 10ps

ta = 50ps

ta = 250ps

ta = 1250ps

Figure 6. Signal-to-Noise Ratio Due to Aperture Jitter

PR

INT

ED

IN U

.S.A

.E

0139

9–1–

9/00

(re

v. 0

)

Date post:	24-Aug-2020
Category:	Documents
Upload:	others
View:	1 times
Download:	0 times

NAVSEA AD6640 Total Dose Test Report - NASA · Test Report Final Report Prepared for: NASA GSFC/J&T...

Documents