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© System-on-Chip Group, CSE-IMM, DTU 2
Introduction – intra chip communication
P
Keypad
Network
DSP
Memory
RF
© System-on-Chip Group, CSE-IMM, DTU 3
Introduction – intra chip communication
P
Keypad DSP
Memory
RF
BUS
© System-on-Chip Group, CSE-IMM, DTU 4
Introduction – intra chip communication
P
Keypad DSP
Memory
RF
Point-to-Point
© System-on-Chip Group, CSE-IMM, DTU 5
Overview
• Important Paradigms• Network Abstraction• Performance Evaluation• Research Opportunities
© System-on-Chip Group, CSE-IMM, DTU 6
Important Paradigms for NoC
• Re-use• Flexibility• GALS• Low Power
Core
Network AdapterRouting Node
Link
© System-on-Chip Group, CSE-IMM, DTU 7
On-Chip vs Off-Chip
• On-Chip Cheap Wires Power Limited Area Limited Unreliable Wire
Models
• Off-Chip Wire/pin Limited High Latency Higher Node
Complexity Viable
© System-on-Chip Group, CSE-IMM, DTU 8
µP Mem.
Typical P2P Write Session (3 comm. events)
DATA
ACK
µP NI
“Networked” Write Session(4 comm. event)
DATA
N-ACK
Mem.NI
DATA
DATA
WRT
Network Usage Example
© System-on-Chip Group, CSE-IMM, DTU 9
Network Abstraction - OSI
Application/Presentation Layers
Session/Transport Layer
Network, Link and Physical Layers
Socket Socket
Sink CoreSource Core
NetworkInterface
CoreInterface
© System-on-Chip Group, CSE-IMM, DTU 10
Network Dataflow View
Socket Socket
Sink CoreSource Core
Packets
Flit
Phif
Messages
© System-on-Chip Group, CSE-IMM, DTU 11
Memory
Application Layer Traffic Characterization
µP, Dedicated Hardware
Communication Msg. Sizesmall large
Fre
q. o
f C
omm
. Eve
nts
high
lowI/O (sensors,
wired/wireless)
DSP, Application Specific Blocks
© System-on-Chip Group, CSE-IMM, DTU 12
Application Based Communication Network Design
The consistent theme in the literature is to design on-chip network for the application the chip is utilized for, but there is a growing integration of various application cores within a single chip. Hence the need for the network to be flexible and robust so that it can support diverse types and volume of traffic generated by different cores.
An example is the Nokia’s future mobile set that can provide real-time application needs as well as “low latency” data needs.
© System-on-Chip Group, CSE-IMM, DTU 13
QoSlow high
Ban
dwid
th
Uti
liza
tion
Traffic Distribution
low
high
‘Normal’ (bulk) traffic
Critical
events
Control, interrupts, requests, et al?
Streaming
© System-on-Chip Group, CSE-IMM, DTU 14
Network Abstraction
•Session / Transport Layer Plug and play interface Traffic encapsulation
•Network / Link Layer Topology Protocol
© System-on-Chip Group, CSE-IMM, DTU 15
Network Abstraction
• Physical Layer Sub-micron technologies pose challenges Circuit design
Low-swing drivers Differential signaling Asynchronous
Link implementations such as virtual circuits
© System-on-Chip Group, CSE-IMM, DTU 16
Networks-on-Chip
Many combinations! How to judge trade-offs?!
© System-on-Chip Group, CSE-IMM, DTU 17
Boil Down of OSI
Presentation
Application
Transport
Network
Session
Data
Physical
OSI NoC Job Description
Application Message Source/Sink
Interface
• Network Configuration• Error Correction• Packet Creation, Message Reconstruction• Addressing
Network• Flow Control• Prioritization (Bandwidth Reservation)
Link Point-to-point Channels (wires)
© System-on-Chip Group, CSE-IMM, DTU 18
Performance Evaluation
• Quantitative terms Latency Bandwidth Power Area
• Qualitative terms QoS Load balancing Reconfigurability Fault tolerance … more features?
© System-on-Chip Group, CSE-IMM, DTU 19
Tools and Testing
NoC is a subset of SoC Tools
Design Simulation
Testing Pre-fabrication Post-fabrication
© System-on-Chip Group, CSE-IMM, DTU 20
Issues
• At Application Layer• Minimizing the end-to-end latency• Making network communication “transparent”• Support for different traffic types
• At Interface Layer• Message-to-packet overhead (and vice versa)
• Breaking up and re-sequencing?• Error Correction cost?• Addressing techniques?
• End-to-end flow control• Message buffer sizing?• Circuit-switching-like properties?• QoS (Network setup cost, BW reservation)?
© System-on-Chip Group, CSE-IMM, DTU 21
Issues, cont…
• At Network Layer• Need specialized technique for “fast and dedicated routing”
• Combination of deterministic and non-deterministic routing?• Topology• Link-to-link Flow Control
• Packet buffer sizing?• Virtual channels (deadlock avoidance)?• Back pressure (Congestion look-ahead)?
• Routing Mechanism • Address resolution• Bandwidth reservation
• At Link Layer• Fast flexible links
• Virtual channels?• Split channels for multi-flit-per-cycle communication?• Dedicated Address / Control lines?
© System-on-Chip Group, CSE-IMM, DTU 22
Overhead Considerations
• Routing Protocol• Congestion control• Error-correction• Network setup/tear-down• Synchronization
© System-on-Chip Group, CSE-IMM, DTU 23
Research Opportunities
• Traffic + Application• Topology + Protocol• Reconfigurability• Area + Power Issues• Interfaces (GALS)• Sub-micron Technology
Exploitation
© System-on-Chip Group, CSE-IMM, DTU 24
References
• BJERREGAARD, T. and MAHADEVAN, S. 2004. “NoC Survey Manuscript”, Submitted.• HO, R.,MAI, K. W., AND HOROWITZ,M. A. 2001. The future of wires. Proceedings of
the IEEE.• ITRS. 2001. International technology roadmap for semiconductors (ITRS) 2001. Tech.
rep., International Technology Roadmap for Semiconductors.• JANTSCH, A. AND TENHUNEN, H. 2003. Networks on Chip. Kluwer Academic
Publishers.• LEE, K. 1998. On-chip interconnects - gigahertz and beyond. Solid State Technology.• OCPIP. The importance of sockets in soc design. White paper downloadable from
http://www.ocpip.org.• BENINI, L. AND MICHELI, G. D. 2002. Networks on chips: A new soc paradigm. IEEE
Computer.• DALLY, W. J. AND TOWLES, B. 2001. Route packets, not wires: On-chip
interconnection networks. In Proceedings of the 38th Design Automation Conference. • DIELISSEN, J., RADULESCU, A., GOOSSENS, K., AND RIJPKEMA, E. 2003. Concepts and
implementation of the phillips network-on-chip. In Proceedings of the IP based SOC IPSOC’03.
• GOOSSENS,K.,MEERBERGEN, J. V., PEETERS, A., AND WIELAGE, P. 2002. Networks on silicon: Combining best-effort and guaranteed services. In Proceedings of the 2002 Design, Automation and Test in Europe Conference (DATE’02). IEEE.