×
+ All Categories
Log in
English
Français
Español
Deutsch
The top documents tagged [chip network]
Home >
chip network
Sony Chassis Eg1h
599 views
Power-Aware and BIST-Aware NoC Reuse on the Testing of Core-based Systems Érika Cota Luigi Carro Flávio WagnerMarcelo Lubaszewski UFRGS Porto Alegre, Brazil.
220 views
Intel Redefines GPU: Larrabee Tianhao Tong Liang Wang Runjie Zhang Yuchen Zhou.
222 views
Conference on Adaptive Hardware and Systems (AHS'14) - FlexTiles FPGA Emulation
94 views
Embedded system
37 views
STRUCTURED CODESIGN FOR MANYCORE SYSTEMS Jürg Gutknecht & Lisa (Ling) Liu, ETH Zürich Sofsem Novy Smokovec, January 2011.
216 views
The Migration of Safety-Critical RT Software to Multicore Marco Caccamo University of Illinois at Urbana-Champaign.
214 views
An Analytical Model for Worst-case Reorder Buffer Size of Multi-path Minimal Routing NoCs Gaoming Du 1, Miao Li 1, Zhonghai Lu 2, Minglun Gao 1, Chunhua.
218 views
Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs Hiroki Matsutani Michihiro Koibuchi Daisuke Ikebuchi Kimiyoshi Usami Hiroshi Nakamura.
214 views
Hyunbean Yi, Sungju Park, and Sandip Kundu, Fellow, IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I : REGULAR PAPERS, VOL. 57, NO. 7, JULY 2010 Reporter:
215 views
Network-on-Chip An Overview System-on-Chip Group, CSE-IMM, DTU.
220 views
June 20 th 2004University of Utah1 Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors Karthik Ramani Naveen Muralimanohar.
215 views
Next >