New Challenge: High Speed Serdes IP Sign-off 04 MIPI...Skipper Liang Principle Application Engineer,...

Skipper Liang

Principle Application Engineer, ASI/SPB Taiwan

April, 2015

New Challenge: High Speed Serdes IP Sign-off

( MIPI M-PHY validation )

2 © 2013 Cadence Design Systems, Inc. All rights reserved.

Massive Bit TransmissionBER – Bit Error RateChannel ResponseEqualizerBathtub Curve

Agenda

Challenge Today

Conclusions

Peak Distortion (Worst Bit Pattern)Pulse ResponseWorst 0Worst 1

Jitter and Noise



Agenda

Challenge Today

Conclusions


Jitter and Noise


• BER (Bit Error Rate):

1. Long simulation time

In MIPI M-PHY Spec., it defines BER=10−10 as the target for design. It means you should transmit 1010 bits in your simulation during sign-off stage. It will take a lot’s of you time.

2. Peak Distortion (Worst bit pattern)

Even after 1010 bits are transmitted, can you make sure you have seen the worst case?

• Jitter Tolerance

In MIPI M-PHY Spec., it defines your design should tolerated a sinusoidal jitter as the following mask. How to implement in your MIPI IP sign-off?

Challenge Today



Agenda

Challenge Today

Conclusions


Jitter and Noise


BER-Bit Error Rate Bit Error Rate (BER) refers to the rate between error bits and total

transferred bits. For example, to achieve BER less than 10−10, you will try hard to make sure your system will meet one error bit (eye mask violation) after more than 1010 bits transferred.

Using “Circuit Simulator”:

128bits 1hr 47min

10,000,000bits ???


Channel Response

Tx Rx

Serial LinkData out

FFE DFE/CDR

Package

Interconnect

System

InterconnectPackage

Interconnectδ(t) h(t)

Channel’s Impulse Response


Channel Response

Package

Interconnect

System

InterconnectPackage

Interconnectx(t) y(t)

dtttt )()()(*)()( xhxhy

)()(),()( fHthfXtxFFTFFT

)()()( fHfXfY

h(t)

To derive y(t):

Method 1: (circuit simulator – SPECTRRE)

Method 2: (channel simulator – SystemSI Serial Link Analysis)

)()( tyfYIFFT

For a LTI system:


Equalizer

Data out

FFE DFE/CDR

Package

Interconnect

System

InterconnectPackage

Interconnect

h(t)

eq1(t) eq2(t)

x(t) y(t)

)(2)()(1)()( fEQfHfEQfXfY

An Ideal equalizer will compensate the distortion effect of the channel in

the following way:

)()(2)(1 1 fHfEQfEQ

Then:

)(2)()(1)()( fEQfHfEQfXfY

)()()()( 1 fXfHfHfX

And

1)()( 1 fHfH)()()( 1 tthth

Impulse


Equalizer

Equalizer Output

Non-

Linear Linear

)4()3()2(

)()()()(

432

101

ttxttxttx

ttxtxttxthEqualizer

Formulus:

Circuit Netlist

*.dllThe Mechanism how

the equalizer operates

*.amiSetting Taps, coefficients, limit of

coefficient, or come out the optimized

coefficient.

Digital DataEqualized

Data

IBIS

Output

Buffer

By Cadence AMI

Service or

designer himself

By Cadence

SPICE/Behavio

r translator T2B


Bathtub Curve

Vertical

Bathtub Curve

Noise Bathtub

Curve



Agenda

Challenge Today

Conclusions


Jitter and Noise


Pulse Response

-0.5UI 0.5UI

Package

Interconnect

System

InterconnectPackage

Interconnect

x(t) y(t)

h(t)

)()(),()( fHthfXtxFFTFFT

)()()( fHfXfY

Channel simulator – SystemSI Serial Link Analysis

)()( tyfYIFFT


Worst 0

0 1 1 0 1 0 0 1 0 0 0 0 0

0 1 1 0 1 0 0 1 0 0 0 0 0


Worst 1

0 1 0 1 1 0 0 0 0 0

0 1 0 1 1 0 0 0 0 0


Random/Worst Bit Pattern

47 bits length

For a 47 bits length, there can be 247 = 140,737,488,355,328 combinations.



For a 1010 bits length, there are 1010

47= 212,765,957 segments with 47 bits

length, and since

212,765,957 < 140,737,488,355,328

It is possible that 1010 random bits fail to include the

worst bit pattern which is 47 bit length !!



Red 1010 random bits include worst bit pattern

Blue 1010 random bits exclude worst bit pattern



Agenda

Challenge Today

Conclusions


Jitter and Noise


Jitter and Noise

Non-impaired bit

edge• Jitter source will bring out

jitter and noise

• Noise source will bring out jitter and noise

• The overall jitter and noise is a combination of random horizontal and vertical non-ideal shift.


Jitter and Noise

In measurement

Difficult to

implement in

simulation during

the sign-off phase



Agenda

Challenge Today

Conclusions


Jitter and Noise


Conclusion Cadence SystemSI provide a job-oriented method for MIPI M-PHY sign-off, nomatter in a pre-layout or post-layout analysis:

Could be a W-element

or a S-parameter of a

layout


Conclusion

All check items defined in MIPI

Spec. is ready for user to choose

for compliance test.


ConclusionSimulation Result


ConclusionCompliance Report


Conclusions

Cadence SystemSI SLA (Serial Link Analysis) provide a much

faster method for massive bits transmission than traditional

circuit simulation.

With the function of worst bit pattern generation, SystemSI

will help user to predict the worst performance of a system

and to improve the robustness of their design.

A customized flow and compliance check especially for MIPI

in SystemSI helps user to speed their IP sign-off job.

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New Challenge: High Speed Serdes IP Sign-off 04 MIPI...Skipper Liang Principle Application Engineer,...

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