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Noise Canceling in 1-D Data: Presentation #10
Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar
M2
Mar 28rd, 2005Chip Level Layout 2
Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware
Project Manager: Bobby Colyer
Status
• Design proposal (Done)
• Architecture proposal (Done)
• Size Estimates and Floorplan (Done)
• Gate Level Design
- Schematics (Done)
• To be done:– Layout (93%)– Spice simulation (85%)
Design Decisions
• Redesigned the bottom fpAdder to better fit the new floorplan.
• Changed the wiring of the inputs and outputs of the toplevel registers and muxes.
Previous Floorplan
New and Improved Floorplan
Layer Masks - Poly
Layer Masks - Metal 1
Layer Masks – Metal 2
Layer Masks – Metal 3
Layer Masks – Metal 4
The Chip
• Dimension– Width = 377.19µ– Height = 303.3450µ
• Area = 114418.701µ²
• Transistor count = 25859 • Density = 0.226 trans/µ²• Aspect ratio = 1: 1.24
Floating Point Multiplier
10-bit Wallace Tree Multiplier
20 bit output
2 10-bit inputs
Side components of the Multipliers
Center Side
Inputs
Output
fpMult: Simulation Results (Extracted RC)
Bits 8-15
Simulation Results (Schematics with Load Caps)
Bits 8-15
Floating Point Adder
fpAdder Components
AlignShift: Simulation Results (ExtractedRC)
Registers• 2 types of registers
16 bit Register: Simulation Results (ExtractedRC)
16 bit Register: Simulation Results (Schematic)
16-bit 2-1 Mux
Simulation Results (ExtractedRC)
Simulation Results (Schematics with Load)
ROM
Simulation Results (Schematics with Load)
ROM Analysis
• Rise Time = 672.21 ps
• Fall Time = 620.4 ps
Questions?