Noise Canceling in 1-D Data: Presentation #12

Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar

M2

April 11th, 2005Final LVS and Simulation

Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

Project Manager: Bobby Colyer

Status

• Design proposal (Done)

• Architecture proposal (Done)

• Size Estimates and Floorplan (Done)

• Gate Level Design

- Schematics (Done)

– Layout (Done)

• To be done:– Spice simulation (97%)

Last week’s Floorplan

LVSed Full-Chip Layout

LVS Output File

Net-lists match

Final Poly Mask

Final Metal 1 Mask

Final Metal 2 Mask

Final Metal 3 Mask

Final Metal 4 Mask

The Chip

• Dimensions– Width = 373.0950µ– Height = 298.00µ

• Area = 111182.31 µ²• Transistor count = 25153

– NMOS: 13407– PMOS: 11746

• Density = 0.23 trans/µ²• Aspect ratio = 1: 1.25

Floating Point Adder 1

Floating Point Adder 2

Floating Point Adder 3

Multiplier 1 Final Simulations Results

Multiplier 1: Rise Time

Rise Time: 48.3823 ps

Multiplier 2 Final Simulation Results

Multiplier 2: Rise Time

Rise Time: 48.729 ps

Adder 3 Final Simulation Results

Adder 3: Rise Time

Rise Time: 39.4352 ps

Full-Chip Critical Path Estimation

Challenges

• Adder 1&2 simulations

• Obtaining accurate full-chip simulation results

Questions?