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Other Switch Architectures Parallel Packet Switch 3 · 2015. 9. 10. · Parallel Packet Switch 4...

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1 The Relative Queuing Delay of Parallel Packet Switches Hagit Attiya CS, Technion Joint work with David Hay ClubNet lecture Mar-16-05 Parallel Packet Switch 2 Output Queued Switches Cells are queued at the output ports when they arrive Switch must operate at aggregate input (=output) line rate! ClubNet lecture Mar-16-05 Parallel Packet Switch 3 Other Switch Architectures Input queuing (IQ) Cells are queued at the input ports Head of line blocking Virtual output-queuing (VOQ) Each input holds a separate (virtual) queue for each output Complex (=expensive) scheduling algorithms Combined input-output queuing (CIOQ) Queuing both in inputs and outputs Memory / control in two locations Still require memory / decision speed input line rate ClubNet lecture Mar-16-05 Parallel Packet Switch 4 Parallel Packet Switch (PPS) [Iyer and McKeown] 3-stage Clos network with K middle stage planes Fixed size packets (cells) switched in parallel through the planes fragmentation and reassembly outside the switch Plane 1 Plane K 1 2 N N 2 1 . . . . . . . . .
Transcript
Page 1: Other Switch Architectures Parallel Packet Switch 3 · 2015. 9. 10. · Parallel Packet Switch 4 Parallel Packet Switch (PPS) [Iyer and McKeown] 3-stage Clos network with K middle

1

1

The R

ela

tive Q

ueuin

gD

ela

y

of

Para

llel Packet

Sw

itches

Hag

it A

ttiya

CS

, Tec

hnio

n

Join

t wor

k w

ith D

avid

Hay

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

2

Outp

ut

Queued S

witches

Cel

ls a

re q

ueue

d at

th

e ou

tput

ports

whe

n th

ey a

rriv

e

Sw

itch

mus

t ope

rate

at

agg

rega

tein

put

(=ou

tput

) lin

e ra

te!

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

3

Oth

er

Sw

itch A

rchitectu

res

Inpu

t que

uing

(IQ

)C

ells

are

que

ued

at th

e in

putp

orts

Hea

d of

line

bloc

king

Virtu

alou

tput

-que

uing

(VO

Q)

Each

inpu

t hol

ds a

sep

arat

e (v

irtua

l) qu

eue

for e

ach

outp

utC

ompl

ex (=

expe

nsiv

e) s

ched

ulin

g al

gorit

hms

Com

bine

d in

put-o

utpu

t que

uing

(CIO

Q)

Que

uing

bot

h in

inpu

ts a

nd o

utpu

tsM

emor

y / c

ontro

l in

two

loca

tions

Stil

l req

uire

mem

ory

/ dec

isio

nsp

eed

≥in

put l

ine

rate

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

4

Para

llel Packet

Sw

itch

(PPS)

[Iye

ran

d M

cKeo

wn]

3-st

age

Clo

s ne

twor

k w

ith K

mid

dle

stag

e pl

anes

Fixe

d si

ze p

acke

ts

(cel

ls)

switc

hed

in p

aral

lel

thro

ugh

the

plan

esfra

gmen

tatio

n an

d re

asse

mbl

y ou

tsid

e th

e sw

itch

Pla

ne

1

Pla

ne

K

1 2 NN21

. . .. . .

. . .

Page 2: Other Switch Architectures Parallel Packet Switch 3 · 2015. 9. 10. · Parallel Packet Switch 4 Parallel Packet Switch (PPS) [Iyer and McKeown] 3-stage Clos network with K middle

2

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

5

Para

llel Packet

Sw

itch

(PPS)

Eac

h pl

ane

is a

nN☓

N s

witc

hW

ith in

put r

ate

r < R

Can

be

an o

utpu

t-qu

eued

sw

itch

The

over

-cap

acity

of

the

switc

h is

its

spee

dup

S =

Kr/R

RRR

Rr

r rr

Pla

ne

1

Pla

ne

K

1 2 NN21

. . .. . .

. . .

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

6

Para

llel Packet

Sw

itch

(PPS)

Dem

ultip

lexo

rat t

he in

put

port

deci

des

whe

re to

sen

d an

inco

min

g ce

llC

ells

arr

ive

and

leav

e at

di

scre

te ti

me

slot

s A

t lea

st R

/r tim

e-sl

ots

betw

een

two

cells

from

an

inpu

t to

a pl

ane

from

a p

lane

to a

n ou

tput

As

in In

vers

e M

ultip

lexi

ng

for A

TMR

RRR

rr r

r

Pla

ne

1

Pla

ne

K

1 2 NN21

. . .. . .

. . .

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

7

PPS P

erf

orm

ance F

igure

s

The

lag

behi

nd a

shad

ow o

utpu

t-que

ued

switc

hO

pera

ting

at ra

te R

Rec

eivi

ng th

e sa

me

traffi

cR

elat

ive

queu

ing

dela

y (R

QD

) Im

pact

of q

ueui

ng w

ithin

the

switc

h N

egle

ct th

e im

pact

of d

iffer

ent p

ropa

gatio

n de

lays

Com

pete

tive

(rel

ativ

e) m

easu

reBu

t add

itive

(rat

her t

han

mul

tiplic

ativ

e)

Rel

ated

to th

ece

ll de

lay

jitte

r, an

d bu

ffer s

ize

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

8

This

Work

How

(lac

k of

) inf

orm

atio

n af

fect

s th

e R

QD

Low

eran

d up

per b

ound

s

Dep

end

on d

emul

tiple

xor t

ype

With

/ w

ithou

t buf

fers

Cen

traliz

ed: G

loba

l inf

orm

atio

nFu

lly-d

istri

bute

d: O

nly

loca

l inf

orm

atio

n u-

Rea

l tim

e (u

-RT)

:Loc

al in

form

atio

n an

d gl

obal

info

rmat

ion

olde

r tha

n u

time

slot

s

Page 3: Other Switch Architectures Parallel Packet Switch 3 · 2015. 9. 10. · Parallel Packet Switch 4 Parallel Packet Switch (PPS) [Iyer and McKeown] 3-stage Clos network with K middle

3

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

9

PPS w

/ C

entr

alize

d C

ontr

ol

[Iye

ran

d M

cKwo

en]

Find

free

link

s be

twee

n in

puts

an

d pl

anes

at a

rriva

l tim

eC

alcu

late

cel

l dis

patc

hing

tim

ein

th

e sh

adow

OQ

sw

itch

Find

free

link

s be

twee

n pl

anes

an

d ou

tput

s at

this

tim

eD

ispa

tch

cell

thro

ugh

a co

mm

on

plan

e (a

t the

targ

et ti

me)

Mus

t exi

stsi

nce

spee

dup

≥2

Zero

RQ

D, b

ut…

Rel

ies

on k

now

ing

the

stat

us o

f al

l inp

ut-p

orts

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

10

Tra

ffic

Restr

ictions

Low

erbo

unds

hol

d ev

en fo

r lea

kybu

cket

flow

s:

No

mor

e th

anτ

R+B

cel

ls s

harin

g an

inpu

t-or

ou

tput

-por

t arr

ive

to th

e sw

itch

durin

g τ

time.

⊳Al

so u

nder

Adve

rsar

ialQ

ueui

ng T

heor

yre

stric

tions

.

Num

ber

of ce

lls d

estined

fo

r a

cert

ain o

utp

ut

For

any

tim

e in

terv

al,

the

scat

tere

dar

ea is

larg

er t

han

th

e gre

y ar

ea b

y at

most

B

time

cells

R

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

11

Concentr

ation S

cenari

o

(Sim

plified)

Assu

me:

Buffe

r at o

utpu

t jis

em

pty

Exa

ctly

m c

ells

for j

arriv

e du

ring

[t,t+

m)

All c

ells

are

sen

t thr

ough

pla

ne k

RQ

D≥

m(R

/r-1)

⊳Ex

act s

et-u

p ne

eded

in th

e ge

nera

l cas

eo

Acco

unt f

or b

urst

so

Pass

age

of ti

me

Can

als

o (lo

wer

) bou

nd th

e ce

ll de

lay

jitte

r.

. . .. . .

. . .j

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

12

Fully D

istr

ibute

d,

Buff

erl

ess L

ow

er

Bound

RQ

D ≥

N[(R

/r)-1

]for

an

unpa

rtitio

ned

algo

rithm

All

dem

ultip

lexo

rs m

ay s

end

a ce

ll to

out

put j

thro

ugh

the

sam

e pl

ane

kTh

e pr

oof c

reat

estra

ffic

that

sen

ds N

cells

th

roug

h th

e sa

me

plan

e to

the

sam

e ou

tput

W

ithin

shor

t tim

eC

lean

buf

fers

initi

ally

Sta

gger

the

cells

to a

void

bur

sts

App

lyth

e co

ncen

tratio

n le

mm

a.

Page 4: Other Switch Architectures Parallel Packet Switch 3 · 2015. 9. 10. · Parallel Packet Switch 4 Parallel Packet Switch (PPS) [Iyer and McKeown] 3-stage Clos network with K middle

4

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

13

Low

er

Bound o

n t

he

Avera

ge R

QD

The

prev

ious

pro

of c

reat

es

traffi

c in

whi

ch s

ome

cell

has

RQ

D ≥

N[(R

/r)-1

]S

ame

RQ

D fo

r fol

low

ing

cells

with

the

sam

e de

stin

atio

n Si

nce

the

switc

h m

ust p

rese

rve

orde

r with

in fl

owFo

r a s

uffic

ient

ly lo

ng tr

affic

aver

age

RQ

D ≥

N[(R

/r)-1

]-εfo

rarb

itrar

ily s

mal

l ε

Cel

l with

hig

h R

QD

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

14

d-Part

itio

ned A

lgori

thm

s

RQ

D ≥

d[(R

/r)-1

]if

dde

mul

tiple

xors

sen

d a

cell

dest

ined

for o

utpu

t j

thro

ugh

plan

e k

sam

e pr

oof…

Inpu

tcon

stra

ints

impl

y d

≥N

/S

RQ

D≥

[N/S

][(R

/r)-1

]Ev

en if

pla

nes

are

a-pr

iori

parti

tione

d

k

j

. . .. . .

. . .

d inputs

use

k

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

15

Fully D

istr

ibute

d,

Buff

erl

ess U

pper

Bound

Frac

tiona

l tra

ffic

disp

atch

(FTD

) alg

orith

m[I

yer

and

McK

eown

, 200

1] [K

hoti

msk

y, K

rish

nan,

200

1]

Div

ide

the

flow

of c

ells

into

blo

cks

of le

ngth

R/r

Two

cells

in th

e sa

me

bloc

k ar

e se

nt th

roug

h di

ffere

nt p

lane

sne

eds

a sp

eedu

p ≥

2H

as R

QD

≈(R

/r)N

Proo

fsar

e fla

wed

.I&

M b

ound

que

uing

in th

e m

ultip

lexo

r (ou

tput

) an

d ig

nore

queu

ing

in th

e pl

anes

K&

K ig

nore

per

iods

whe

n th

e P

PS

is b

usy

and

the

shad

ow is

idle

, and

vic

e ve

rsa

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

16

New

Pro

of

for

FT

D

Our

pro

of m

etho

dolo

gy is

bas

ed o

n bo

undi

ng th

e im

bala

nce

betw

een

plan

esAp

plic

able

to o

ther

type

s of

dem

ultip

lexo

rsA

ssum

esa

glob

al F

CFS

disc

iplin

ebo

th o

n th

e P

PS

and

the

shad

ow s

witc

hce

llsar

rivin

gaf

ter a

cel

l cdo

not

dela

y it

We

prov

e th

at s

ome

cell

c th

at s

uffe

rs m

axim

um

RQ

D is

notq

ueue

d in

the

mul

tiple

xor

It su

ffice

s to

bou

nd th

equ

euin

g w

ithin

the

plan

es

alth

ough

ther

e qu

euin

g in

mul

tiple

xors

is p

ossi

ble

Page 5: Other Switch Architectures Parallel Packet Switch 3 · 2015. 9. 10. · Parallel Packet Switch 4 Parallel Packet Switch (PPS) [Iyer and McKeown] 3-stage Clos network with K middle

5

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

17

How

man

y ce

lls (a

bove

fair

shar

e) a

re s

ent t

hrou

gh p

lane

k,

dur

ing

a tim

e in

terv

al [t

1,t2

]

Imba

lanc

eat

tim

e t,

∆=

max

imum

of ∆

jk (t)

over

all

j, k

and

t.

The Im

bala

nce F

acto

r

),

()

,(

),

(2

12

12

1t

tA

Rrt

tA

tt

jk j

k j−

=∆

),

(max

)(

11

tt

tk j

tk j

∆=

Num

ber o

f cel

ls

dest

ined

forj

Num

ber o

f cel

ls

dest

ined

for j

and

sent

th

roug

h pl

ane

k

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

18

Theo

rem

:

In fa

ct, d

epen

ds o

n th

e m

ax tr

ansi

ent b

urst

Max

imum

num

ber o

f cel

ls w

ith s

ame

dest

inat

ion

arriv

ing

at th

e sa

me

time-

slot

Can

bou

nd th

e R

QD

by

boun

ding

Imbala

nce F

acto

r and R

QD

()

++

∆≤

N1

,0max

rRRQD

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

19

Pro

of

for

FT

D

Hen

ce, t

he m

axim

um

RQ

Dis

Also

the

aver

age

rRrR

N

tt

ARr

rRrR

rR

tt

A

tt

ARr

rR

tt

A

tt

ARr

tt

A

tt

ARr

tt

At

t

jN i

ji

jN i

ji

jN i

kj

i

jk j

k j

1

),

(1

),

(

),

()

,(

),

()

,(

),

()

,(

),

(

21

12

1

21

12

1

21

12

1

21

21

21

−=

−+

−=

−=

∑∑∑

=

=

=→

()1+

NrR

Asym

ptot

ical

ly m

atch

es th

e lo

wer

bou

ndC

lubN

et le

ctur

eM

ar-1

6-05

Par

alle

lPac

ket S

witc

h20

Eas

ier t

o st

art c

alcu

latio

ns w

hen

both

apl

ane

and

the

shad

ow s

witc

h ar

e id

le a

t tim

e-sl

ot

Pre

viou

s ce

lls a

lread

y le

ftW

ill n

otde

lay

futu

re c

ells

Nee

d to

con

side

r bus

ype

riods

in w

hich

eith

erth

e pl

ane

orth

e sh

adow

sw

itch

are

not i

dle

The

plan

eop

erat

esat

low

er ra

tePl

ane

busy

per

iod

can

belo

nger

The

plan

ere

ceiv

eson

ly a

sub

seto

f the

traf

fic

Shad

owsw

itch

busy

per

iod

is lo

nger

Busy P

eri

ods

Page 6: Other Switch Architectures Parallel Packet Switch 3 · 2015. 9. 10. · Parallel Packet Switch 4 Parallel Packet Switch (PPS) [Iyer and McKeown] 3-stage Clos network with K middle

6

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

21

1-Real

-T

ime, B

uff

erl

ess

Low

er

bound

If th

ere

are

no b

urst

sO

nly

one

inpu

t get

s a

cell

for o

utpu

t jFu

ll in

form

atio

n ab

out t

raffi

c to

out

put j

Can

sim

ulat

e ce

ntra

lized

alg

orith

m

With

bur

stin

ess

fact

or [N

/K]-1

RQ

D ≥

[N/S

][1-(

R/r)

]C

an b

e ex

tend

edto

ave

rage

RQ

D

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

22

Matc

hin

g U

pper

Bound

Div

ide

plan

esin

toeq

ual-s

ize

sets

Two

phas

es, e

ach

usin

g on

ly p

lane

s of

one

set

Aph

ase

ends

whe

n m

any

of it

s pl

anes

are

not

ba

lanc

ed(∆

≠0)

W

ith s

uffic

ient

spe

edup

, the

plan

es o

fthe

oth

er s

et

are

bala

nced

whe

n th

e ph

ase

ends

Spe

edup

S=8

yiel

dsR

QD

<4N

Asym

ptot

ical

ly m

atch

ing

the

low

er b

ound

(fo

r con

stan

t S)

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

23

Can R

andom

ization H

elp

?

Spre

adce

lls a

cros

s pl

anes

Cho

ose

at ra

ndom

to w

hich

elig

ible

pla

ne to

sen

d a

cell

Som

e ce

llsu

ffers

high

RQ

D

With

low

pro

babi

lity

(but

non

-neg

ligib

le)

Am

plifi

catio

n:m

any

trial

s un

til th

is h

appe

ns w

ith v

ery

high

pr

obab

ility

Perp

etua

te th

is h

igh

RQ

DSi

nce

the

switc

h m

ust o

bey

per-

flow

FC

FSAl

mos

t sam

e av

erag

eR

QD

as

dete

rmin

istic

alg

orith

ms

Rel

ies

on a

n ad

aptiv

ead

vers

ary

Wha

t hap

pens

whe

n th

e ad

vers

ary

is n

on-a

dapt

ive?

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

24

PPS w

ith B

uff

ers

at

the

Input-

Port

s

Del

ay is

the

sum

of q

ueui

ng in

the

inpu

t-po

rts a

nd in

the

plan

esD

emul

tiple

xing

alg

orith

m is

mor

e fle

xibl

e| i

nput

buf

fer |

≥u:

RQ

D ≤

u B

lack

box

redu

ctio

n to

CP

A| i

nput

buf

fer |

< u

: RQ

D >

[N/S

][1-(

R/r)

], ev

en w

ith 1

-RT

algo

rithm

Fully

dis

tribu

ted

algo

rithm

s ar

e ∞

-RT

Page 7: Other Switch Architectures Parallel Packet Switch 3 · 2015. 9. 10. · Parallel Packet Switch 4 Parallel Packet Switch (PPS) [Iyer and McKeown] 3-stage Clos network with K middle

7

Clu

bNet

lect

ure

Mar

-16-

05P

aral

lelP

acke

t Sw

itch

25

Futu

re R

esearc

h

Ran

dom

izat

ion

agai

nst o

bliv

ious

, non

-ada

ptiv

ead

vers

ary

Mul

ticas

t tra

ffic

Par

tial,

out-d

ated

info

rmat

ion

abou

t the

sw

itch

Cre

dit-b

ased

con

trol

Som

e de

gree

of s

ynch

roni

zatio

n

26

T H

A N

K

Y O

U !


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