1 1 Scheduling algorithms for input-queued IP routers Packet switch architectures 2015/16 Andrea Bianco Paolo Giaccone Gruppo Reti di Telecomunicazioni Dipartimento di Elettronica Politecnico di Torino http://www.tlc-networks.polito.it 2 Outline IP routers OQ routers IQ routers Scheduling Optimal algorithms Heuristic algorithms Packet-mode algorithms Networks of routers QoS support CIOQ routers Multicast traffic Conclusions 3 Note The slides marked RWP are reproduced with permission of Prof.Nick McKeown from the Electrical Engineering and Computer Science Dept. of Stanford University (CA,USA)
Transcript
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Scheduling algorithms for input-queued IP routers
Packet switch architectures 2015/16
Andrea Bianco Paolo Giaccone
Gruppo Reti di Telecomunicazioni
Dipartimento di Elettronica Politecnico di Torino
http://www.tlc-networks.polito.it
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Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
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Note
The slides marked RWP are reproduced with permission of Prof.Nick McKeown from the Electrical Engineering and Computer Science Dept. of Stanford University (CA,USA)
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4
Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
5
“The Internet is a mesh of routers”
core router
access router
enterprise router
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Access router: Ø high number of ports at low speed (kbps/Mbps) Ø several access protocols (modem, ADSL, cable)
Enterprise router: Ø medium number of ports at high speed (Mbps) Ø several services (IP classification, filtering)
Core router: Ø low number of ports at very high speed (Mbps/Gbps) Ø very high throughput Ø few services
“The Internet is a mesh of routers”
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Basic architecture
Control Plane
Datapath per-packet processing
Switching Forwarding Table
Routing table
Routing protocols
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Basic functions
Ø Routing § computation of the output port of
an incoming packet (forwarding) § uses the routing tables computed by
the routing protocols § can be a complex procedure:
• very large routing tables • dynamic variation of routes in the Internet
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Basic functions
Ø Switching § transfer of packets from input ports
to output ports § solution of the contentions for output ports
• queueing methods – where to store
• scheduling methods – what to transfer
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Faster and faster
Ø Need for high performance routers § to accommodate the bandwidth demands
for new users and new services § to support QoS (over-provisioning) § to reduce costs with respect to a cloud of smaller size
routers (maybe) • a smaller number of fibers is needed • a smaller number of devices (but it is less costly?) • May be more energy hunghry
Ø Increase of electronic packet processing power cannot accommodate the increase in link speed
Moore’s law 2x / 18 months
Butter’s Law 2x / 9 months
12 0,001
0,01
0,1
1
10
100
10001980 1983 1986 1989 1992 1995 1998 2001
Acc
ess
Tim
e (n
s)
Moore’s Law 2x / 18 months
1.1x / 18 months
RWP
Memory access time
5
13
It’s hard to keep up with Moore’s law: § the bottleneck is memory speed
Moore’s law is too slow: § routers need to improve faster
than Moore’s law
RWP
Moore’s law
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Router capacity exceeds Moore’s law
Growth in capacity of commercial routers: § 1992 ~ 2 Gb/s § 1995 ~ 10 Gb/s § 1998 ~ 40 Gb/s § 2001 ~ 160 Gb/s § 2003 ~ 640 Gb/s § … till 2003 average grow rate around 2.2x/18
months § 2012 ~ 10 Tb/s § 2014 ~ 100 Tb/s
RWP
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Single packet processing
Ø The time to process one packet is becoming shorter and shorter § worst case: 40-Byte packets (ACKs)
travelling over the Internet • 3.2 µs at 100 Mbps • 320 ns at 1 Gps • 32 ns at 10 Gps • 3.2 ns at 100 Gbps • 320 ps at 1Tbps
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S F
LC
LC
LC
LC
CP
S F
IP
IP
IP
IP
CP
OP
OP
OP
OP
Hardware architecture
physical structure logical structure
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Hardware architecture
Main elements Ø line cards
§ support input/output transmissions § adapt packets to the internal format of the switching fabric § support data link protocols § In most architectures
• store packets • classify packets • schedule packets • support security
Ø switching fabric § transfers packets from input ports to output ports
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Ø control processor/network processor § runs routing protocols § computes and stores routing tables § manages the overall system § sometimes
• store packets • classify packets • schedule packets • support security
Ø Virtual output queueing (VOQ) § one queue for each input/output pair
• N queues at each input • N2 queues in the whole switch
§ eliminates HOL blocking § used in high-bandwidth routers
• scheduling implemented in hardware at very high speed
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IQ switches with VOQ
Output N
Input 1 1
N
Output 1
Input N 1
N
scheduler
switching fabric
Note: from now on, we always assume VOQ at the switch inputs
input constraints
output constraints
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Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
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Scheduling in IQ switches
Ø Scheduling can be modeled as a matching problem in a bipartite graph § the edge from node i to node j refers to packets
at input i and directed to output j § the weight of the edge can be
• binary (not empty/empty queue) • queue length • HOL cell waiting time, or cell age • some other metric indicating the priority
of the HOL cell to be served
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Scheduling in IQ switches
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Graph G Matching M1
2
3
4
3
4
2
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8
2
5
4
4
8
1
2
3
4
1
2
3
4
1
2
3
4
Graph Matching
inputs outputs
scheduler
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Implementing schedulers
Ø Scheduling is a complex task § a scheduling algorithm can be implemented
in hardware if: • it shows good performance for a wide range
of traffic patterns • it can be efficiently parallelized • it can be efficiently pipelined • it requires few iterations (or clock cycles) • it requires limited control information
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Scheduling uniform traffic
Ø A number of algorithms give 100% throughput when traffic is uniform § For example:
• TDM and a few variants • iSLIP (see later)
RWP
Example of TDM for a 4x4 switch
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Scheduling non-uniform traffic
Ø If the traffic is known and admissible, 100% throughput can be achieved by a TDM using: § for a fraction of time a1 matching M1 § for a fraction of time a2 matching M2 § for a fraction of time ak matching Mk
§ subject to ∑i ai = 1 Ø thanks to the Birkhoff - von Neumann
theorem
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Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
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Maximum Weight Matching
Ø Maximum Weight Matching (MWM) § among all the possible N! matchings, selects the one
with the highest weight (sum of the edge metrics) • MWM is generally not unique
§ MWM is too complex to be implemented in hardware at high speed
• the best MWM algorithm requires O(N3) iterations, and cannot be implemented efficiently, since it is based on a flow augmentation path algorithm
• cannot be parallelized and pipelined efficiently § MWM has never been implemented in a commercial
chipset
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Maximum Weight Matching
Ø MWM is the optimal solution of the scheduling problem when the traffic is unknown, when the weight is either the queue length or the cell age § achieves 100% throughput under any traffic
• also under non-Bernoulli arrival processes, satisfying the law of large numbers
§ achieves low average delays, very close to those of OQ switches
§ possible starvation for lightly loaded packet flows
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MWM with pipeline and latency
Ø Let T and P be fixed Ø Dt denotes the matching used at time t Ø The following variations of MWM also achieve
100% throughput: § Dt = MWM(t-P) MWM with pipeline degree P § Dt = MWM(ceil(t/T)•T) MWM with latency T § combinations of both
Ø thus, it seems easy to achieve 100% throughput!
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MWM with pipeline and latency
Ø But: § What about throughput?
• 100% throughput – but needs the computation of a MWM …
§ What about delays? • delays can be really bad!
J
L
L
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General consideration
Ø When scheduling in IQ switches, it is very difficult to achieve simultaneously § high throughput § low delay § limited implementation complexity
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Maximum Size Matching
Ø Maximum Size Matching (MSM) § among all the possible matchings, selects the one
with the highest number of edges (like MWM with binary edge weights)
• MSM is generally not unique § the best MSM algorithm requires O(N2.5) iterations,
and cannot be implemented efficiently, since it is based on a flow augmentation path algorithm
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Maximum Size Matching
Ø MSM maximizes the instantaneous throughput
Ø MSM may not yield 100% throughput § short term decisions can be inefficient
in the long term § non-binary edge weights allow MWM
to maximize the long-term throughput
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Instability of MSM Ø Assume:
§ P(arrival at Q12) = λ § P(arrival at Q11) = P(arrival at Q22) = 1-λ-ε
§ Q12 = B » 0 Q11 = Q22 = 0 § in case of parity serve Q11 and/or Q22 instead of Q12
Ø Observe: § Q12 is served only when A11 = 0 and A22 = 0, i.e. with probability:
P(serve Q12) = P(no arrivals at both Q11 and Q22 ) = [1-(1-λ-ε)]2 = (λ+ε)2 § P(serve Q12) < P(arrival at Q12) if ε is small enough § Example: λ = 0.5; ε = 0.1;
P(serve Q12) = 0.36 In1
In2
Out1
Out2
1-λ-ε
1-λ-ε
λ
Note: this proof is due to I.Keslassy and R.Zhang, Stanford Univ.
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Uniform traffic Ø MWM and MSM behave almost identically
1
10
100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Mea
n de
lay
Normalized Load
Uniform Traffic
MWM MSM
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LogDiagonal traffic Ø MSM is somewhat inferior to MWM
1
10
100
1000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Mea
n de
lay
Normalized Load
LogDiagonal Traffic
MWM MSM
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Diagonal traffic Ø MSM yields much longer delays than MWM at medium/high loads
1
10
100
1000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Mea
n de
lay
Normalized Load
Diagonal Traffic
MWM MSM
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Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
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Approximations of MSM and MWM
Ø Motivation § strong interest in scheduling algorithms with
• very low complexity • high performance
Ø Usually § implementable schedulers (low complexity)
⇒ low throughput, long delays § theoretical schedulers (high complexity)
⇒ high throughput, short delays
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Some implementable algorithms
Ø Approximate MSM § WFA, iSLIP, 2DRR, RC, FIRM and many others
§ Request (from inputs to outputs) • each unmatched input sends a request
to every output for which it has a cell § Grant (from outputs to inputs)
• if an unmatched output receives requests, it sends a grant to one of the inputs
– contentions solved by a round-robin mechanism § Accept (from inputs to outputs)
• if an unmatched input receives grants, it selects a single output and it becomes matched to it
– contentions solved by a round-robin mechanism
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iSLIP
Ø The round robin mechanism in iSLIP is designed so that, under uniform traffic, iSLIP emulates a dynamic TDM scheduler synchronized on the arrival pattern
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iSLIP
Ø iSLIP is maximal • often, with log N iterations • always, with N iterations
Ø iSLIP was implemented on a single chip in the Cisco 12000 router § http://www.cisco.com/warp/public/cc/pd/rt/12000/tech/fasts_wp.pdf
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APPROXIMATIONS OF MAXIMUM WEIGHT
MATCHING
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iLQF
Ø iLQF means “iterative Longest Queue First”
Ø iterates among the following 3 phases § Request § Grant § Accept
Ø Properties of Mt § informally, Mt should be a “good” sample
in the space of all possible matchings Ø Examples:
§ Mt is a matching picked uniformly at random
§ Mt is derived from the arrival vector At
§ Mt is a good “neighbor” of Dt-1
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100
Theoretical properties
Dt-1
Dt
COMP1
Mt
Ø Stability § 100% throughput under any
admissible Bernoulli traffic pattern
Ø Delay § the better is the weight of Mt ,
the smaller are the queue lengths, and hence the smaller are the delays
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Dt-1
Mt
Dt
MAX
MAX
N1 NK
At
K-th neighbor of Dt-1
Example of practical implementation Ø Exploiting parallel search:
Ø This scheme is called APSARA
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What is a “neighbor” of a matching?
• Each neighbor – differs from Dt-1 in ONLY TWO edges – can be generated very easily in hardware
3 neighbors
• Example: 3 x 3 switch Dt-1
N1 N2 N3
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Max-APSARA
Ø APSARA, as described before, is not maximal
Ø Max-APSARA is a modified version of APSARA where a maximal size matching algorithm runs on the remaining unmatched inputs/outputs § e.g., if k inputs/outputs are unmatched,
• run iSLIP with k iterations • select k random edges among the
unmatched inputs/outputs
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APSARA performance
0.01
0.1
1
10
100
1000
10000
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Mea
n IQ
Len
gth
Normalized Load
Diagonal Traffic
MWMMaxAPSARA APSARA iSLIPiLQF
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Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
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Routers and switches
Ø IP routers deal with variable-size packets Ø Hardware switching fabrics often deal
with fixed-size cells Question:
§ how to integrate an hardware switching fabric within an IP router?
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Router based on an IQ cell switch: cell-mode
switching fabric
IQ cell switch 1 ISM
N ISM
ORM 1
ORM N
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Cell-mode scheduling
Ø Scheduling algorithms work at cell level § pros:
• 100% throughput achievable § cons:
• interleaving of packets at the outputs of the switching fabric
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Router based on an IQ cell switch: packet-mode
switching fabric
IQ cell switch 1 ISM
N ISM
ORM 1
ORM N
NO packet interleaving
if packet-mode
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Router based on an IQ cell switch: packet-mode
switching fabric
IQ cell switch 1 ISM
N ISM
ORM 1
ORM N
NO packet interleaving
if packet-mode
ORMs can be removed
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Packet-mode scheduling
Ø Rule: packets transferred as trains of cells § when an input starts transferring the first cell
of a packet comprising k cells, it continues to transfer in the following k-1 time slots
Ø Pros: § no interleaving of packets at the outputs § easy extension of traditional schedulers
Ø Cons: § starvation due to long packets
• inherent in packet systems without preemption • negligible for high speed rates
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Packet-mode scheduling
Ø Questions § can packet mode provide high
throughput?
§ what about delays? YES! J
It depends…K
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Packet-mode properties
Ø Main theoretical results § MWM in packet-mode yields 100% throughput § Packet mode can provide shorter delays
than cell mode, depending on the packet length distribution
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Simulation scenario
Ø Router with ISMs and ORMs Ø Uniform packet traffic
Spotted packet traffic for cell mode MWM MSM iSLIP iLQF
Cell-mode Packet-mode
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At high load PM becomes better
Effect of packet size distribution Ø iSLIP delayCM/delayPM for different packet size distributions
better PM
better CM
0
0.5
1
1.5
2
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Pac
ket m
ode
gain
for i
SLI
P
Normalized load
Uniform Exponential Trimodal Bimodal
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Packet mode features
Ø Packet mode scheduling § is a feasible modification of schedulers § improves throughput
• but it can generate some unfairness between long and short packets
– inherent to all variable-packet networks without preemption
§ may give better packet delays than cell mode • depends on the packet size distribution
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Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
120
Network of IQ routers
Ø Question: § given a network of IQ switches running MWM
and an admissible input traffic, is the network always stable?
NO! L
this is quite counterintuitive…but true
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121
Networks of IQ routers
Ø Consider the acyclic network of IQ routers in the following slide § derived from well established results
from adversarial queueing theory § a very specific scenario, but comprises
only few switches… • this situation may not be common,
but cannot be excluded in real networks
122
Pathological network of IQ switches
Network with 8 switches and 4 flows
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Instability of MWM
Ø If MWM is adopted at each IQ router, and the traffic is admissible, the system can be unstable under Bernoulli i.i.d. arrivals
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Instability of MWM
Ø MWM is too greedy, in the sense that it can create traffic bursts that are amplified by each scheduler
Ø A server can be idling when large bursts (directed to it) are blocked because of the contentions upstream § the problem arises when a packet flow is
subject to priority changes along its path through the network
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Stability in networks of routers
Ø Global policies § “Oldest in the network” and many others
• problem: requires global information about the network, and synchronized clocks at the ingress of the network
126
Stability in networks of routers
Ø Semi-local policies § MWM with local information about the router
neighbors can achieves 100% throughput under i.i.d. Bernoulli arrivals
§ Virtual network queue • the weights used by MWM are:
– wij = max{0,Xij-Xdown-queue(ij))} where down-queue(ij) is the first downstream
queue which is receiving packets from Xij
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Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
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IQ and QoS
Ø Problem: § support rate guarantees, with admissible rate
matrix
129
Birkhoff von Neumann decomposition
Ø goal: find a sequence of matchings Mk and their fraction of time φk such that the service given to all the queues satisfies R
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IQ and frame scheduling
Ø Example:
M1
φ1=1/4, φ2=1/2, φ3=1/4
M2 M2 M3 M1 M2 M2 M3
frame i frame i+1
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How to decompose R?
Ø R double substochastic
Ø R’ double stochastic such that R’≥R
Ø R’ decomposition
augmentation algorithm
BvN algorithm
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Augmentation algorithm
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133
BvN algorithm
134
BvN algorithm
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Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
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136
CIOQ routers
Output 1
switching fabric
Output N
S
S
o1
oN
Input 1 S
Input N S
VOQ
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CIOQ routers
Ø Question: § if a low speedup S is allowed (and queues
are available at both inputs and outputs), is it possible to design simple scheduling algorithms, capable of achieving high throughput and low delay?
YES! J
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OQ emulation
Ø a CIOQ switch achieves perfect OQ emulation if the departure order of all the packets from each output is the same as the emulated OQ § it is impossible to distinguish, by observing
arrivals and departures, if the switching architecture is CIOQ or OQ
§ delays are perfectly controlled • easy to implement scheduling algorithms
born for OQ (eg: WFQ)
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Work conservation
Ø a CIOQ switch is work-conserving when each output is busy at the same time as the corresponding OQ switch § i.e., each output of the switch for which there are cells
(either at the inputs or at the outputs) at the beginning of cell slot T is active at the end of the cell slot T
§ output never idling whenever a packet is present destined to it
§ good delay performance: same average delays as OQ Ø note that OQ emulation implies work conservation
but not viceversa
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Speedup and performance
Ø speedup 4 § exact OQ emulation
Ø speedup 2 § exact OQ emulation § work conservation
• same average delay than OQ
141
CIOQ routers with S=2
Ø If S = 2 § easy to obtain 100% throughput
• any maximal matching obtains 100% throughput
§ less easy to obtain work conservation • LOOFA algorithm
§ it is difficult to obtain perfect OQ emulation • stable marriage algorithm with special
preference list
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LOOFA
Ø Occupancy oj : number of cells currently residing at the j-th output queue
• at each time slot, oj is decremented by one because of departures
Ø Basic idea of LOOFA § Higher priority is given to outputs with lower
occupancy, thereby attempting to maintain work-conservation for all outputs
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LOOFA
Ø If S = 2, during each of the two phases § each unmatched input selects a non-empty
VOQ directed to the unmatched output with the lowest occupancy, and sends a request to that output
§ each unmatched output grants one request • the selection can be round robin, random, ...
§ repeat until the matching is maximal
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LOOFA with S=2
Ø TEO: § LOOFA achieves work conservation if S = 2
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145
OQ emulation with S=4
Ø urgency of a cell=departure time in OQ-current time
Ø MUCF (Most urgent cell first) During each phase: 1. outputs request their most urgent cells from inputs 2. input grants output with the most urgent cell 3. loser output tries to obtain their next urgent cell 4. when no more matchings are possible, cells are
transferred and the next phase starts
146
OQ emulation with S=4
Note: picture reproduced from Balaji Prabhakar and Nick McKeown, "On the Speedup Required for Combined Input and Output Queued Switching.", Computer Systems Technical Report, November 1997
147
OQ emulation and speedup 4
Ø TEO: § MUCF with speedup 4 obtains OQ emulation
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CIOQ routers
Ø CIOQ are very promising architectures § many degrees of freedom in design
• how to balance input/output buffers • how the buffers interact
– e.g., by backpressure mechanisms
Ø Several currently designed architectures are supposed to be CIOQ
Ø Speedup S is becoming closer and closer to 1 in practical implementations of new switching architectures (CIOQ →IQ)
149
Outline
Ø IP routers Ø OQ routers Ø IQ routers
§ Scheduling § Optimal algorithms § Heuristic algorithms § Packet-mode algorithms § Networks of routers § QoS support
Ø CIOQ routers Ø Multicast traffic Ø Conclusions
150
Multicast traffic
Misleading idea: Ø observe
1. OQ can achieve 100% throughput under any admissible unicast and multicast traffic
2. OQ can be perfectly emulated by CIOQ with S = 2
§ then, with S = 2 it is possible to achieve 100% throughput for multicast traffic
WRONG! L because observation 2 holds only for unicast traffic
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151
Multicast traffic
Ø Question: § what is the minimum speedup required
to achieve 100% throughput?
unknown! L
152
Multicast traffic Ø Possible implementations
§ copy network before the switching fabric • a multicast cell with f destinations is treated as f cells • possible bandwidth inefficiency
§ dedicated queue • multicast packets are treated in some specific way
1 UC
MC N
N × N
UC+MC
N × N
153
Multicast traffic: optimal queueing
Ø MC-VOQ queueing § best throughput performance
• avoids HOL blocking § 2N-1 queues for each input, one for each fanout set
• re-enqueuing process ⇒ out-of-sequence problem • no re-enqueuing ⇒ some throughput degradation
MC+UC
1
2N-1 N × N
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154
Multicast traffic: optimal scheduling
Ø The optimal scheduling for multicast traffic can be defined similarly to unicast traffic § it is a sort of max flow algorithm on all N(2N-1)
queues Ø Many heuristics can be envisaged
to approximate it
155
Summary
Ø 3 main ingredients for IQ scheduling algorithms: § Weight computation § Matching computation § Contention resolution
156
Summary
Ø Weight computation § obtains the priority of each input queue § the metric can be related to queue length,
waiting time of the cell at the HOL, … Ø Contention resolution
§ whenever the selection is among situations with equal weights
§ can be round robin, or random
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157
Summary
Ø Matching computation § computes the matching, trying to maximize
its total weight § can be based on
§ an iterative search, like in iSLIP, iOCF, iLQF
§ a matrix greedy approach, like in MUCS, WFA
§ a reservation vector, like in RPA § a learning approach, like in APSARA
158
Summary
Ø Good IQ scheduling algorithms exist: § 100% throughput § short delay § limited complexity
Ø Performance differences are significant only close to saturation
159
Summary
Ø Open questions concerning IQ schedulers: § QoS guarantees § stability of networks of switches § multicast traffic
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§ Moon S.H., Sung D.K., ``High-performance variable-length packet scheduling algorithm for IP traffic'', IEEE GLOBECOM'01, Dec.2001
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switching systems'', IEEE GLOBECOM'97, vol.1, New York, NY, 1997, pp.170-174 § Guo M., Chang R., ``Multicast ATM switches: survey and performance evaluation'', Computer Communication
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in multiple input-queued switches”, IEEE Symposium on Computers and Communications, pp.166 –171, 2001
§ Smiljanic A., “Flexible bandwidth allocation in high-capacity packet switches”, IEEE/ACM Transactions on Networking, vol.10, n.2, pp.287-293, Apr.2002
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ISCC'98, July 1998, pp.331-335, Athens, Greece
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§ M.Andrews, L.Zhang,``Achieving Stability in Networks of Input-Queued Switches'',IEEE INFOCOM 2001, Anchorage, Alaska, Apr.2001, pp.1673-1679
§ M.Ajmone Marsan, E.Leonardi, M.Mellia, F.Neri,``On the Throughput Achievable by Isolated and Interconnected Input-Queued Switches under Multicass Traffic'',IEEE INFOCOM 2002, New York, NY (USA), June 2002
§ M. Ajmone Marsan, P. Giaccone, E. Leonardi, F. Neri,``On the Stability of Local Scheduling Policies in Networks of Packet Switches with Input Queues'', IEEE JSAC, to appear, 2003
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