Overview of KLM Electronics - University of Hawaiʻiidlab/bronson/projects/... · 2015. 8. 28. ·...

Overview of KLM ElectronicsIsar Mostafanezhad

University of Hawaii at Manoa

Belle II Summer School at PNNL

August 2015

1

Overview of the Talk

1. Team Members and Moles

2. KLM Scintillator Readout Electronics Development at UH Manoa

3. HW/FW/SW Overview

4. Timeline of Operations

5. Design History

6. Production Testing and Calibration

7. Commissioning

8. Summary and Continued Efforts

2Belle II Summer School, PNNL, August 2015

Team Members and Roles


Gary VarnerUH PI

ASIC designSystem

Architect

Isar MostafanezhadUH PostdocTech Lead

FW/SW/Test Dev.Commissioning

Xiaowen ShiUH Grad

HW DesignHW Production

Bronson EdralinUH Grad

SW DesignSW Test Dev.

Chris KetterUH Grad

Mech. Design

Julien C.UH UndergradLocal Assembly

Vihtori VartaUH Grad

Local Assembly/Test

Eduardo K.UH Intern

Testing

Matt AndrewUH EE Staff

HW Design Reviews

Brandon KunklerIU EE Staff

FW Dev.: RPC and Data Concentrator

Gerard VisserIU EE Staff

HW Design Reviews

Leo PiilonenVPI PI

US KLM Manager

Belle II: KLM Scintillator Upgrade

• KLM detectors:• Endcap: scintillators

• Barrel: scintillators +RPCs

• Located outside the magnet

• ITEP

High performance readout system for Belle II KLM- IEEE NSS 2014, N47-6: Thursday Nov 13, 2014 11:45 am -12:00 pm


KLM scintillator upgrade

• RPC-based KLM demonstrated good performance at Belle (efficiency endcap > 90%, barrel ~ 99%, stable operation, low bg)

• With SuperKEKB luminosity, it is still possible to use RPC in the outer barrel, however the efficiency of endcap KLM becomes unacceptably low due to high neutron background and large RPC dead time.

• Requirements to maintain KLM performance:• Low dead time:

KLM Readout module specifications


6

ASIC: TARGETX developed at UH Manoa, TSMC 0.25DAQ: USB, or PocketDAQ, or Ethernet

Requirements: Low cost, high performance

Scintillator channels ~20k

TARGETX ASICs (& daughtercards) 1250

Channels/ASIC 16

9U VME Motherboards 144

Endcap layers 14

Endcap segments 4

Modules per endcap 56

Barrel segments 8

Barrel layers 15

Modules in barrel 32

Sample rate (GSa/s) 1.0

Single sample resolution (bits) 10-12

Belle II Summer School, PNNL, August 2015

KLM Scintillator Electronics:Parts and Quantity

• 144 Modules required for the KLM scintillator sub-detector

• Each Module:• Covers up to 150 scintillator bars(channels) with MPPC readout• 1x KLM Motherboard

• Chassis for daughtercards and SCROD

• 1x KLM Ribbon Header Interface Card (RHIC)• Provides MPPC bias, slow control, and routes signals to/from MPPCs to Motherboard

• 1x KLM SCROD Rev A• System Control and Readout Module

• 10x TARGETX Daughtercards• Full waveform 1GSa/s ADCs, one ASIC(16 channels) per daughtercard

• All parts are production quality: barcoded or laser engraved


Key Hardware Components and Locations

8

RHIC

MotherboardSCROD

10x TXDC

Data Concentrator

PocketDAQ:HSLB, COPPER

FTSWUT3Barrel/Endcap Scintillators

Preamps and Carriers

Detector LayersOn top or

around Magnet

E-hut

HV Power Supply

9UVME

6UVME


Hardware Overview I

• Preamps carrier card:• Located inside the scintillator packaging

• 15 preamps connect to one carrier card

• Each preamp is a differential pair BJT, Bias: +1.2V and -3.8V, 17 mA per ch.

• ~10m ribbon cables bring bias and signal from/to motherboard


Hardware Overview II

• Ribbon Header Interface Card (RHIC):• Connected to the VME crate on top of the magnet

• Generates negative side of preamps bias

• Generates MPPC bias and routes HV to the carrier

• MPPC bias monitoring

• Analog signal routing to the motherboard

• Barcoded

10

Crate testing at UH


Hardware Overview III

• KLM Motherboard:• 9U VME design, +3.3V, +5V, -5V

• Chassis and power/signal routing

• Mounts 1x SCROD and 10x TARGETX Daughtercards

• Protection fuse

• Calibration pin header

• Barcoded


Hardware Overview IV

• SCROD Rev A5• Standard Controls and ReadOut Device

• Spartan-6 FPGA

• SRAM for pedestal storage and operations

• SFP, TTD, R-JTAG

• Barcoded


Hardware Overview V

• TARGETX Daughtercard• TARGET X ASIC: 1GSa/s digitizer

• 16 channels: 15 scintillators and 1 calibration

• Positive side of preamps bias

• BALUN transformers

• Laser engraving

13

Laser Engraving


The TARGET-X ASIC: TeV Array Readout GSa/s Electronics with Trigger

• 16 Channel ADC at 1 GSa/s• ~16 MHz LVDS sampling clock• ~64 MHz LVDS digitization & readout clock (16 channels at once)• 2x32 sampling array• 512x32 storage array (~16.3 us depth)• ~1mV input noise• 11 bit effective, 1.9V range• Trigger encoding for reducing # of pins• TSMC 250nm• Designed at UH Manoa ID Lab.



Benchtop and crate assembly

15

Fully populated KLM barrel crate at KEK.Ribbon cables enter from the bottom.4 Sectors, 2 layers each

Benctop testing of the latest HW at UH


Scintillator FW Overview I

• 1 Xilinx Spartan-6 FPGA controls 10 TARGETX ASICs• Provide sampling and digitization clocks

• Programs ASICs’ slow control bias and timing registers

• Programs HV trim DACs on the RHIC

• Perform ASIC readout, calibration, pedestal subtraction and Q & T calculation

• Routes ASIC trigger bits and readout data to Data Concentrator

• Code developed in VHDL within Xilinx ISE• Supports USB, PocketDAQ and Ethernet (WIP) communication


Scintillator FW Overview II

B2TT

Conc.intfc

AuroraCore

FO: serial RX

RX_d:16b

TX_d:16b

Waveform FIFO

FO: serial TX

FTSW: CLK+External Trig

FIFO_d:96b

from ASIC: Trig bits

Run Ctrl: 16b,to ASICs, DC and MB+ Pedestals

Run Ctrl +Pedestal FSM

Register bank-> ASIC + SCROD

MPPC Bias, Temp ADC

ASIC Readout Control

FSM: Populate Registers

Status regs

Charge & Time:WaveformDemux+ Ped sub.

DAQ_d:16b*Ethernet CommunicationOnly for calibration and test FW

Pedestal RAM

3

Data Concentrator

FTSWTARGETX


TARGETX ASIC Readout

32 samples

TX ASICAnalog Storage

Sampling Array

32 analog samples

t0t1

Digitization +Readout

t0 is advanced in sync with the 127MHz clockt1-t0 is a run control parameter: in the order of 5.2 us

RF Input

SCROD


9UMB/SCRODTX FW

FTSW

COPPER

Data Concentrato,

RPC FWuT3

SFP (B2Link)

SFP(Aurora)Global Decision

Logic

PrPMC

B: HSLB FWFIFO

Readout PC

CLK+TRIG

Global L1 Trig

CLK + ext TRIG

RPC or Scin TRIG

Scintillator FW Overview III9U VME Crate

6U VME Crate

E-hut


Scintillator FW Overview IV

• Idle operation:• FPGA buffers trigger bits with a depth >5.2 us.

• TARGETX buffers analog samples with a depth >16 us.

• Triggered readout, where FPGA:• will look back ~5.2us in trigger buffer for channels with hits

• will calculate the readout position within the AISC

• performs digitization and readout of ~128 ns samples

• subtracts pedestals and calculates Q and T

• Sends event data with debug info to Data Concentrator


Software Overview

• Developed for testing at UH• C++ code for USB readout• Python wrapper for production test scripts• Coming up: python code for Ethernet readout

• Automated testing scripts• TargetX timing optimization• Minimal user intervention for long tests >8hrs• Integrates with in-house inventory database:

• Retrieve HW configs• Store test results for future reference

• In-house inventory tracking software • Web based• Barcode scanning• Detailed test results and shipping information


Timeline of Operations

22

Apr ‘14

May ‘14

Jun’14

Jul’14

Aug’14

Sep’14

Oct’14

Jul’15

Jun’15

May’15

Apr’15

Feb’15

Mar’15

Jan’15

Dec’14

Nov’14

Aug’15

Sep’15

Oct’15

Started at UH

TargetXReadout RevA

Integrationat IU

FW Dev,TX Rev.B prod, testing

B2GM:KEK Sector testing

Remote debugUSB Readout

Modified Rev. B at KEK

Rev. C:Reduce power, cost

Rev. C Pre Prod., Testing

B2GM:Full Barrel Sector EcapSLC

CRTCRT CRT

Full Production TestingCommissioning

Background events and attempts:FW debugging, UH+KEK PocketDAQ upkeep, Ethernet development, FW version control and maintenanceKEK power shutdowns,…


Pre production: Rev.A, testing and debug Pre production: Rev. B, FW Dev Pre production: Rev.C Testing and commissioning

KLM Readout HW Design Revisions

• Rev.A• ~July 2014

• First attempt at TARGETX readout

• Rev.B• ~September 2014

• Redesigned SCROD with fewer components

• Rev.C• ~March 2015

• RHIC Component replacement to reduce production costs (save ~50k)

• Optimize power consumption for better performance in full Endcap crates


Production Testing and Calibration

• TargetX• Noise test, pedestal test• All channels operational, all readout windows operational• Timing calibration for best performance

• 40MHz sine input @ 600mVpp• Per chip scan of timing register

• Analog Front-end• MPPC bias test• Preamplifier carrier temperature readout• Trigger threshold scan• Full dark count waveform sampling triggered by MPPCs

• USB based readout (slow) on four concurrent stations


TARGETX ASIC Production Testing: Pedestals and input noise

Look for shorts and unexpected pedestal offsets

Input Noise Histogram

for Single Channel

Input Noise

for Single Channel

Input noise~2.25 mVrms


TARGETX ASIC Production Testing Parameter Optimization

Enhanced Sampling Performance by Optimizing SSToutFB

All values below red line indicate that an optimized SSToutFB was chosen

Each ASIC went though parameter sweeps to optimize timing and create the best waveform sampling.


Analog front end: MPPC Bias, Trigger Scan and Temperature

27

MPPC current vs. voltage and operable region:All channels work well

Trigger threshold scan:All channels work well

Carrier Temperature


MPPC Waveform Sampling

28

Overlay plot of 76 MPPC events recorded on a single channel one TARGETX ASIC.

Indicates health of analog path all the way to through sampling


SW trigger Q and T


Full KLM barrel crate

30

• 8 RevC modules were installed in the barrel crate• Due to only one RPC crate being fully commissioned, the

data concentrators were positioned within the same RPC and VME crate for ease of access.

• Each sector (motherboard pair) is serviced by 1 data concentrator and HSLB in the e-hut.

• New RHIC framing and HV connector functionality were tested.

• Additional temporary fiber cables were routed to e-hut. Unfortunately due to lack of time and resources there were no conduits used.

• A slow control and PocketDAQ readout was performed on all sectors.

Fully populated KLM barrel crate.Ribbon cables enter from the bottom


Endcap crate

• UH crew secured the endcap racks to the rails and the floor and installed the VME crate. (Chris K.)

• Two KLM RevB readout motherboards were installed in the crate.

• FTSW and data concentrator were installed

• The scintillator ribbon cables are awaiting a jig to be manufactured.

31

Bubble wrapped endcap crate and two endcap racks on endcap door before installation


New HV patch panel and associated cabling

• KLM HV patch panel was installed

• A temporary DB25 connector was soldered to bring HV lines to the crates.

• The HV connectors on the RHIC on the crate were tested mechanically and electrically.

• Due to an unpopulated 0 Ohm resistor, this did not work in last minute. We will try again.

• The long production HV cables and breakouts were ordered by VT and should arrive at UH.

32

E-hut: HV Patch panel Crate: HV line entering the RHIC


KLM DAQ cabling plan

• Exact cable lengths were measured.

• Work in progress: coming up with a cabling plan to minimize routing while connecting the VME and RPC crates together and to the e-hut.

• These lengths will be used buy KEK to place orders for trunk fiber cables for DAQ, trigger and FTSW clocks and patch panels.


Continuing efforts

• UH, IU: Remote debugging of the sector which has both RPC and scintillator layers in order to achieve a joint RPC/Scint event readout• New slow control HV trim DAC values and trigger thresholds has been uploaded.

• UH: Gathering scintillator waveforms for analysis at IHEP

• UH: Troubleshooting the powering scheme to avoid future issues at next round of commissioning

• KEK: Installation of the endcap ribbon cables for endcap readout

• KEK: Installation of the rest of the barrel and endcap racks and crates; ordering and installation of fiber trunks and panels; providing the required FTSW and COPPER hardware;

• Next commissioning effort to populate the entire KLM scintillator readout electronics is scheduled for early October 2015. (2 weeks prior to 22nd B2GM: Oct 19-22, 2015)


Summary

• Overview of KLM scintillator readout and brief history

• HW design and production

• FW structure and development

• SW development and testing

• Production test results and CRT efforts

• Trigger and DAQ routing and interface

• Lot 1 commissioning summary

• Next steps


Acknowledgements and Q&A

• Credits: • PNNL

• KEK

• IDLAB

• IU

• VT

• Questions?


BACKUP


KEK: 200K events run, V=72.0Trig Threshold=3200

6

Next: Run more large events and scan V to calculate MPPC gain


KLM Electronics 10/30/2014

• Item Qty. assembled1) SCROD Rev A4: 52) MB Rev B: 83) TX Daughter-card Rev B: 1004) USB Daughter-card: 45) KLM RHIC (old Rev B): 10

• Note:• Items 1-3: designs updated from previous• Item 4: new design• Item 5: same board

1

2

3

4

5

4


MPPC Waveform Sampling

41

Calibration channelNot connected to MPPC

Plot of 15K MPPC events recorded on 16 channels of a single TARGETX ASIC.

Indicates health of analog path,


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