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Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
PanSTARRS Gigapixel Camera PanSTARRS Gigapixel Camera SystemSystem
Scope of Gigapixel Camera effort. WIYN telescope collaboration. OTA development status OTA test plan OTA package, focal plane and cryostat
design. OTA controller electronics design and
development.
OutlineJohn Tonry (IFA), Gerard Luppino (IFA), Peter Onaka (IFA), Barry Burke (MITLL)
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Scope of Gigapixel Camera EffortScope of Gigapixel Camera Effort
YES Maybe? NO
OTA Detectors• OTA Packages• OTA Focalplane• Camera Cryostat• OTA Controller Electronics• Camera Diagnostics• Host Image Acquisition Computers • Software for OTA operation• Software for Guiding.• Detector Calibration Info. (e.g. flats, biases, darks, linearity, etc.)
Host Computer Network Shutter Detectors for Telescope collimation and focus. Instrumental Signature Info. (fringing, scattered light, etc.) Cryostat Window
Filter Server Instrument Rotator (if Alt/Az) Telescope Control Telescope optical alignment Sky probe hardware and software Flatfield Illumination Scheduler Software Pipeline Software
Part of Detector/Camera System Scope?
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
WIYN Telescope CollaborationWIYN Telescope Collaboration
Non Binding Collaboration WIYN Developing One-Degree Imager (ODI)
• Camera System Nearly Identical to one of the PanSTARRS Gigapixel Cameras.
WIYN Contribution PanSTARRS Contribution
Develop 2nd source for OTAs• STA (Bredthauer)
WIYN Telescope time for OTA testing. Procurement of large filters. Detector testing and characterization. MONSOON controller
Lend four OTAs for WIYN/QUOTA camera Design for QUOTA camera (copy of PanSTARRS test camera). OTA package design. OTA operating software OTA controller design.
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
OutlineOutline
Overview of OTA Principal design and process
challenges• Pixel layout• Logic design, fabrication, and recent
results• Metallization and interconnects
Other OTA design issues and options• Die size and pads• Enhanced substrate E fields• Compatibility of design with CMOS option• Mini-OTA (MOTA) options
Process options and lot-1 splits Design status and summary
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Orthogonal Transfer Array Orthogonal Transfer Array (OTA)(OTA)
88 array of small OTCCDs , each ~500 500 pixels*
OTCCD cells independently clocked via on-chip control logic
Cells read out one row at a time at 1-MHz read rate; readout time ~ 2 s
Subset of cells (typically five) selectable for tracking guidestars at ~30-Hz rates
*(12 um: 480 x 496; gaps 9 x 28, 10 um: 574 x 594; gaps 11 x
35)
OTCCD cells
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
DetectorDetector Details – OverviewDetails – Overview
Each CCD cell of a 4K 4K OTA Independent ~500 500-
pixel CCDs• Individual or collective
addressing• 1 arcmin field of view
Dead cells excised, yield >50%• Bad columns confined to cells
Cells with bright stars for guiding
8 output channels per OTA • Fast readout (8 amps, 2 sec)
Disadvantage – 0.1 mm gaps, but gaps and dead cells are dithered out anyway
5 cm
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
OutlineOutline
Overview of OTA Principal design and process
challenges• Pixel layout• Logic design, fabrication, and recent
results• Metallization and interconnects
Other OTA design issues and options• Die size and pads• Enhanced substrate E fields• Compatibility of design with CMOS option• Mini-OTA (MOTA) options
Process options and lot-1 splits Design status and summary
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Principal ChallengesPrincipal Challenges
OTCCD• OTCCD yield was low until recently (lot 4)• Pixel layout appears to be critical to high yield
Control logic• Except for some preliminary test structures nMOS has
not been part of Lincoln CCD process• Design and simulation learning curve
Metallization• Extensive use of two levels of metal• New planarized metal process recently developed on
other programs; test-structure data are encouraging
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Polysilicon stackup must be minimized• High stresses may be a factor• Metallization process requires low gate profile (see
subsequent chart) OTCCD lot 4 had high yield after pixel re-design Design rules
• Max of two poly layers over channel stops• Max of three poly layers over channel regions
OTCCD Process IssuesOTCCD Process Issues
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Original pixel layout
Three-poly stacks onlyAreas of three- and four-poly stacks
Revised pixel layout
Poly PileupPoly Pileup
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
OTCCD TypesOTCCD Types
Type 1 OTCCD• Most experience with this
style: 2K 4K, 1024 1320, 512 512 (all 15-µm pixels)
• 2K 4K now has good yield (CCID-28, lot 4)
Type 2• Higher symmetry but no
obvious fabrication advantage
• Only 512 512 (15-µm pixels) made thus far
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
OTA Pixel DesignsOTA Pixel Designs
Experience to date is with 15-µm pixels
Desired pixel sizes are ≤ 12 µm• 12-µm pixel: low risk• 10 µm: moderate risk• 8 µm: high risk• Tight trade space:
Example of 10-µm pixel design
Poly3, poly4layout
Poly stackup
Minimum polylinewidth Well capacity
Poly1, poly2layout
Channelstops
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Pixel Design ChoicesPixel Design Choices
Current plan: four versions of OTA, each with different pixel layout
Two 12-µm-pixel designs as lowest risk • OTA-a: type 1• OTA-b: type 2
Two 10-µm pixel designs, both scaled from 12-µm layouts, as somewhat higher risk but closer to desired pixel size
• OTA-c: type 1 (scaled OTA-a pixel)• OTA-d: type 2 (scaled OTA-b pixel)
Pixel a Pixel b
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Logic Design ConsiderationsLogic Design Considerations
Requirements• Cells must be independently addressable• Parallel clocks for each cell can be set to one of
three states– Active (image readout, update pixel shifts, etc.)– Standby (image acquisition between updates)– Floating (shorted phases)
• Cell outputs read out one row at a time– Maximum of one cell/column read at any time
Desired• Low FET count, compact layout• Low power• Compatible with parallel shift rate > 100 kHz
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Control Logic OverviewControl Logic Overview
NMOS logic chosen• Easy to add to n-channel CCD process(+)• Power inefficient (-)
Early start on development• Oct 2002: SPICE parameter extraction from test
MOSFETs on CCID-28, lot 4• February 2003: preliminary OTA logic designs added to
SST mask set• June 2003: logic designs on SST wafers in test!
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Addressing and Control Addressing and Control Logic:Logic:
Current DesignCurrent Design
Data are latched at each cell until addressed again
Flexible operation• Cell can be clocked
with video on or off• Standby mode
during science image acquisition
• Defective parallel gates can float
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Final Control Logic DesignFinal Control Logic Design
39 FETs, 0.6–0.8 mW power dissipation
Operation with VDD=5.0 V; accepts inputs with 5-V CMOS-compatible levels
Further variants under study for inclusion as test structures
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Logic Designs on SST WafersLogic Designs on SST Wafers
Designs• Simple building-block circuits• Preliminary OTA addressing
and control logic (since modified)
• Advanced aggressive designs Important validation of design
and simulation methodologies
Original OTA logic design (61 FETs)
Closeup of circuit
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
First Test Circuit ResultsFirst Test Circuit Results
Latch circuit works for VDD= 5.0 V
Two versions (different design rules) successful
Threshold voltages somewhat higher than expected• Fix is simple
implant-dose adjustment
D
D
CLK
CLK
Q
Q
Q
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Additional NMOS Test ResultsAdditional NMOS Test Results
First version of OTA control logic works!
Design from January; uses 61 FETs
Functions with VDD=5 V
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
MetallizationMetallization
OTA uses large amount of wiring
Two levels of metal (light and dark blue)
Design rules kept deliberately relaxed• Line widths and
spacings 5 µm
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Metallization Process: Metallization Process: Planarized Dielectrics with W Planarized Dielectrics with W
PlugsPlugs Same approach as used in
current CMOS processes Process outline:
• Thick oxide deposited and planarized (CMP)
• Contact holes etched, filled with W (damascene process)
• Metal straps• Repeat for second metal
Advantages• W plugs can be narrower
and deeper than conventional contacts for AlSi
• Planar surface better for fine lithography
Shorts yield from test wafers is high
Poly stackups must be minimized to maintain poly/metal isolation Cross section from CCID-34 test wafer
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Metal Strapping ExperimentsMetal Strapping Experiments
Used existing large imager (~20 cm2) mask set and added metal straps over chanstops
Critical test (gate shorts induced by straps) showed high yield
Significant differences from standard LL CCD process• Dry-etched metal (vs. wet)• Ti/TiN/AlSi (vs. AlSi)• W plugs (new)
Metal straps
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Metallization OptionsMetallization Options
Placing digital-related lines over pixel arrays increases fill factor by 3.3%• Is this a worthwhile gain?
Process implications• Greater chance of
metal/poly shorts• More room for metal lines:
fewer metal/metal shorts• Metal lines can be wider:
faster clocking, less vulnerable to line breaks
Metal-over-pixels option requires three mask changes
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
OutlineOutline
Overview of OTA Principal design and process
challenges• Pixel layout• Logic design, fabrication, and recent
results• Metallization and interconnects
Other OTA design issues and options• Die size and pads• Enhanced substrate E fields• Compatibility of design with CMOS option• Mini-OTA (MOTA) options
Process options and lot-1 splits Design status and summary
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Die SizeDie Size
Exclusion zone > 5 mm chosen die size = 49.5 49.5 mm
Compatible with STA/Dalsa requirements
Saw kerf ≈ 70 µm sawn die size = 49.43 49.43 mm
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Pad LayoutPad Layout
Mirror symmetric pad layout: FI and BI devices use same package and I/O
Rightside
Leftside
Center
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Deep Depletion with Deep Depletion with Substrate BiasSubstrate Bias
– Chanstop and bottom substrate electrically connected: bottom substrate cannot be biased
+ Chanstop and bottom substrate electrically isolated: bottom substrate can be biased
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Advantages of Deep Advantages of Deep DepletionDepletion
Front-illuminated
– Improved high-energy x-ray response
Vsub
Back illuminated
– Increased vertical E fields tighter PSF
Vsub
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Measured Depletion DepthsMeasured Depletion Depths
Deep-depletion CCD (CCID-42)• 512512, 15-µm-pixel
frame-transfer device• Same pinouts as all
previous 5122 devices Data taken from
capacitance-voltage test structure that represents CCD layout
Depletion depths > 150 µm easily achieved
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Data from MIT/CSRX-ray Data from MIT/CSR
Si absorption length at 22 keV=1370 µm• QE depletion
depth Improved detection
of high-quality events• ~2 count
increase consistent with ~2 increase in depletion depth
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Deep DepletionDeep Depletion
Current plans• Thin four CCID-42 chips to varying thicknesses (60 –
150 µm)• Measure QE and PSF vs. thickness and substrate bias
(data relevant to Pan-STARRS)• Devices ready for test in 2 – 3 months• Backside treatment: II/LA or chemisorption charging?
OTA design can include deep-depletion option
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Why OTA/CMOS Hybrid?Why OTA/CMOS Hybrid?
Advantages• Risk reduction if monolithic OTA fails• Simplifies OTCCD processing (no NMOS, large network
of metal lines)• Pathfinder for more on-sensor processing in CMOS• Possible improvement in fill factor
Disadvantages• Additional costs: CMOS design, fab & test, bump
bonding• Adjustments to thinning process
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
OTA chip CMOS control chip
Bump bonding
Hybrid OTA/CMOS sensor
Hybrid OTAHybrid OTA
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
OTA Design for CMOS HybridOTA Design for CMOS Hybrid
Optional metal mask brings all OTA cell functions to pads for bumping
Can be done as process split (one mask change, two mask steps deleted)
Fill factor uncertain; better than baseline but maybe not as good as metal-over-pixels
Space allows double pads/function for redundancy
OTA cell
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
CMOS/OTA AttachmentCMOS/OTA Attachment
1. Attach CMOS die to OTA wafer2. Underfill with epoxy
3. Attach handle wafer (with epoxy)4. Flush-thin CCD wafer
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
OTA/CMOS Hybrid SensorOTA/CMOS Hybrid Sensor
After bonding After CCD thinning, pad-via etch,back-surface treatment
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Mini OTAsMini OTAs
MOTA is 22-cell version of OTA
Opportunity to try advanced features
• Two-phase serial register• Dual output gates• Higher performance logic
designs Useful as monitor devices
(QE, PSF, etc.) ~12 die possible Fits in conventional PGA
Tentative wafer layout
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Process Splits for Lot 1Process Splits for Lot 1
10m
Type 1
Type 1 Type 2
Type 2
12m 12m
10m
Wafers Split Options
1-4 Baseline process
5-8 CMOS
9-10 CMOS + deeper depletion
11-13 Metal over gates
14-16Metal over gates + deeper depletion
17-19Deeper depletion + higher resistivity
20-22 Deeper depletion
23-24 Look ahead
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Test Plan for OTAsTest Plan for OTAs
Device selection phase (Mar –Jun 2004)• Approximately 16 different devices
– Pixel size, CMOS logic, deeper depletion, shutter, etc.• MOTAs with more exotic choices• Serious, thorough testing necessary during a short time
which will lead to final, production OTA design choices.
Production testing (Oct 2004 – Oct 2006)• Wafer probe frontside for S/O (powered up?); excise cells?• Wafer probe backside, cold (packages are valuable)• OTA test, tune, and select• 300 OTAs need testing (20,000 CCDs!), so we need well
designed, stable test setups, software, and analysis tools.
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Design Selection PhaseDesign Selection Phase
Clocking / pixel performance• CTI• Pocket density• Cosmetics• Dark current• Image persistence• QE non-uniformity, fringing• QE• Full well• Clocking time constants• Charge diffusion• Goodies
– Electronic shutter– 2-phase serial
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Design Selection PhaseDesign Selection Phase
Amplifier performance• Read noise• 1/f knee – noise versus speed• Linearity• Amplifier / logic glow• Cross – talk: inter-cell, inter-OTA• Goodies:
– pJFET?
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Design Selection PhaseDesign Selection Phase
Package/cells• CR and radioactivity rate• Addressing• Cell excision:
– Laser/ultrasonic excision?– Tri-state logic?
• OTA metrology– Flatness– Placement of dice on package
• Epoxy squeeze-out, epoxy voids• Bond wire masking / covering of bright scatterers
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
HardwareHardware
Controller• New controllers must be thoroughly tested and understood! • Features
– Alter clocking / bias voltages– Read out full chip or arbitrary binned subarray– 1 Mpix readout at 4e- noise– Slow readout for better noise
Dewars and focal planes• 1 OTA, quick swap• 2 x 4 OTA, 2 controller: test 2x2, QUOTA/OCTOTA for sky• MOTA package / testing
Test setup• X-ray source• Monochromator / photodiode (inside dewar?)• Optical images focussed on detectors (sub pixel?)
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Testing SetupTesting Setup
Replace normal dewar window with “Snoutus Maximus”• Simultaneous x-ray stimulation from Fe55 or optical
light• Complete test sequence in one 5 hour cool-down cycle
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing – QualitativeX-ray Testing – Qualitative
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
Row
Column
Pixel Value
Row
Column
Pixel Value
Perfect CTE Bad CTE
Serial CTI
Parallel CTI
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
Slop2• Determine and subtract bias level• Generate and subtract “local sky”• Reconstruct split pixels (if requested)• Identify K-alpha pixel values as a function of (x,y)• Fit a plane
Gain derived from plane intercept at (0,0) Noise derived from overclocks CTE parallel from y slope, CTE serial from x slope Other features sometimes visible in pixel value
plots
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
Plot pixel values as a function of column (x) and row (y)
K-alpha (1620 e-) and K-beta (1780 e-) are visible
Junk on right comes from a bright defect and associated bleed column.
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
Here’s the associated histogram of pixel values.
K
K
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
Clean up split events, threshold on single x-ray events…
Define “CTE” as –log(CTI) (it’s the “number of 9’s” of
CTE) This chip loses 0.1%
across 2048 serial pixels, hence CTE_serial = 6.43.
It loses 0.3% across 4096 parallel pixels, hence CTE_parallel = 6.13
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
Here’s the associated histogram of pixel values.
Gain is 1620 e- / 1320 ADU = 1.22 e/ADU
Noise is 2.86 ADU from the overclocks = 3.48 e-. K
K
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
LHS: <SPE> = 1305 ADU RHS: <SPE> = 1261 ADU
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
This chip has a number of bright defects that I tried to minimize by cooling to –130
The chip loses 3.6% across 2048 serial pixels, hence CTI_serial = 4.77
It loses 1.5% across 4096 parallel pixels, hence CTI_parallel = 5.44
This poor behavior is because it’s at –130C, and would not be detectable optically – the trap time is so long that any edge pattern would look very sharp.
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
Gain is 1620 e- / 1320 ADU = 1.22 e/ADU
Noise is 2.46 ADU from the overclocks = 3.01 e-.
Even when the charge transfer is not working very well, it’s possible to characterize the amplifier’s performance.
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
This chip has a slight block in the serial register.
You would not see it from images, but it stands out clearly in the x-ray pixel values as a function of column.
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Optical Testing - LinearityOptical Testing - Linearity
• Conventional linearity test with variable length exposures
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing - QuantitativeX-ray Testing - Quantitative
Take a few x-ray images at different VDD, and choose the optimum VDD.
VDD which minimizes noise is usually very obvious.
If VDD is too low the noise goes way up as gain drops precipitously; if it’s too high the noise goes up and the amplifier may start glowing.
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
X-ray Testing – Charge X-ray Testing – Charge DiffusionDiffusion
• Charge diffusion will be more important in the future– Better red response
requires thicker devices– CCD cost is proportional to
area, so smaller pixels are desirable
– Diffusion is proportional to CCD thickness
• The distribution of split pixel values is sensitive to the charge diffusion, and Fe55 x-rays can provide a sensitive measure of diffusion length – 0.33 pixel = 5m in this case.
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Optical Testing - QEOptical Testing - QE
Measure about 20 points, especially where QE is changing rapidly.
Similar devices are probably very similar – don’t bother QE testing all of them.
Good opportunity to characterize fringing and other non-flatness (e.g. brick wall pattern in the blue)
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
Test Data and DatabaseTest Data and Database
Typical test data• Dark images (3 temps, 3 exposure times: 0, 100, 1000 sec)• X-ray images (4 VDD, 4 clock volts, 3 clock speeds)• Monochromator images (20 wavelength, 8 exposure time x 4
VDD)• Focussed images (8 exposure time x 4 VDD)
– Test pattern (look at resolution)– Image with structure (look for linearity)– Point sources (look for cross-talk, image persistence)– Low level uniform and pocket pumping
Detector database• 300 OTA x 100 images x 32 Mb = 1 Tb• 20,000 CCD x (Noise, gain, QE, CTI, dark, full well, linearity,
cosmetics, pocket density, diffusion, preferred biases and clock volts and timings, comments, etc, etc…)
This requires a high degree of organization and uniformity!
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
TradeoffsTradeoffs
(Read noise)2 (Read time) ~ 50 (goal) 100 (probable?) 200 (unacceptable?)
(Diffusion) / (Thickness) ~ (7-Vsub) -1/2 / 3
(QE @ 1 m) ~ 0.16 (Thickness / 40m)
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
ScheduleSchedule
Controller hardware• Component selection mid-Aug• PCBs CAD complete Oct• Flex cabling Nov• Controller prototype Dec-Jan
Controller software• Gbit ethernet tested Aug• Compact PCI throughput Aug• Centroid & shift Aug/Sep• Pixel server software Nov• OTA control development Oct-Dec
Test suite• Define tests Sep 1• Design test bench Oct 1• Define software Oct 15• Acq/fab test bench Nov 15• Test software complete Jan 1, 2004
Pan-STARRS Preliminary Requirements Review 04 Aug 03Pan-STARRS Preliminary Requirements Review 04 Aug 03
ScheduleSchedule
Cryostat• Package design Oct 1• Dewar and focal plane Nov 1• Hermetic cabling Dec 1• Packages complete Jan 1, 2004
Detectors• Layout finished Aug 15• Layout checked Sep 2• Masks ordered Sep 4• Start lot Sep 8• Frontside chips available Mar 1, 2004• CMOS addressing chips avail Mar 15, 2004• Thinned OTAs available May 15, 2004• Decision on Lot 2 design Jun 30, 2004