Partial Reconfiguration of FPGAs Part 1: Technology and ... · SRAM based FPGA • SRAM bits can be...

1

Partial Reconfiguration of FPGAsPart 1: Technology and Opportunities

Prof. Dirk StroobandtGhent University – Computer Systems Lab (CSL) Hardware and Embedded Systems (HES) group

[email protected]://hes.elis.ugent.be/dstrooba

Ghent University – Computer Systems Lab (CSL) – KHBO presentation – 27 November 2012 1

UGent – CSL – HES group

Overview• FPGAs and partial reconfiguration (PR)• Overview of PR technologies• Worldwide PR efforts• Towards industrial adoption of PR

KHBO presentation – 27 November 2012 2

• FPGAs and partial reconfiguration (PR)• Overview of PR technologies• Worldwide PR efforts• Towards industrial adoption of PR

2


Why adaptive hardware?


Design-time DSE

Single application

Fixedarchitecture

Single Pareto front

Ref [3]: D. Stroobandt and K. Bruneel, “How Parameterizable Run-time FPGA Reconfiguration can Benefit Adaptive Embedded Systems,” in Worldcomp 2011 Proceedings, 2011, pp. 184–194.




Scenario-aware Design-

time DSE

Application scenarios

Para-meterized

architecture

Pareto front per scenario

Application scenarios

Application scenariosApplication

scenarios

Dynamic mappingselection

Design-time Run-timeRef [3]: D. Stroobandt and K. Bruneel, “How Parameterizable Run-time FPGA Reconfiguration can Benefit Adaptive Embedded Systems,” in Worldcomp 2011 Proceedings, 2011, pp. 184–194.

3




Scenario-aware Design-

time DSE

Multiple architecture

instances

Pareto front per scenario and per architecture

Dynamicarchitecture and

mapping selection


instances


instances

Design-time Run-timeRef [3]: D. Stroobandt and K. Bruneel, “How Parameterizable Run-time FPGA Reconfiguration can Benefit Adaptive Embedded Systems,” in Worldcomp 2011 Proceedings, 2011, pp. 184–194.

Application scenariosApplication scenarios

Application scenariosApplication

scenarios


Classification of architectures• Three ingredients

– Fixed physical implementation of part of function– Inputs specifically targeted at changing functionality– Inputs to be manipulated by the component


Predesignedhardware

Programmable parts

chip

Controlled switches Data inputs

– Fixed physical implemen-tation of part of function

– Inputs specifically targeted at changing functionality

– Inputs to be manipulated by the component

4


FPGA: the best of both worlds


Predesignedhardware

Programmable parts

chip

Instructions Data inputs

m-processor– Functionality changed by

instructions– Software solution– Very flexible– Inherently sequential– Changes every cycle

Predesignedhardware

Programmable parts

chip

Configuration data Data inputs

FPGA– Functionality changed by

configuration bit stream– Configware solution– High perf. + adaptable– Massively parallel– Changes less frequently

Predesignedhardware

Programmable parts

chip

Data inputs

ASIC– Functionality cannot be

changed / is fixed– Hardware solution– Very high performance– Massively parallel– No change at all

Performance gap FPGA/ASIC smaller because FPGAs in leading edge process nodes


Basic FPGA structure: large matrix of many small logic elements

• Each logic element calculates 1 bit (through a configurable function)

• Interconnection between elements also configurable


LE LE

LE LE

LE LE LE LE

LE LE

LE LE

Logic Element Tracks in channel

5


Basic logic element

• Each LE has 4 (6 in Virtex-5 and up) 1-bit inputs • One single bit data output• Logic element is called LookUp Table (LUT)• Can realise each Boolean function of I inputs

functions (if I=4)KHBO presentation – 27 November 2012 9

Out = A & B & C & D

Logic Element

&ABCD

Out

KI

6422

&


SRAM based FPGA

• SRAM bits can be programmed many times

• Each programming bit requires 5 (or 6) transistors


SRAM based FPGA

Read or write

Data

Q

Q

Programming bit

interconnection

I1 I2

P1P2P3P4

Out

2-input LUT

LUT

Ref [5]: K. Compton and S. Hauck, “Reconfigurable Computing : A Survey of Systems and Software,” ACM Computing Surveys (CSUR), vol. 34, no. 2, pp. 171–210, 2002.

6


FPGA contains a wealth of configurable routing



Strong evolution in FPGAs


Source: M.A. Wahlah, “Field Programmable Gate Arrays with Hardwired Networks on Chip” Ph.D. thesis Delft University, 2012.

7


FPGA configurability


FFLUT

0

1

1

0

1

0

0

1

01 0

0 0

10

1 0

0 1

00

0

0

0

1

0

1

1

1

0


(Run-time) (re-)configuration• Configurable = hardware changed once

– Only one application / fixed at design time

• Reconfigurable = changed for each new application– Several applications / fixed at compile time

• Run-time reconfigurable (RTR) = changed during application– Several application parts / fixed at run-time– Seen as virtual hardware (cf. virtual memory)


Ref [5]: K. Compton and S. Hauck, “Reconfigurable Computing : A Survey of Systems and Software,” ACM Computing Surveys (CSUR), vol. 34, no. 2, pp. 171–210, 2002.

8


RTR benefits• Real-time flexibility in the choice of algorithms or

protocols available to application at any moment• Enables use of new techniques in design security• Improves FPGA fault tolerance• Accelerates configurable computing• Reduces bitstream storage requirements



Configuration Interface

config.DB

ConfigurationManager

ApplicationSoftware

ReconfigurationRequest

CPU

config.DBF1F2

Static

Dynamic reconfiguration

FPGA

F1F2

config.DB

DynamicF1F2

9





Two types of reconfiguration• Full reconf. (FR): halts/reconfigures entire FPGA

– Can impose significant performance overhead

• Partial reconf. (PR): halts/reconfigures portion– Mitigates FR overhead by isolating to selected parts


Central

Controlling Agent

ICAPMem controller

Module A

Module B

Module C

Static modules Reconfigurable Modules (PRMs)

PRR 1

PRR 2Static region

Static modules

Module: A & B

Modules: C & D

Module D

FPGA Fabric

Example with 2 PRRs

10


Partial reconfiguration inXilinx Virtex devices

• Frames:– Smallest unit of reconfiguration.

• Frames in Xilinx devices:– Virtex, Virtex II, Virtex II-Pro:

• The whole column.– Virtex 4, Virtex 5, …

• Only a complete tile• Different in various devices:

– Virtex-6: 40 CLBs x 1 CLB– Virtex-5: 20 CLBs x 1 CLB– Virtex-4: 16 CLBs x 1 CLB


Width

Height

TASK 2

Logical shared memory

TASK 1CLB


Two methods ofdelivering partial bit file


D. Dye, “Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite,” Xilinx white paper Virtex-4, Virtex-5, Virtex-6, and 7 Series FPGAs, WP374 (v1.2) May 30, 2012

11


Internal configurationaccess port (ICAP)

• Port to read and write the FPGA configuration at run time

• Enables a user to write software programs for an embedded processor that modifies the circuit structure and functionality during the circuit’s operation

• Allows for automated runtime reconfiguration



Dynamic reconfiguration port• Each functional block (except I/Os) has a dynamic

reconfiguration port– It is directly accessible from the FPGA logic.

Configuration bits can be written to and/or read from depending on their function.

– Each bit of memory is initialized with the value of the corresponding configuration memory bit in the bitstream. Memory bits can also be changed later through the ICAP (ICAPE2).

– The output of each memory bit drives the functional block logic, so the content of this memory determines the configuration of the functional block.


12


Dynamic reconfiguration port


Source: Xilinx 7 Series FPGAs Configuration User Guide, UG470 (v1.5) November 5, 2012


Configuration modes• Xilinx 7 series has 5 configuration modes

– Serial• FPGA is configured by loading one configuration bit per CCLK cycle.

– Serial Peripheral Interface (SPI)• enables use of low pin-count SPI flash for bitstream storage• direct connection to four-pin SPI flash for reading a stored bitstream

– Byte Peripheral Interface (BPI)• enables use of parallel NOR (BPI) flash for bitstream storage• direct connection to address, data, and control signals of a BPI flash

– SelectMAP• 8-, 16-, or 32-bit bidirectional data bus interface for configuration and

readback– JTAG

• four-pin JTAG interface to configure FPGA using Xilinx software, directly from a processor, or using third-party boundary-scan tools


13


Partial reconfiguration inXilinx Virtex devices

• Module-based PR:– Implement any single component separately.– Constrain components to be placed at a given location.– Complete bitstream is finally built as the sum of all partial

bitstreams.• Difference-based PR:

– Implement the complete bitstreams separately.– Implement fixed parts + reconfigurable parts with

components constrained at the same location in all the bitstreams.

– Compute the difference of two bitstreams to obtain the partial bitstream needed to move from one configuration to the next one.



Module-based PR• Initially developed to allow several engineers

to cooperatively work on the same project.• Procedure:

– Project leader• Identifies the components of the whole project,• Estimates the amount of resources consumed by each

component, • Defines locations for the components on the device

– Engineers• Develop the single parts independently.


14


Module-based PR



Module-based PR• Bus Macros guarantee fixed communication

channels among RMs and the fixed part– One must ensure that signals will not be routed on

the wrong paths after the reconfiguration.– Routing resources for such inter-module signals

must not change when a module is reconfigured.


15


Bus macro• Bus macro:

– HDL code should ensure any reconfigurable module signal used to communicate with another module does so only by first passing through a bus macro.

– Each macro: 4-bits of inter-module communication• if A communicates via 32 bits to B, then eight (32/4) bus

macros will need to be instantiated.



Bus macro


16

UGent – CSL – HES group 31


Constraints of modular method• The size and the position of a module cannot

be changed.• Input-output blocks (IOBs) are exclusively

accessible by contiguous modules.• Reconfigurable modules can communicate

only with neighbor modules, and it must be done through bus macros.

• No global signals are allowed (e.g., global reset), with the exception of clocks that use a different bitstream and routing channels.


17


Difference-basedpartial reconfiguration

• Small changes on the FPGA configuration• Manually done using the FPGA Editor• What can be modified?

– LUTs equations– BRAM contents and BRAM write modes– I/O standards and pull-ups or pull-downs on external

pins– MUXes that invert polarity,– Flipflop initialization and reset values,

• What cannot be modified?– Routing – very dangerous: internal contentions.



Problems withdifference-based method

• Lack of automation – changes must be done manually

• In complex designs it is difficult to find the component you want to modify

• Xilinx current support is mostly for modular based method.


18


The new way – a little easier1. Synthesize base system with reconfigurable

module with input and output pins (XPS)2. Create software files to manage PR Region

(SDK)3. Use Plan Ahead to manage PR Region and

create bit-streams (Lots of steps here)4. Merge bit-streams into download.bit to run

on the FPGA



Altera: similar reconfigurationschemes for Stratix V devices

• Fast passive parallel (FPP) (×8, ×16, and ×32)• Active serial (AS) (×1 and ×4)• Passive serial (PS)• JTAG

• PR made easier using the Quartus incrementalcompilation flow

• Available information still very basic


19


Special use of reconfiguration:Tabula Spacetime architecture


From FPGA to 3PLD

Source: S. Teig, “Going beyond the FPGA with Spacetime” presentation at FPL 2012.


Tabula Spacetimearchitecture is 3D


From FPGA to 3PLD

Source: S. Teig, “Going beyond the FPGA with Spacetime” presentation at FPL 2012.

20


Implementing the thirddimension in Spacetime

KHBO presentation – 27 November 2012 39Source: S. Teig, “Going beyond the FPGA with Spacetime” presentation at FPL 2012.


Spacetime memories


21


Spacetime memories• 2 GHz throughput (faster than most ASICs)• 12 different pieces of logic can be adjacent to

the same memory!– Very low latency

• DSPs can be fed at 2 GHz– DSPs can run at 2 GHz in practice



Spacetime Geometry• Spacetime geometry is Minkowski

– Not Euclidean or Manhattan– Component sinks must be in its light cone


22


Spacetime Geometry





23


PR system from KIT


M. Huebner, T. Becker, and J. Becker, “Real-Time LUT-Based Network Topologies for Dynamicand Partial FPGA Self-Reconfiguration,” in 2004 SBCCI’04, September 7–11, 2004, Pernambuco, Brazil, 2004, pp. 28–32.


Erlangen Slot Machine


Main application for the ESM are video processing applications. Using partial run-time reconfiguration the video processing

kernels can be exchanged without disturbance of the whole video processing

system.

http://www12.informatik.uni-erlangen.de/esmwiki/

24


Glitchless modular dynamicreconfiguration

• Uses “glitchless dynamic reconfiguration” toreconfigure regions cutting through frames– In Virtex-II/pro not for LUT

RAMs and SRLs (in Virtex-4everywhere)

• Allocates 100% of long linesand 20% of the hex lineswithin module regionsto statically routed signals


P. Sedcole, B. Blodget, T. Becker, J. Anderson and P. Lysaght, “Modular dynamic reconfiguration in VirtexFPGAs,” in IEE Proc.-Computers and Digital Techniques, Vol. 153, No. 3, 2006, pp. 157–164.


Virtual Configurations


M. Liuzy, Z. Luy, W. Kuehnz, and A Jantsch, “Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations,” in ReCoSoC 2010.

25


Other important aspects• Estimation of the benefits of using PR for

applications without full PR implementation– Ref [1] K. Papadimitriou, A. Dollas, and S. Hauck,

“Performance of Partial Reconfiguration in FPGA Systems : A Survey and a Cost Model,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 4, no. 4, 2011.

• Verification of PR designs– Ref [2] L. Gong and O. Diessel, “ReSim: A reusable

library for RTL simulation of dynamic partial reconfiguration,” in 2011 International Conference on Field-Programmable Technology, 2011, pp. 1–8.



Other important aspects• Relocation of bitstreams to different regions

– T. Becker, W. Luk, and P.Y.K. Cheung, “Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration,” FCCM 2007, pp. 35-44


26


Design Methodologies• PR design flow


C. Conger, A. Gordon-Ross, and A.D. George, “Design Framework for Partial Run-Time FPGA Reconfiguration,” in ERSA 2008.

Special-purpose systems Multi-purpose systems


GoAhead• Powerful for implementing partially reconfigurable systems• Supports basically all recent Xilinx FPGAs• Has some distinct features that are not available in the PR

tool chain provided by Xilinx including:– Decoupling of partial modules from the static design (partial

modules and the static design can be implemented completely independent to each other)

– Module relocation and multi-module instantiations – Module integration without logic overhead (no bus macro or

proxy logic required) – Hierarchical reconfiguration (a PR module inside a PR module) – Communication architecture generation for hosting multiple PR

modules simultaneously in the same PR region


Ref [4]: C. Beckhoff, D. Koch, and J. Torresen, “GoAhead : A Partial Reconfiguration Framework,” in 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012, 29 April - 1 May 2012, Toronto, Ontario, Canada, 2012, pp. 37–44.

27


GoAhead GUI



GoAhead flow


28


Few industrial examples• Software defined radio implementation using

PR– Eric J. McDonald, The Aerospace Corporation– IEEE A&E Systms Magazine, July 2008, pp. 10-15

• Communication and consumer applications are mentioned but hard to find examples





29


PR industrial adoption?• RTR and PR have been applied by several

research groups at universities but not (much) in industry

• Main problems– No tool flow for run-time reconfiguration frontend– Too many low-level device details to take into

account at the backend• Recent FP7 project FASTER: Facilitating

Analysis and Synthesis: Technologies forEffective Reconfiguration



Who is in FASTER?


FORTH-ICS (FOR) - Coordinator

Chalmers University of Technology (CHT)

Imperial College London (IMP)

Politecnico to Milano (PDM)

Ghent University (GNT)

Maxeler Technologies (MAX)

STMicroelectronics (STM)

Synelixis Solutions LTD (SYN)

30


Motivation: Challenges• Creating reconfigurable systems is hard!• The designer has to:

– Identify portions to be reconfigured– Establish a schedule that

• (a) respects dependencies • (b) achieves performance and other constraints

– Manage the system resources (reconfiguration area)– Be wise: reconfiguration cost is substantial– Verify a changing system!

• Tool support for these tasks is esoteric to say the least• Resource management is up to the user• Verification: any support today?



FASTER Goals & Innovation• Include reconfigurability as an explicit design

concept in computing systems design, along with methods and tools that support run-time reconfiguration in the entire design methodology

• Provide a framework for analysis, synthesis and verification of a reconfigurable system

• Provide efficient and transparent runtime support for partial and dynamic reconfiguration, including micro-reconfiguration

• Demonstrate usability & performance with commercial applications (ΜΑΧ, STM, SΥΝ)


31


FASTER Vision



FASTER Proposed Flow


32


FASTER Expected Impact• Cost reduction in terms of product

development and maintainability cost, as well as reduced total cost of ownership (TCO)

• New products enabled by the considerably shorter time-to-market and product adaptability

• Support the specification of parallelism in the input (tools for analysis, etc.)

• Performance and power consumptionimprovements (overall system)



Demonstration and Use• Address three domains: HPC, Desktop, Embedded• Identified corresponding complex applications:

– (a) Reverse Time Migration (RTM), a computational seismography algorithm (MAX, HPC)

– (b) Global Illumination (STM, Desktop)– (c) a Network Intrusion Detection System (SYN, Embedded)

• Basic Metrics: speed, cost, and power consumption

• Evaluate the FASTER tool flow on designer productivity in the design and verification process


33


High-level Analysis &Reconfigurable System Definition


High-level analysisEstimation of metrics (power, speed, area)

App task profiling + Identification of

reconfigurable cores

Optimization of app for micro-reconfiguration

Off-line schedulingand mapping into

reconfigurable regions

PlatformArchitecture

App Task GraphPerformance

Characteristics


Verification flow


Source

Equivalent?Equivalent Not equivalent,counter-example

Checker

Symbolic simulator

Compiler

TargetTransformations

Symbolic input

Output(from source)

Output(from target)

Source Target

Yes No

Compile to simulation

Designoptimization

Symbolic simulation

ValidationSource Target

34


Run-time System• Provide support for partial & dynamic reconfiguration

– Extend the OS capabilities, integrate in existing systems– Efficient on-line scheduling and placement of task modules

• Evaluate reconfiguration overhead• Propose advanced mechanisms to support

– Scheduling – Relocation– Fragmentation = f(relocation, scheduling)– Area allocation

• Bottom-line: extend the flexibility of run-time support



Expected Results & ConclusionsFASTER is a focused project that builds on combined partner expertise as well as on past research work & projects

We focus on (and hope to demonstrate):• productivity improvement in implementation and

verification of dynamically changing systems• total ownership cost reduction (NIDS and RTM

systems)• performance improvement under power constraints

for Global Illumination and Image Analysis application

http://fp7-faster.eu/


35


Can we do even more?• Today: configurability on a large time scale

– Prototyping– System update– ...

• UGent: configurability on a smaller time scale– Dynamic circuit specialization

• Frequently changing (regular) inputs vs. infrequently changing parameters

• Parameters trigger a reconfiguration (through configuration manager)

– Goals:• Improve performance• Reduce area• Minimize design effort

• See part 2 by Karel Bruneel after the break!KHBO presentation – 27 November 2012 69

Date post:	08-Apr-2020
Category:	Documents
Upload:	others
View:	12 times
Download:	0 times

Partial Reconfiguration of FPGAs Part 1: Technology and ... · SRAM based FPGA • SRAM bits can be...

Documents