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8/2/2019 PCI Basics
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PCIPCI
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PCI 2
Typical System ImplementationTypical System Implementation
CPU Cache Memory
Subsystem
DRAM Subsystem PCI Bridge/MemoryController
Host Bus
PCI Local Bus
PCI Add-in Slots
ISA BusBridge ISA Add-in Slots
ISA Bus
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PCI 3
Desktop PlatformsDesktop Platforms
Exp Bus
Xface
Exp Bus
XfaceIDE
IDE
Processor
Processor
Bridge/
Memory
Controller
Bridge/
Memory
Controller DRAM
DRAM
LAN, SCSI,
Video, etc
Graphics
Graphics
PCI Local Bus
ISA/EISA - MicroChannel
Cache
Cache
Add-in
Fax
Modem
R
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PCI 4
Server PlatformsServer Platforms
Expansion
Bus Bridge
Host Bridge
System Bus
Processor/Cache Processor/Cache MemoryControllerMemory
Host Bridge
PCI to PCI
Bridge
LAN LANSCSI
Conn 1 Conn 4
PCI Local Bus 32/64-Bit PCI Local Bus
Expansion
Bus Bridge
LAN FAX
PCI Local Bus
Bridg
e
I/O
SCSI
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PCI 5
Mobile PlatformsMobile Platforms
IDEIDE
ProcessorProcessor
Bridge/
Memory
Controller
Bridge/
Memory
Controller DRAMDRAM Graphics
Graphics
PCI Local Bus
CacheCache
BridgeBridge
I/O Bus Sockets
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PCI 6
PCI AutoPCI Auto--ConfigurationConfiguration
+PCI AddPCI Add--in Cardin Card
PCI Based MotherPCI Based Mother
BoardBoard Auto ConfigurationAuto ConfigurationSystemSystem
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PCI 7
PCI OverviewPCI Overview
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PCI 8
PCI FeaturesPCI Features
l 32-Bit or 64-Bit address and data
l 66 or 33 down to 0 MHz synchronousoperation
l Single or multiple bus masters
lReflected bus signalingl Stepped signaling
l
Bus parity error reportingl 5 or 3.3 volt operation
lCache support
l JTAG testing
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PCI 9
PCI BusPCI Bus
l Bus Signals
l Bus Commands
l Bus Transactionsl Arbitration
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PCI 10
PCI Bus SignalsPCI Bus Signals
RST
CLK
GNT#
REQ#
IDSEL
DEVSEL#
STOP#IRDY#
TRDY#
FRAME#
PAR
C/BE#[3::0]
AD[31::00]
TMS
TCK
SDONE
SBO#
LOCK#
REQ64#
ACK64#
PAR64
C/BE#[7::4]
AD[63::32]
TDO
TDI
TRST#
PCI Pin List
Required Pins Optional Pins
PCICOMPLIANT
DEVICE
64-BitExtension
InterfaceControl
CacheSupport
JTAG(IEEE 1149.1)
Address
& Data
InterfaceControl
Arbitration(masters only)
System
SERR#
PERR#ErrorReporting
Interrupt A-D#
Present 1-2
Clkrun#
M66EN
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PCI 11
PCI Bus Control SignalsPCI Bus Control Signals
l
System CLK
RST#
l Address Data
AD[31:00]
C/BE[3:0]#
PAR
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PCI 12
PCI Bus Control SignalsPCI Bus Control Signals
l
Interface Control FRAME# - LOCK#
IRDY# - IDSEL#
TRDY# - DEVSEL# STOP#
l Arbitration
REQ#
GNT#
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PCI 13
PCI bus accessPCI bus access
l PCI is a Multimaster Bus
l All transactions initiatedby a
master
l All transactions to/from a target
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PCI 14
PCI Bus Control SignalsPCI Bus Control Signals
l FRAME#
driven by master to indicate transfer start and
end
l IRDY# driven by master to indicate it is ready to
transfer data
l TRDY# driven by master to indicate it is ready to
transfer data
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PCI 15
Bus transaction start
Address
42 31 5 6 7 8CLK
9
FRAME#
AD
C/BE# Command
IRDY#
GNT#
Bus Idle
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PCI 16
PCI Command DefinitionPCI Command Definition
C/BE [3::0]# Command Type
0000 Interrupt acknowledge
0001 Special Cycle
0010 I/O Read
0011 I/O Write
0110 Memory Read
0111 Memory Write
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple1101 Dual Address Cycle
1110 Memory Read Line
1111 Memory Write and Invalidate
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PCI 17
PCI CommandsPCI Commands
The PCI bus commands, encoded on the C/BE[3::0]# lines, aresummarized below:
Interrupt Acknowledge (0000)
Performs a read implicitly addressed to the system interruptcontroller
Address bits are logical dont cares during the addressphase
Byte enables indicate the size of the vector to be returned
Special Cycle (0001)
Provides a simple message broadcast mechanism on thePCI bus
Logical equivalent of a wire to all agents
Alternative to physical signals during sidebandcommunications
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PCI 18
PCI Commands (Cont.)PCI Commands (Cont.)
I/O Read (0010)
Reads data from an agent mapped in I/O address space
Byte enables indicate the size of the transfer and must be
consistent with the byte address I/O Write (0011)
Writes data to an agent mapped in I/O address space
Byte enables indicate the size of the transfer and must be
consistent with the byte address Reserved (0100, 0101, 1000, 1001)
Reserved for future use
Memory Read (0110)
Reads data from an agent mapped in memory address space
Target can do anticipatory read if no side effects can beguaranteed (Prefetchable Memory)
Target must ensure coherency of data in temporary buffers after
this transaction
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PCI 19
PCI Commands (Cont.)PCI Commands (Cont.)
l Memory Write (0111)
Writes data to an agent mapped in memory addressspace
Target assumes responsibility for coherency of data
l Configuration Read (1010)
Reads the configuration space of each agentl Configuration Write (1011)
Transfers data to the configuration space of each agent
l Memory Read Multiple (1100)
Fetches a full cache line and starts fetching the next
Differs from Memory Read by the intent to fetch morethan one cache line before disconnecting
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PCI 20
PCI Commands (Cont.)PCI Commands (Cont.)
l Dual Address Cycle (1101)
Generates two 32-bit address cycles to produce one 64-bit address
l Memory Read Line (1110)
Reads up to the cacheline boundary
Differs from Memory Read by the intent to complete a fullcacheline read
l Memory Write and Invalidate (1111)
Transfers a complete cacheline to memory, theninvalidates the line in cache (Writeback & HITM#)
Differs from Memory Write by its guarantee of a minimumtransfer of one complete cacheline
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PCI 21
Memory AccessMemory Access
l Reads
Memory Read 0110
burst of less than a cache line
Memory Read Line 1110
burst of cache line
Memory Read Multiple 1100
l
Writes Memory Write 0111
Memory Write & Invalidate 1111
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PCI 22
Bus Read
BusCmd
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL
#
Data 2 Data 3
wait
wait
Datatransfer
Datatransfer
Address
wait
42 31 5 6 7 8CLK
9
Data 1
BE#s
Datatransfer
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PCI 23
PCI Bus ReadPCI Bus Read
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
ADDRESS DATA-1 DATA-2 DATA-3
BE#SBUS CMD
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PCI 24
PCI Bus WritePCI Bus Write
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PCI 25
Premature TerminationPremature Termination
l Master Abort
No DEVSEL from any target
l Disconnect
Target cant continue burst, stop after currenttransfer
l Retry
Target cant complete current cycle, retry laterl Abort
Target has fatal error, dont retry
M Ab
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PCI 26
Master Abort
Address
42 31 5 6 7 8CLK
9
Bus Cmd
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL
#
Fast
Medium
Slow
Bridg
e
Di t
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PCI 27
Disconnect
Data
wait
42 31 5 6 7
CLK
FRAME#
AD
IRDY#
TRDY#
DEVSEL
#
Data
Datatransfer
STOP#
Datatransfer
TRDY - True, Stop - True, Devsel - True
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PCI 28
Retry
42 31 5 6 7
CLK
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
TRDY - False, Stop - True, Devsel - True
T t Ab t
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PCI 29
Target Abort
42 31 5 6 7
IRDY#
CLK
FRAME#
TRDY#
STOP#
DEVSEL#
TRDY - False, - True, De sel - FalseStop v
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PCI ArbitrationPCI Arbitration
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PCI 31
PCI Bus ArbitrationPCI Bus Arbitration
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PCI 32
ArbitrationArbitration
lArbitration is access based
Master must arbitrate for each busaccess
l
Central arbitration scheme Each master has a unique request
and grant signal
lArbitration is hidden
Occurs during previous bus cycle
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PCI 33
Arbitration SchemeArbitration Scheme
lAn arbiter may implement any
scheme which is fair Fairness means that, in general, the
the arbiter must advance to a newagent when the current master
releases the bus
Each potential master must begranted access to the bus
independently of other requests
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PCI 34
Bus ParkingBus Parking
l
Parking permits the arbiter to selectan agent, by asserting its GNT#,when no other agent is using or
requesting the busl The arbiter determines how this
selection is made Fixed, Last Used, , or None
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Delayed TransactionsDelayed Transactions
D l d T tiD l d T ti
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PCI 36
Delayed TransactionsDelayed Transactions
l Used by two types of devices:
I/O Controllers
Single delayed transaction in general
Bridges Particularly PCI-to-PCI bridges
Multiple delayed transactions in
general
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PCI 37
CPU MEM
Local Bus
ATU
PCI Bus
D l d T tiD l d T ti
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PCI 38
Delayed TransactionsDelayed Transactions
l Master issues read
l Slave latches date
l Slave terminates with retry
l Slave transfers data from memoryto buffer
l
Master issues repeat readl Slave terminates with TRDY
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LatencyLatency
LatencyLatency
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PCI 40
LatencyLatency
l
Arbitration latency Bus acquisition latency
l Master data latency
l Target latency
Initial
Subsequent
Bus Access LatencyBus Access Latency
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PCI 41
Bus Access LatencyBus Access Latency
l
Number of clocks from the assertionof REQ# to the completion of thefirst data transaction
Sum of: Arbitration Latency
Bus Acquisition Latency
Master Latency
Target Latency
LatencyLatency
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PCI 42
LatencyLatency
Master assertsREQ#
Master receivesGNT#
Master assertsFRAME#
Target assertsTRDY#
ArbitrationLatency
AcquisitionLatency
TargetLatency
Latency TimerLatency Timer
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PCI 43
Latency TimerLatency Timer
l Latency Timer (LT) controls trade-offbetween high throughput and lowlatency
l Latency Timer counter sets minimumnumber of clocks before the mastermust surrender GNT#
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PCI HardwarePCI Hardware
PCI Card ConnectorsPCI Card Connectors
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PCI 45
PCI Card ConnectorsPCI Card Connectors
5V 32-Bit Connector
5V 64-Bit Connector
3.3V 32-Bit Connector
3.3V 64-Bit Connector
Keyway
33 MHz
33/66 MHz
Rear Front
5 V To 3 3 V Migration Path5 V To 3 3 V Migration Path
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PCI 46
5 V To 3.3 V Migration Path5 V To 3.3 V Migration Path
5 Volt Card 3 Volt Card Dual-Voltage Card
Key near backpanel Key away from
3 Volt
System
5 Volt
System backpanel
PCI Component Pin OutPCI Component Pin Out
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PCI 47
PCI Component Pin OutPCI Component Pin Out
Trace LengthTrace Length
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PCI 48
Trace LengthTrace Length
Less than 1.5" Trace Length
PCI Component Bus LoadingPCI Component Bus Loading
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PCI 49
PCI Component Bus LoadingPCI Component Bus Loading
PCI
< 2nS
DevicePCIDriver
Clock
Device
HIGHLOW
V_ih
V_test
Driving PCI
T_prop
V_il
T_prop
V_test
V_test 5v = 1.5 vV_test 3v = 0.4 Vcc
Driving 50pF
Test Load
PCI Load DefinitionPCI Load Definition
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PCI 50
PCI Load DefinitionPCI Load Definition
l Tprop = 10ns @33MHz, 5ns @ 66MHz
l
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PCI 51
PCI Load RestrictionsPCI Load Restrictions
It is specifically a violation of the PCI specification to:
l Attach an expansion ROM directly, or via bus transceivers, on
any PCI pins ROM code may not execute in-place
l Attach two or more PCI devices on an expansion board exceptbehind a PCI component
l Attach any logic, other than a single PCI device, which snoopsPCI pins
l Use PCI component sets which place more than one load onany PCI pin,
Separate address and data path components
l Use a PCI component which has more than 10pF per pin
l Attach any pull-up resistors, or other discrete devices, to PCIsignals except behind PCI component
66MHz Operation66MHz Operation
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PCI 52
66MHz Operation66MHz Operation
l PCI operates at 66 MHz only in the 3.3V
environmentl Agents indicate 66MHz capability both
electrically and programmatically
M66EN pin 66M bit in status register
l Any 33MHz board on the bus grounds
the M66EN pin and disables 66 MHzoperation
Pin B49 grounded indicates 33MHz
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PCI ConfigurationPCI Configuration
System InitializationSystem Initialization
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PCI 54
yy
l Configuration allows software (BIOS) to
initialize the systeml Each device has configuration registers
l At power up software scans bus(es)
l Software analyses system
requirements
l Configuration registers are set toconfigure individual devices
Configuration TypesConfiguration Types
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PCI 55
g ypg yp
l Specific bus commands
configuration read (C/BE# = 1010)
configuration write (C/BE# = 1011)
l Type 0
local PCI bus
IDSEL line indicates device
address field indicates register
l
Type 1 remote PCI bus (through bridge)
address field indicates bus, device and register
Configuration Space HeaderConfiguration Space Header
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PCI 56
Device ID Vendor ID
CommandStatus
Class Code Rev
Cache Line SizeLatency TimerHeader TypeBIST
Base Address 0
Base Address 1
Base Address 2
Base Address 3
Base Address 4
Base Address 5
Cardbus CIS Pointer
Subsystem Vendor IDSubsystem ID
Expansion ROM Base Address
Reserved
Reserved
Interrupt LineInterrupt PinMin_GntMax_Lat
00
04
08
0C10
14
18
1C
20
24
28
2C
3034
38
3C
Command RegisterCommand Register
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PCI 57
Bit Meaning0 I/O Space Enable1 Memory Space Enable2 Bus Master Enable3 Special Cycle Enable
4 Memory Write and Invalidate Enable5 VGA Palette Snoop Enable6 Parity Error Enable7 Wait Cycle Control
8 SERR# Enable9 Fast Back to Back Enable10:15 Reserved
IDSEL Line AddressingIDSEL Line Addressing
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PCI 58
gg
lAddressing the Configuration Space of a device
is done using the IDSEL signal as a chip select,and setting AD[1::0] to 00 to indicate a Type 0
configuration transaction
l The method used to generate IDSEL is system
specific, however, if no other mapping is
required the following may be used
l The IDSEL of Device 0 is connected to AD[16],
Device 1 is connected to AD[17], etc. through
Device 16 connected to AD[31]
Interrupt LineInterrupt Line
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PCI 59
p
l 8-Bit register which contains interrupt line
routingl Value in this register is the interrupt number
(IRQ) to which the devices interrupt pin is
connectedl If, during initialization, the device requests
an IRQ, one is assigned.
The IRQ number is placed in this register byconfiguration software at initialization time
Interrupt PinInterrupt Pin
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PCI 60
l The interrupt pin register indicates which of thefour interrupts, INTA#-INTD#, the device orfunction uses
lA value of 1 corresponds to INTA#, 2 to INTB# etc
l Devices which do not use interrupts place 0 in thisregister
l This register is read only
l Each function within a device may use oneinterrupt
A single function device must use INTA# If a multifunction device requires two interrupts
they must be INTA# and INTB# etc.
l Interrupts may be shared (chained)
Interrupt RoutingInterrupt Routing
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PCI 61
A
B
C
D
A
B
C
D
A
B
C
D
Route 0
Route 1
Route 2
Route 3
IRQ5
IRQ9
IRQ10
IRQ11
IRQ12
I
RQ
Router
Slot1
Slot2
Slot3
PCI Bus InterruptsPCI Bus Interrupts
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PCI 62
Router
MIN_GNT and MAX_LATMIN_GNT and MAX_LAT
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PCI 63
l Minimum Grant and Maximum Latency
l MIN_GNT defines the burst-period length
required by the device
l MAX_LAT specifies how often the device must
gain access to the PCI bus
Maximum time between accesses
l Both registers are read only and have a
granularity of 250 nanoseconds
l Values of 0 in these registers indicates no major
latency requirements for the device
DocumentationDocumentation
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PCI 64
l PCI Local bus Specification Rev 2.1
PCI Special Interest Group http://www.pcisig.com/
l PCI System Architecture, 3rd Edition
Mindshare
ISBN# 0-201-40993-3
l PCI Hardware & Software Architecture and
Design
Edward Solari & George Willse