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Challenges in the RF Design of highly Challenges in the RF Design of highly integrated Direct Conversion Receivers for integrated Direct Conversion Receivers for
multi-band multi-standard applicationsmulti-band multi-standard applications
Laboratorio di MicroelettronicaLaboratorio di Microelettronica
Università degli Studi di Pavia, ItalyUniversità degli Studi di Pavia, Italy
Francesco SveltoFrancesco Svelto
Injection Locked dividers for Quadrature Generation in Direct Conversion Receivers
This Talk
A CMOS Direct Downconverter with +78dBm Minimum IIP2 for 3G Cell-Phones
A 750mV 15KHz 1/f Noise Corner 51 dBm IIP2 Direct Conversion Front-End for GSM in 90nm CMOS
LNA
IC
0°
90°
Mixer
Mixer
VGA
VGA
VCO
Quad.Gen.
A 0.13 m CMOS Front-End for DCS1800/UMTS/802.11b-g
This Talk
LNA
IC
0°
90°
Mixer
Mixer
VGA
VGA
VCO
Quad.Gen.
An Interference Robust 0.18m CMOS 3.1-8GHz UWB Receiver Front-End
This Talk
A Variable Gain RF Front-End for Multistandard WLANs Applications
LNA
IC
0°
90°
Mixer
Mixer
VGA
VGA
VCO
Quad.Gen.
A CMOS Direct Downconverter A CMOS Direct Downconverter
with +78dBm Minimum IIP2 with +78dBm Minimum IIP2
for 3G Cell-Phonesfor 3G Cell-Phones
International Solid-State Circuits Conference, Feb. 2005International Solid-State Circuits Conference, Feb. 2005
• TX signal leakage sets challenging RX IIP2 (>+50dBm)
• Expensive external SAW filter alleviates IIP2 and IIP3 specs
State-of-the-Art “Hybrid” Zero-IF UMTS RX
Goal: fully integrated solution
LOLO
IC
ExternalSAW
LNA1 LNA2I
Q
Mechanisms of 2nd Order Intermodulation
Counter-measures:
RF-LO coupling
Orthogonal RF and LO
paths
Mismatch in load resistors
Fully differential V-I converter (IIP2CM ~ +40dBm)
and 0.1% load resistors mismatch
IIP2 > +100dBm!
V-I converter
AC coupling
RF+ RF-
LO-
Common mode todifferential conversion
Low frequencyIM2 generation
LO+ LO+
• Very high IIP2 (>+90dBm)
at low frequency
• Dramatic drop at radio
frequency
2nd Order Distortion in Switching Pairs
Parasitic capacitor at source
nodes plays a key role
RF+ RF-
LO-
2nd orderintermodulation
LO+ LO+
Switching Pair Equivalent Model
VS - FrequencyVS - Time
LO+
Ibias
Cpar
Voff LO-VS
Ibias
Voff
0
1/fLO
VS
Cpar
t0
Voff
1/fLO = Cpar/gm
ffLO 3fLO
IM2 Due to LO odd-harmonics
Ibias+ IIM
Voff
0
1/fLO
VS
IIM2
Cpar
Source voltage VS
ffLO 3fLO
Tailcurrent
fDC
Ibias IIM
fIM
Capacitor current down-converted by device commutation
IM2 sidebands
Tailcurrent
Source voltage VS
IM2 sidebands
fDC
Ibias IIM
fIM
2fLO 4fLO
Gain at even LO harmonics due to duty-cycle distortion
IM2 due to LO even-harmonics
LO+
Cpar
Voff
LO-VS
IIM2
Ibias+ IIM
fLO
IM2 contributions from harmonics
Power of down-converted side-bands around
fundamental at least 17dB higher
-190
-180
-170
-160
-150
-140
-130
-120
1 2 3 4 5 6
LO harmonic
Out
put I
M2
[dBm
]
21dB 17dB
W/L=200/0.3 m/mI=2mA
Suppressing IM2 due to Switching Pairs
• LSW is chosen with
same impedance
magnitude as Cpar
at LO frequency
• CFAT drains IM2
currents flowing
through LSW
LO+
LO-LSW LSW
CFAT
cpar cpar
IM2 path
LO+
IM2 path
IM2 contributions with LC filter
High order harmonics are almost unchanged
-190
-180
-170
-160
-150
-140
-130
-120
1 2 3 4 5 6
LO harmonic
Out
put I
M2
[dBm
]
Intrinsic behavior
With proposed LC filter
25dBattenuation
V-I Converter
RC degeneration leads to high IIP2 and high IIP3
RF+ RF-iRF+ iRF-
Mdeg MdegCdeg Cdeg
Frequency [Hz]100k 1M 10M 100M 1G 10G
Tran
scon
duct
ance
[dB]
Example-30
-40
-50
-60
-70
-80
• AC Coupling tranconductor and switching pair is a solution,
but price is consumption
• Fully differential for high IIP2, Pseudo-differential for high IIP3
V-I Converter: IIP2
Low gain at low frequency
improves IIP2RF+ RF-
Mdeg MdegCdeg Cdeg
2025303540455055606570
0 1 2 3 4 5 6 7 8 9 10
Biasing Current [mA]
IIP2CM
[dBm
]
Theory
Simulation
mCM2
2GIIV2=
G
2,rfCM
2
m,rf ds,deg
gG =
2 1+g r
V-I Converter: IIP3
Cdeg provides low impedance at
signal frequency high IIP3
RF+ RF-
Mdeg MdegCdeg Cdeg
2
4
6
8
10
12
14
16
18
1 2 3 4 5 6 7 8 9 10Biasing Current [mA]
IIP3
[dBm
]
RC deg.: theoryRC deg.: simulationFully diff.: simulation
22,rf ds,deg3,rfDIFF
3
m,rf ds,deg
g rgG = +
4 3 1+g r
mDIFF3
4GIIV3=
3 G
Downconverter Schematic
• Differential load resistors
save voltage room
• Common-mode feedback
sets DC output voltage
• 4mA from 1.8V supply
RF+ RF-
912/1.13.3pF
LO+
LO-5.5nH
15pF
LO+
45/0.18
270/0.3
Op amp800
800/2
34pF
Die Photo
• Differential inductor with
central tap RF grounded
by MIM capacitor
• Highly interdigitated
devices for matching
• Orthogonal LO and RF
paths where crossing
• 2.2mm2 die area
(1.2mm2 active area)
STMicroelectronics 0.18m RFCMOS - LQFP32 Package
IIP2 Measurement
• The two tones are filtered by the mixer RC load
• Differential probe has negligible impact on measured IIP2
Signalgenerator
Balun
Mixer Differentialprobe
LO input
RF input
f
f = 500kHz
fTX
DC
IM2
ffTX-f LO500kHz[1.92GHz-1.98GHz]
Bal
un
-100-80-60-40-20
020406080
100120
-30 -20 -10 0 10 20 30 40 50 60 70 80 90
Input Power [dBm]
Out
put P
ower
[dB
m]
Input IP2 = +84dBm
IIP2 = 2PDSB-SC - PIM2
50556065707580859095
100105
0 10 20 30 40 50 60
Sample #
IIP2
[dBm
]IIP2 Statistics
+78dBm
minimum IIP2
Lot #1 [March 2004]Lot #2 [June 2005]
50
55
60
65
70
75
0 5 10 15 20
Sample #
IIP2
[dBm
]
IIP2 Statistics without Cfat
IN+ IN-
Op amp
LO-
LO+
LO-
912/1.1
CFAT
LSW
Vref
Cload
Mdeg MdegCdeg
Rload
MpMp
LSW
Rload
Cload
Cdeg
IIP2 without Cfat
X
Conversion Gain and Noise
Conversion gain
• 16dB in-band gain
• 4.5MHz output bandwidth
Input referred noise
• 350kHz 1/f noise corner
• 4nV/√Hz average noise [10kHz-1.92MHz] -162
-160
-158
-156
-154
-152
-150
-148
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Frequency [MHz]
Inpu
t Noi
se P
SD [d
Bm
/Hz]
10k 100k 1M 10M8
10
12
14
16
18
Frequency [Hz]
In-B
and
Gai
n [d
B]
Measurement Summary
Voltage Gain [dB] 16
Output Bandwidth [MHz] 4.5
IIP3out-of-band [dBm] +10
IIP3in-band [dBm] +9
Minimum IIP2 [dBm] +78
Input Ref. Noise [nV/Hz] 4
Voltage Supply [V] 1.8
Current Consumption [mA] 4
Zero-IF UMTS Receiver
Assuming:
• 18dB LNA peak gain, Q=10 13dB gain at 1.98GHz
• 0dBm LNA IIP3out-of-band
• Downconverter with measured performance
IIP2 > +65dBm
IIP3out-of-band = -3dBm
Fully integrated zero-IF 3G receiver is feasible
Antenna input:
LOLO
IC
LNA I
Q
A 750mV 15kHz 1/f Noise Corner A 750mV 15kHz 1/f Noise Corner
51dBm IIP2 Direct – Conversion 51dBm IIP2 Direct – Conversion
Front – End for GSM in 90nm CMOSFront – End for GSM in 90nm CMOS
International Solid-State Circuits Conference, Feb. 2006International Solid-State Circuits Conference, Feb. 2006
Wireless Receivers in Deep-Submicron CMOS
Extremely high dynamic range at low voltagein cellular direct conversion solutions
90nm GSM Front-End at 750mV, to be compatible with 65nm and 45nm nodes
LNA LOQ
LOI
-43dBm-33dBm
-23dBm
GSMRX Signal(-99dBm)
AM Interferer
3MHz6MHz
0
RX Signal
Noise
IM2
f [kHz]100 200 300
Low-Voltage RX Front-End for GSM
• Few stacked devicesRequires high supply voltage
LNA LOQ
LOI
IN+ IN-
OUT+ OUT-
LG
LS
MRF
MC
LL
CLMSW
MRF
LO+
RL
LO-LO-
IN+ IN-
OUT- OUT+
MBIAS
Pseudo-Differential Input Stage
Mechanism #1:• IIM2,CM transfers to the
output still as a CM current
• R: conversion CM → diff.• Load resistors: (R/R=0.3%)
R/R ~ -50dB
Mixer IIP2 < 55dBmInadequate!
R + R
LO-LO-
IN+ IN-
VIM2,OUT
LO+
+ -
R -2
R2
IIM2,CM IIM2,CM
LO+ is ON
LO- is ONLC
filter
Suffers from excessive CM distortion: IIP2CM ~ 5dBm(W=50m, I=4mA)
Leakage Through the Commutating Pairs
• Transconductor: IIP2CM ~ 5dBm
• Leakage (Voff = 2mV):
L ~ -50dB
Mixer IIP2 < 55dBmInadequate!
Mechanism #2:• Voff1 and Voff2 determine
different leakage gainsIM2DIFF at mixer output
Voff1
R
LO-LO-
IN+ IN-
VIM2,OUT
LO+
+ -
R
IIM2,CM IIM2,CM
Voff2
LDIFF,1 LDIFF,2
LCfilter
Solution: Shunt-Shunt Feedback
• Low-frequency
CM feedback loop
attenuates IIM2,CM
• Transconductor:
IIP2CM ~ 5dBm;
R/R, L ~ -50dB;
1+GLOOP > 40dB
Mixer IIP2 > 90dBm!
LO-LO-
IN+ IN-
LO+
Voff1 Voff2
IIM2,CM IIM2,CM
Op
Amp+ -
VCM
VREF
IFEED IFEED
IIM2,CM
1+GLOOP
IIM2,CM
1+GLOOP
R + R2
R - R2
PCM
LCfilter
PCS1900 Direct-Downconverter Schematic
• PCM injects
common-mode noise No noise penalty
• PL reduces voltage
drop on R1
• gm,RF = 24mS further reduces switches 1/f noise contribution trading IIP2 and IIP3
• 5mA from 750mV-VDD
MSW
MRF
L1
C1
PCM
LO+
RCM
PLR1
C3
LO-LO-
VREF
+ -
IN+ IN-
OUT- OUT+
C2
250 5pF
2000/2.5
520pF
10k
400/0.3
125/0.220pF
5nH1000/0.1
Op AmpA
PCS1900 Low-Noise Amplifier Schematic
• Inductive degeneration for very low NF
• Partially external input impedance matching minimizes NF
From simulations: Gain = 23dB; NF = 1.6dB
• 5mA from 750mV-VDD
IN+ MIN 400/0.1
MC 400/0.1
20/0.1Gain Control
PG
CL 1.9pFLL 4.2nH
IN-LS 4nH
LSMD 4.7nH
OUT- OUT+
On C
hip
CSMD
2.2pF
Die Photo
• Dedicated RF ground avoids noise coupling from the substrate
• STMicroelectronics CMOS090 (90nm) - LQFP32 Package
• Highly interdigitated devices for matching
• 4.3mm2 die area(2.7mm2 active area)LNA
Mix
er I
Mix
er Q
Input Impedance Matching and RF Gain
1.7 1.8 1.9 2 2.1 2.218
20
22
24
26
28
30
32
34
-40
-30
-20
-10
0
Gai
n [d
B]
|S11
| [dB
]
Frequency [GHz]
Gain - MeasurementGain - Simulation|S11| - Measurement|S11| - Simulation
Noise Power Spectral DensityIn
put-R
efer
red
Noise
PSD
[dBm
]
Frequency [kHz]0 20 40 60 80 100
-174
-172
-170
-168
-166
-164
-162
-16015kHz 1/f noise corner
Average Noise Figure
[1kHz-100kHz]: 3.5dB
45
50
55
60
65
70
75
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Sample #
IIP2
[dBm
]IIP2
51 dBm minimum
over 25 samples
Voltage Gain 31.5dB
Noise Figure [1kHz-100kHz] 3.5dB
1/f Noise Corner 15kHz
Minimum IIP2 51dBm
IIP3 -10.5dBm
1dB C.P. due to 3MHz Blocker
-18dBm
Gain Reduction 6dB
Voltage Supply 750mV
Current Consumption 15mA
Die/Active Area 4.3/2.7mm2
Technology STMicroelectronics CMOS090
Measurement Summary
Injection Locked dividers for Injection Locked dividers for
Quadrature Generation in Direct Quadrature Generation in Direct
Conversion CMOS ReceiversConversion CMOS Receivers
Journal of Solid-State Circuits, Sept. 2004Journal of Solid-State Circuits, Sept. 2004
Custom Integrated Circuits Conference, Sept. 2003Custom Integrated Circuits Conference, Sept. 2003
Local Oscillator Generation
RF inLO
LO I
LO Q
BB I
BB Q
• Low phase noise at large offset
• Large tuning range
• Minimum power consumption
while driving large mixer LO input capacitancewhile driving large mixer LO input capacitance
Coupled LC Oscillators
Quadrature accuracy trades with phase noise
Fixed capacitances reduce the available tuning range
I+
I+
I-
I-Q+
Q+ Q-
Q-
I+
I+
I-
I-Q+
Q+ Q-
Q-
+Cpar Cmixer
Phase noise and tuning range set by the VCO
Quadrature accuracy set by dividers
Dividers must feature enough ‘locking band’
Injection Locking Frequency Dividers
A VCO running at 2A VCO running at 200 drives two LC frequency drives two LC frequency
dividersdividers
divideby 2
divide by 2
+
-
VCO@
20
LO_I
LO_Q
0
bias
V o-
bias
Vo+
The DC current is actually limiting the locking range:
(es.: if IDC = Iinj, |max| ≈ 30°)
Harmonic components other than the fundamental are filtered-out by the LC tank For correct regeneration the loop phase shift is
() + () = 0
Regenerative Model, 3, 5, ...
Vocos(t+)
IDC +
IINJ @2
cos(t+)
ITANK =
IINJ/2 cos(t-)
ITANK=IINJ/2
IINJ cos(2t)IDC +
IINJ cos(2t)
cos(t+)
ITANK= IDC cos(t+) +
IINJ/2 cos(t-)
IDC
IINJ/2
ITANK
max
22
2 2DC inj
DC inj
I Iarctg
I I
Locking Range and Quadrature Accuracy
inj
DCdev
inj 0
DC
I
Iχ 3 Δω 2Ph = Q +1 =
I4 ω 3 Q
I
V1cos(t+1)
V2sin(t+2)
+IINJ
-IINJ
IDC
IDC
Locking-range and phase accuracy improve
reducing load Q and increasing injection ratio
• Fully Differential Topology
• DC offset cancellation loop
• 0.18m CMOS Technology
• Double Frequency VCO
• Second-Harmonic Injection Locking Dividers
CMOS Direct Conversion front-end
Servo-loop around the VGA implements a 3kHz high pass filter
2
90°
VCOLNA
0°
IVGA
Gm
QVGA
Gm
Die Microphotograph
Total chip area = 16mm2
3.4m
m4.7mm
I&Q I&Q VGA VGA
+ + servo servo looploop
VCOVCO
I&Q I&Q mixer mixer and and
dividersdividers
LNALNA
VarBias
Vctrl
MN1MN2
Double Frequency VCOVsig
P-substrate
Vctrl
n-well
Cox
PolySI
n+n+
Separate supply voltage:
Improved tuning Range
Improved PSRR
0.1
0.2
0.3
0.4
-4 -2 0 2 4
VarBias-Vctrl[V]
Cap
[pF
]
Improved tuning
Dividers Implementation
Capacitive load: parasitic only
Q lowered to 4 to keep a safety margin on quadrature error
Input trasconductor in subthresold for maximum Iinjection
Cload = 1.2pF
LO + LO -
bias
5nH
1.8 V
2kI+ I- Q- Q+
40/ 0.25
3.5
3.6
3.7
3.8
3.9
4
0 0.3 0.6 0.9 1.2 1.5 1.8Var_control
VC
O F
req
uen
cy[G
Hz]
VddLO=1.1V
VddLO=1.2V
VddLO=1.3V
VddLO=1.4V
VCO Tuning Range
1.75
1.8
1.85
1.9
1.95
2
0 0.3 0.6 0.9 1.2 1.5 1.8Var_control
Div
iders
Fre
qu
en
cy
[GH
z]
VddLO=1.1V
VddLO=1.2V
VddLO=1.3V
VddLO=1.4V10.6%10.6%
Lower oscillation
frequency due to LC load variation
Locking range and Phase deviation
0
1
2
3
4
5
6
7
8
9
10
1.73 1.78 1.83 1.88 1.93 1.98 2.03 2.08
Output Frequency [GHz]
model
Pha
se D
evia
tion
[°] measurements
Locking Range
0
5
10
15
20
25
30
-6 -4 -2 0 2 4 6 8 10 12 14Injected Power [dBm]
measurements
model
Lo
ckin
g R
ang
e [%
]
IINJ/IDC = 0.5
IINJ/IDC = 1
IINJ/IDC = 1.33
Phase Deviation
(down-converted signals)
IINJ/IDC=0.5
IINJ/IDC=0.9
IINJ/IDC=1.5
Phase Noise
* Integrated between 200 kHz and 1.92 MHz** Integrated between 10 kHz and 1.92 MHz
Performance Summary
Power consumption breakdown
47dBGain
-155dBc/HzPN@135MHz
0.18m 6M CMOS
Technology
16mm2Active Area
38mWPower
+44.8dBmMinimum IIP2
-2dBmIIP3 out-of-band
4.2dB * 5.6dB **NF
I&Q Mixer 38%
LNA 24%
VGA 9,5%
VCO 9,5%
I&Q DIV 19%
Injection Locked Balanced Dividers
divideby 2
divide by 2
+
-
VCO@
20
LO_I
LO_Q
0Vo+ Vo-
VDCIDC
LC
Fully balanced multiplier suppress
the DC current0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4
Output Frequency, [GHz]
Otp
ut
Am
pli
tud
e,
[V]
/0≈42%
Increasing IDC
42% measured locking range with Qtank = 14
Towards highly integrated Towards highly integrated
Multiband MultistandardMultiband Multistandard
Receivers Receivers
Universal Mobile Terminals
Ultimate
solution: Zero-IF
fully integrated
multistandard RX
• Mixer and analog base-band blocks are easily re-configurable
• LNA is the most critical block for multistandard operation
LNA
ADCAnalog BB
Analog BB ADC
I Q
Switchplexer& SAW
IC
n
n
GSM900GPS
GSM1800/1900CDMA2000
UMTS802.11b/g HiperLAN2
HiSWANa, 802.11a,
802.16a
f[GHz]1 2 3 4 5 6
Vout
RS
VS
LB
LE
ZL
LNA State-of-the-Art
Resonant network
for voltage gain
Resonant network for
input impedance matching
Two resonant networks must be reconfigured for
multistandard operation critical in the GHz range
Series-shunt feedback
Input impedance:
Feedback Amplifier
RS
VOUT
VS
CBYP
ZIN
ZL
IN Lm
1Z (f) + α Z (f)
g
• Biasing current not set by impedance matching constraints allows optimization of NF and IIP3
• Load reconfiguration allows multi-standard operations
OUT L
S S
V Z (f)(f) =
V 2R
Voltage gain
(input matched):
f1
Multi-Band Feedback LNA
Rs
Vout
Vin
Cbypass
f1
-35
-30
-25
-20
-15
-10
-5
0
Frequency
S11
[dB
]
Programmable resonance
frequency load
-10
-5
0
5
10
15
20
Frequency
Gai
n [d
B]
f2
-35
-30
-25
-20
-15
-10
-5
0
Frequency
S11
[dB
]
-10
-5
0
5
10
15
20
Frequency
Gai
n [d
B]
f2
Concurrent Feedback LNA
Rs
Vout
Vin
Cbypass
f1 f2 f3
Multiple resonant load
-35
-30
-25
-20
-15
-10
-5
0
Frequency
S11
[dB
]
-10
-5
0
5
10
15
20
Frequency
Gai
n [d
B]
f1 f2 f3
Input Impedance:
) f ( Z gm1
1
gm
1Zin
load21
Current Gain:
)) f (Z gm(1
1
I
I
load2in
out
• gm1 > 1/Rs
• Current gain greater than 1
Positive Feedback based solution
Bias
In
Zload (f)
Out
IBias
-1
M1
M2
Iout
Iloop Iin
Zin
A 0.13 m CMOS Front-End for
DCS1800/UMTS/802.11b-g with
Multi-band Positive Feedback
Low Noise Amplifier
VLSI Symposium on Circuits, June 2005VLSI Symposium on Circuits, June 2005
Multi-Standard Scenario
MultiStandardReceiver
1805 1880 2110 2170 2400 2485
DCS1800 UMTS IEEE802.11b/g
f[MHz]
230MHz 230MHz
• Cellular (DCS1800)
• Data (IEEE802.11b/g)
• Mixed voice/data (UMTS)
Applications:
• Positive feedback realized by M2-M4
• Re-configurable LC load by inductor selection
Multi-Band LNA
M4 M2
M1
+ Vin -
Vdd
V1L2 diff
L1
L4 diff
L3
V2
Tuneable Load
+ Vout -
Vbias
V3
VariableGain
M5
Vbias
V3
M6M3
Off- Chip
VariableGain
• Three selectable bands
• 6dB gain variation
Multi-Standard Mixer: Transconductor
• Different noise-linearity
trade-off for each standard
• GSM requires higher gm
than UMTS and WLAN but
asks for lower IIP3
• Switch V1 sets the
transconductance gain
M1 M3 M4 M2
M5 M6
M7V1 V1
Vgain
VariableGain
C1 C1Vb1
+ Vin/2 - Vin/2
iRF+ iRF-
Multi-Standard Mixer: Switching Pairs
• LC filter improves noise
and linearity
• PMOS switching pairs for
low 1/f noise
• Multi-mode RC load sets
appropriate gain and
bandwidth for each standard
Multi-mode Load
M8
M13 M14
M9 M10 M11 M12
Vb3
UMTS DCS WLAN
MultiModeLoad
LO+ LO+LO-
C2
Vb2
Vdd
L1
iRF+ iRF-
Input Matching
-35
-30
-25
-20
-15
-10
-5
0
1.5 1.7 1.9 2.1 2.3 2.5
Frequency [Hz]
S11
[d
B]
DCS1800
UMTS
802.11b-g
Gain
15
18
21
24
27
30
1.5 1.7 1.9 2.1 2.3 2.5Frequency (GHz)
Gai
n [
dB
]
DCS1800
UMTS
802.11b-g
Performance summary
DCS1800 UMTS IEEE802.11b/g
Gain (high / low) [dB] 28.5 / 13.5 29.5 / 14.5 23.5 / 8.5
NF [dB] 5.2 5.6 5.8
IIP2 [dBm] 50 51 54
IIP3 [dBm] -7.5 0 -4.8
Current Consumption: 20mA
Voltage Supply: 1.8V
A Variable Gain RF Front-End, A Variable Gain RF Front-End,
Based on a Voltage – Voltage Based on a Voltage – Voltage
Feedback LNA, for Multistandard Feedback LNA, for Multistandard
ApplicationsApplications
Journal of Solid-State Circuits, March 2005Journal of Solid-State Circuits, March 2005
5-6GHz Multi-Standard WLAN Scenario
• About 1GHz overall bandwidth
• Spectrum allocation fragmented in 100-250MHz sub-bands
5150 - 5350
49005000
57255825
5000 5200 5400 5600 5800
Japan: MMAC HiSWANa
[MHz]
5150 - 5350Europe: ETSI
BRAN HiperLAN2 5470 - 5725
US: IEEE 802.11a
51505250
Multi-standard narrow-band
re-configurable receiver
WLAN Multi-Band LNA
Simulated Results
Idiss Gain NF IIP3
6mA 23dB 1.6dB 0dBm
Tunable LC load
8 selectable bands
between
4.9-5.825GHz
Capacitive feedback
1
1 2
C
C C
Lload=3.3nH
RCM=8
Cc=4Ca
Vc
Cb=2Ca
Vb
Ca=40fF
Va
C2
C1
LSMD
Cc
Vc
Cb
Vb
Ca
Va
C2
C1
LSMD
OUT
IN
ONCHIP
Variable Gain Mixer
• Pseudo differential NMOS input stage
• Input stage current boosting
• Differential inductor (Lquad=7nH)
Variable gain feature:
• 11dB gain reduction
• 3.5dB IIP3 improvement
• Constant output pole cut-off frequency and DC output level
7/0.25
50/0.25
Lquad=7nH
Cdiff=9pF
320
200
IN-IN+
LO- LO-
LO+
CSW=25pF
VgcVgc
Vgc
SW1 SW2
SW3
Vgc
SW4 SW5MR
R1
R2
CparCpar
CSW
1.75
mA
0.75
mA
Die Photomicrograph
Technology: STMicroelectronics (BiCMOS7G)
BiasBias
LNALNA
Mix
er I
Mix
er I
Mix
er Q
Mix
er Q
• Chip area:
1.6mm2
• Package
QFN 36
• PAD ESD
protected
Input Impedance Matching
-30
-25
-20
-15
-10
-5
0
4.5 4.65 4.8 4.95 5.1 5.25 5.4 5.55 5.7 5.85 6
Frequency [GHz]
|S1
1|
[dB
]
18
20
22
24
26
28
30
32
4.5 4.65 4.8 4.95 5.1 5.25 5.4 5.55 5.7 5.85 6
Frequency [GHz]
Ga
in [
dB
]Front-End Gain
Fixed IF frequency (500kHz)
Performance Summary
High Gain Low Gain
Voltage gain [dB] 31.5 20.5
NF [dB] 2.5 2.9
IIP3 [dBm] -9.5 -6
IIP2 [dBm] 23 31
I&Q matching [dB] 0.3
Voltage Supply [V] 2.5
Current consumption [mA] 16
Technology BiCMOS SiGe 0.25mm
An Interference Robust An Interference Robust
0.180.18m CMOS 3.1-8GHz Receiver m CMOS 3.1-8GHz Receiver
Front-End for UWB RadioFront-End for UWB Radio
Custom Integrated Circuits Conference, Sept. 2005Custom Integrated Circuits Conference, Sept. 2005
Multi-Band OFDM UWB Scenario
IEEE802.11a
IEE
E 8
02.1
1b/g
Group#1
Group#2
Group#4
Group#3
Group#5
f [MHz]
3168 4752 6336 7920 9504 10560
• Group #1 mandatory, groups #2 - #5 optional
• Huge 5-6GHz WLAN interferer can desensitize the UWB RX
Multi-resonance
LNA with 5-6GHz
WLAN attenuation
Multi-Resonance UWB LNA
Cext=3pF
Vbias
OUT
IN
1.1pF
220fF3nH
1nH
Zload
Lext=5.6nH
C2=700fF
C1=20fF
40/0.18
Zin
on-chip • Feedback-based LNA for superior dynamic range
• 11dB simulated WLAN attenuation
30
35
40
45
50
55
1 2 3 4 5 6 7 8 9 10Frequency [GHz]
|Zlo
ad| [
dB
]
• Single I&Q transconductor lowers LNA load parasitic• 1.5nH inductor tunes out switching pairs parasitic• Second order LPF improves RX selectivity
I&Q Mixers
IN
Vbias
16pF
Cpar
62.5/0.18
LO I+ LO I-
600
OUT I-
4pF
Vbias
100/0.25
200/0.18
OUT I+
LO Q+ LO Q-
OUT Q-VbiasOUT Q+
625/1
1.5nH
580fF
Gain and Input Matching
-30369
1215182124
1 2 3 4 5 6 7 8 9 10Frequency [GHz]
Gai
n [d
B]
-18-16-14-12-10-8-6-4-20
|S11
| [dB
]
Gain |S11|
Performance summary
UWB Channel
[MHz]
Gain [dB]
IEEE802.11a blocking power
[dBm]
1dB C.P. [dBm]
IIP3 [dBm]
IIP2 [dBm]
NF [dB]
Group #1
3432 20.8 -6 -11 -3.5 36.9 7.2
3960 23.2 -6 -12.5 1 34.5 5.2
4488 20.6 -5.5 -11.5 -3.3 42.1 7.3
Group #3
6600 20.2 -5.5 -8 -3.15 46 7.7
7128 22.8 -6.5 -11.5 3.35 35.2 5.3
7656 20.7 -6 -8 -3 42 7.1
Current Consumption: 10mA
Voltage Supply: 1.8V
These works have been carried on by the
following phd students : Francesco Gatta,
Danilo Manstretta, Paolo Rossi, Massimo
Brandolini, Antonio Liscidini, Andrea
Mazzanti, Paola Uggetti, Giuseppe Cusmai,
Marco Sosio.
I am indebted with them.
Acknowledgements