1

Performance Analysis of a 1200 V SiC MOSFET

Based 10 kVA Voltage Source Inverter

Parthasarathy Nayak1, Jose Titus2, Kamalesh Hatua3

Department of Electrical Engineering

Indian Institute of Technology Madras

Chennai - 600036 , India

Email: 1parthasarathy.nayak.2015@ieee.org,2josenit1787@gmail.com,3kamalesh@ee.iitm.ac.in

Abstract—Silicon carbide (SiC) MOSFET has the po-

tential to replace silicon (Si) IGBT due to its superior

switching performance. However due to presence of para-

sitic inductance in converter layout, device voltage and cur-

rent experience overshoots and oscillations during device

switching. These undesired overshoots increase switching

loss. In the context of these parasitic inductances, the

performance of an equivalent Si IGBT and SiC MOSFET

based 10 kVA converter has been compared in this paper.

Variation of switching loss with switching frequency at

different parasitic inductances have been reported. A 10

kVA SiC MOSFET based voltage source inverter has been

designed and its performance has been analyzed by driving

an induction motor.

Index Terms—SiC MOSFET, parasitic inductance,

switching characteristics, switching loss.

I. INTRODUCTION

SIC MOSFET has been the center of attrac-

tion since it’s commercial availability in 2011.

It is mostly due to it’s superior properties like

higher breakdown field strength, improved thermal

stability, superior switching performance, low on

state resistance [1]-[3]. These superior properties

allow the device to be switched beyond 20 kHz

while maintaining efficiency above 99 % for a

hard switched converter. Also due to high switching

frequency of operation, the size of passive filters can

be greatly reduced.

Due to the superior switching characteristics, the

di/dt and dv/dt of the SiC MOSFET is more than

twice that of equivalent IGBTs. With such a high

voltage and current slew rate, the device voltage and

current experience undesired overshoot and oscil-

lations due to the presence of parasitic inductance

in converter layout and device packaging during

switching transients [4]-[7]. These overshoots and

oscillations increase switching loss, degrades EMI

performance of the converter and generates voltage

and current stress in the device.

These are the issues pop up while designing

a SiC MOSFET based hard switched converter.

These issues are not that detrimental for Si IGBT

based converters as they switch slower. Two of

the solutions to these issues are to either reduce

parasitic inductances or to slow down the switching

of the devices by increasing the gate resistance.

Whereas there is a limitation for first solution, due

to mechanical design constraint and the second

solution fails to extract maximum benefit from SiC

MOSFET. There have been analysis on performance

of SiC MOSFET based converter, where authors

have slowed down the device by increasing the gate

resistance [8]-[10]. Though it still provides better

results than Si IGBT based converters but fails to

optimize the potential benefit of SiC MOSFET. This

paper reports the performance analysis of a 10 kVA

converter by keeping minimum gate resistance but

the leakage inductances have been restricted by crit-

ical design of converter layout. It also emphasizes

on the gate driver design for SiC MOSFETs and it’s

performance in the context of common mode current

injection. The developed converter has been tested

by driving an induction motor. The performance of

the inverter at various switching frequency has been

included in this paper along with the effects of high

speed switching on motor terminal voltage.

Section II of this paper draws a comparison

between performance of a 10 kVA SiC MOSFET

and Si IGBT based converter. The change in per-

formance of SiC MOSFET based inverter under

2

the influence of parasitic inductance is reported

in Section III. All detrimental effects of parasitic

inductance are summarized in Section IV. Section

V explains the gate driver and converter layout

designs. Performance of a 10 kVA SiC MOSFET

with an induction motor has been elaborated in

Section VI. Section VII concludes the paper.

II. PERFORMANCE COMPARISON BETWEEN SIC

MOSFET AND SI IGBT BASED 10 KVA HARD

SWITCHED VOLTAGE SOURCE INVERTER

This section carries out a comparison between

performance of an equivalent SiC MOSFET and

Si IGBT based 10 kVA, hard switched two

level voltage source inverter. The SiC MOSFET

(SCH2080KE) under study is ROHM make 1200

V, 35 A device and Si IGBT (IXDH20N120D1) is

of IXYS make 1200 V, 38 A device. This study has

been carried out on a 3-phase inverter, feeding a

R-L load at 0.8 power factor at different switching

frequencies of operation. The typical turn on and

turn off period of selected SiC MOSFET is 70 nsec

and 98 nsec respectively. Whereas for IGBT under

study has turn on period of 175 nsec and turn off

period of 570 nsec. Due to high switching duration,

IGBT exhibits more switching loss compared to SiC

MOSFET. The on state resistance (RDS(on)) of SiC

MOSFET under comparison is 80 mΩ. The on state

voltage VCE(sat) of IGBT is typically 2.4 V. This

high on state voltage for IGBT increases conduction

loss, reducing overall efficiency of the system. The

switching loss and percentage efficiency of two

converters have been plotted in Fig. 1 and Fig. 2

respectively. As depicted in Fig. 1 the switching

loss of SiC MOSFET based 10 kVA converter is

10 W at switching frequency of 5 kHz and 20 W at

20 kHz of switching frequency. On the contrary Si

IGBT based converter exhibits loss up to 100 W at

5 kHz and 280 W at 20 kHz of switching frequency.

Due to this lower switching loss the SiC MOSFET

based converter exhibits an efficiency of 99.4 %

and 98.6 % at switching frequencies of 5 kHz and

20 kHz respectively. In both the cases conduction

loss of the converter is 40 W. Whereas at 20

kHz switching frequency, Si IGBT based converter

exhibits efficiency of 88 % (Fig. 2). This lower

switching loss is an advantage of SiC MOSFET.

But in real practice it is challenging to achieve

such a high efficiency. This is primarily due to the

Switching Frequency (kHz)

5 10 15 20 25

Sw

itch

ing

Lo

ss (

W)

50

100

150

200

250

300

350

Switching Loss Vs Switching Frequency

Si IGBT

SiC MOSFET

Fig. 1. Switching loss Vs switching frequency plot between SiC

MOSFET and Si IGBT based 10 kVA converter.

80

85

90

95

100

105

5 10 15 20 25

Perc

en

tag

e E

ffic

ien

cy

Switching Frequency (kHz)

Percentage Efficiency Vs Switching

Frequency

Si IGBT

SiC MOSFET

Fig. 2. Percentage efficiency Vs switching frequency plot between

SiC MOSFET and Si IGBT based 10 kVA converter.

10 20 30 40 500

500

1000

1500

Switching Frequency (kHz)

Swit

chin

g L

oss

in W

SiC MOSFET based 10 kVA InverterSwitching Loss Vs Switching Frequency with Lp

30 nH Lp 300nH Lp 500nH Lp

Fig. 3. Switching loss Vs switching frequency plot with Lp for SiC

MOSFET based 10 kVA converter.

10 20 30 40 5070

75

80

85

90

95

100

Switching Frequency (kHz)

Per

cent

age

Eff

icie

ncy

SiC MOSFET based 10 kVA Inverter Efficiency Vs Switching Frequency with Lp

30 nH Lp 300 nH Lp 500 nH Lp

Fig. 4. Percentage efficiency Vs switching frequency plot with Lp

for SiC MOSFET based 10 kVA converter.

presence of parasitic inductances in the converter

layout. These parasitic inductances increase voltage

overshoot and switching loss.

3

The above stated switching loss figures are ob-

tained through LTspice simulation at different par-

asitic inductances with different load current level.

These information have been tabulated in a lookup

table in MATLAB. From the lookup table data,

the total switching and conduction loss have been

calculated for a 10 kVA converter.

III. PERFORMANCE OF SIC MOSFET UNDER

THE INFLUENCE OF PARASITIC INDUCTANCES

During switching transients device current and

voltage experience overshoot and oscillation due

to the presence of parasitic inductance (Lp) in

converter layout. The oscillation occurs because

of L-C network formed between parasitic induc-

tances and device output capacitance (Coss). These

overshoots in device voltage and current increase

switching loss. It degrades the efficiency of the

converter. Fig. 3 shows the increase in switching

loss due to increase in parasitic inductances (Lp).

Corresponding reduction in percentage of efficiency

is depicted in Fig. 4. It can be noticed that for

a Lp of 500 nH, switching loss increases to 1500

W at switching frequency of 50 kHz. It results an

efficiency of 84 %. Interestingly for this range of

parasitic inductance, IGBT based converter does not

show greater reduction in efficiency. It is because of

comparatively lower voltage overshoot considering

the slow di/dt of IGBT. Therefore in order to

achieve high efficiency for SiC MOSFET based

converter, a special attention must be given to the

effects of parasitic inductances in the layout.

IV. EFFECTS OF PARASITIC INDUCTANCES ON

SWITCHING PERFORMANCES OF SIC MOSFET

The adverse effects of parasitic inductances

present in converter layout for SiC MOSFET are

manifold. Some of them are described below.

• During turn off transient device voltage experi-

ences a voltage overshoot due to oscillation be-

tween device output capacitance and parasitic

inductance Lp. Due to high current slew rate

(di/dt) of SiC MOSFET (around 1.2 kA/µs),

device experiences a voltage overshoot of 246

V above DC bus voltage of 600 V for parasitic

inductance of 150 nH. It can be observed in

Fig. 5. Table I shows the increase in voltage

overshoot and switching loss with increase in

parasitic inductance Lp.

• Parasitic inductance in the layout causes over-

shoot in device current and gate voltage during

turn on transient. It happens due to oscillation

between Lp and the equivalent capacitance

formed by the parasitic capacitance of load

inductor and the reverse biased capacitance

of antiparallel diode. The overshoot in gate

voltage can damage the gate terminal of the

device if it crosses the maximum gate to source

voltage rating of the device. It can be observed

in Fig. 6. For an Lp of 150 nH device current

and gate voltage overshoot by 30 % and 20 %

respectively. The overshoot in device current

generates stress in the device and increases turn

on loss.

TABLE I

EFFECT OF Lp ON SIC MOSFET PERFORMANCE

Lp Overshoot of Vds Etotal

50nH 5 % 0.9 mJ

100nH 20 % 1.0 mJ

200nH 50 % 1.2 mJ

300nH 55 % 1.7 mJ

500nH 68 % 2.0 mJ

650nH 76 % 2.5 mJ

Fig. 5. Overshoot in device voltage, Vds at Lp of 200 nH. Scale:

Vds = 150 V/div, Time = 290 ns/div.

Fig. 6. Overshoot in gate voltage, Vgs and device current Id at Lp

of 150 nH. Scale: Vgs = 10 V/div, Id = 10 A/div, Time = 100 ns/div.

4

• SiC MOSFET injects comparatively more com-

mon mode noises into the system due to high

di/dt and dv/dt. It happens because of miller

current injection (Cdv/dt) and voltage devel-

oped across DC bus return parasitic induc-

tances (Ldcrdi/dt) during switching transients.

The common mode current flows into the sys-

tem through different coupling capacitances.

For example, the common mode (CM) current

injected in to the control unit passes through

the coupling capacitances of isolated power

supply for gate driver. These noises enter into

the power unit through parasitic capacitances

formed between device surface and heat sink.

These injected noises degrade EMI perfor-

mance of the converter.

V. 10 KVA SIC MOSFET BASED VOLTAGE

SOURCE INVERTER DESIGN

A. Gate Driver Design

An hard switched gate driver has been developed

for switching the devices. The top and bottom view

of the gate driver is depicted in Fig. 7 and Fig.

8 respectively. The gate driver is designed with a

four layer printed circuit board (PCB) to minimize

ground noises. It is stated in the Section IV that

due to high di/dt and dv/dt common mode (CM)

noises are injected in to the system. These noises are

injected into the control circuit through the coupling

capacitance of isolated power supply. Therefore

in order to arrest these noises, an isolated power

supply has been designed with minimum coupling

capacitance (< 5 pF). The isolated power supply is

shown in Fig. 9. It has one primary winding wound

for 15 V supply and two secondary windings for 20

V and -5 V power supply. An additional common

mode choke is provided in the non isolated side

of the gate driver to restrict the injected common

mode current at the gate driver terminal. The gate

driver’s response for restriction of injected common

mode current can be observed in Fig. 10. It depicts

the CM current injected during turn on and turn off

instant.

B. Converter Layout Design

Converter layout design plays a critical role for

SiC MOSFET. The parasitic inductance should be

kept as low as possible to minimize its detrimental

effects. In order to reduce leakage inductances,

Fig. 7. Top view of developed gate driver for SiC MOSFET.

Fig. 8. Bottom view of developed gate driver for SiC MOSFET.

Fig. 9. Isolated gate driver power supply developed for SiC

MOSFET.

Fig. 10. Response of isolated power supply of gate driver and

common mode choke on common mode noise propagation.

Fig. 11. Top view of designed 10 kVA converter layout for SiC

MOSFET.

5

Fig. 12. 10 kVA SiC MOSFET based two level converter.

Fig. 13. Phase voltage and line currents of induction motor. Scale

: IR = 10 A/div, IY = 10 A/div, VRY = 400 V/div.

the developed layout follows sandwiched bus bar

configuration to reduce current loop lengths. The

DC bus has been sandwiched on a printed circuit

board (PCB). As a result the leakage inductance

in each leg is reduced to less than 80 nH. The

copper thickness is maintained at 8 mil. It has been

designed to carry a load current of 20 A. The PCB

is made up of FR4 material of 3.2 mm thickness.

The top view of the converter layout can be seen

from Fig. 11. In order to nullify the effects of

leakage inductances, four metalized polypropylene

capacitors of 20 µF each have been connected across

the DC bus along with two 2200 µF electrolytic

capacitors.

VI. PERFORMANCE ANALYSIS OF THE

DEVELOPED 10 KVA SIC MOSFET BASED VSI

The developed SiC MOSFET based converter has

been tested by driving an induction motor as a load.

The machine parameters are given in Appendix A.

The induction machine is operated by v/f control.

The developed converter is depicted in Fig. 12.

The DC bus has been maintained at 500 V. Due

to reduction of parasitic inductances the voltage

Fig. 14. Inverter and motor terminal voltage along with line current.

Scale : Voltage = 400 V/div, Line current = 10 A/div.

Fig. 15. Inverter and motor terminal voltage along with line current.

Scale : Voltage = 400 V/div, Line current = 10 A/div.

overshoot at the device terminal is reduced to 17 %.

As a result the switching loss is 22 W and efficiency

of the converter is 98.5 % at 20 kHz switching fre-

quency. Fig. 13 shows the response of the converter

at 20 kHz of switching frequency. Even though

the voltage overshoot has been restricted largely,

motor terminal voltage experiences a very high

voltage overshoot and low frequency oscillations as

delineated in Fig. 14 and Fig. 15. It can be observed

that the phase voltage overshoots twice the DC bus

voltage. It occurs due to cable leakage inductances

and parasitic capacitances. In this case the length of

the copper cable from converter terminal to motor

terminal is 2 meter.

VII. CONCLUSION

SiC MOSFET is a viable alternative for Si

IGBT due to its attractive switching characteristics.

But the converter performance degrades with the

presence of parasitic inductances in the layout. In

this paper, a comparison study on SiC MOSFET

and Si IGBT based converter has been carried out

6

under the influence of parasitic inductance. The

detrimental effects of parasitic inductance have

been summarized. The gate driver and converter

layout design has been explained along with its

performances. The developed converter is tested

with an induction motor. The response of the

converter has been elaborated. The efficiency of

the developed converter is found to be 98.5 % at

switching frequency of 20 kHz.

APPENDIX A

TABLE II

KEY PARAMETERS OF THE INDUCTION MOTOR

Parameter Value

Power rating (Prated) 30 kW

Voltage rating (Vrated) 380 V

Stator resistance (Rs) 0.12727 Ω

Rotor resistance (Rr) 0.12727 Ω

Stator leakage inductance (Lls) 0.001341 H

Rotor leakage inductance (Llr) 0.001341 H

Mutual inductance (Lm) 0.045219 H

Rotor inertia (J) 0.8 Kgm2

Number of poles (P ) 4

Rotor speed (N ) 1450 rpm

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