ZVS Switching Regulators Rev 1.2 Page 1 of 27 07/2019 14 – 42V IN ZVS Buck Regulator ZVS Switching Regulators PI332x-00-LGIZ Note: Product images may not highlight current product markings. Product Description The PI332x-00 is a family of high input voltage, wide input range DC-DC ZVS Buck regulators integrating controller, power switches, and support components all within a high-density System-in-Package (SiP). The integration of a high-performance Zero-Voltage Switching (ZVS) topology, within the PI332x-00 series, increases point-of-load performance providing best-in-class power efficiency. The PI332x-00 requires only an external inductor, two voltage selection resistors and minimal capacitors to form a complete DC-DC switch-mode buck regulator. Features & Benefits • High‑Efficiency HV ZVS Buck Topology • Wide input voltage range of 14 – 42V • Power‑up into pre‑biased load ≤ 6.0V • Parallel capable with single‑wire current sharing • Input Over/Undervoltage Lockout (OVLO/UVLO) • Output Overvoltage Protection (OVP) • Overtemperature Protection (OTP) • Fast and slow current limits • Differential amplifier for output remote sensing • User‑adjustable soft start & tracking • –40 to 120°C operating range (T INT ) Applications • HV to PoL Buck Regulator Applications • Computing, Communications, Industrial, Automotive Equipment Package Information • 10 x 14 x 2.6mm LGA SiP Device Output Voltage I OUT Max Set Range PI3325-00-LGIZ 5.0V 4.0 – 6.5V 20A
Transcript
ZVS Switching Regulators Rev 1.2Page 1 of 27 07/2019
14 – 42VIN ZVS Buck Regulator
ZVS Switching RegulatorsPI332x-00-LGIZ
Note: Product images may not highlight current product markings.
Product Description
The PI332x-00 is a family of high input voltage, wide input range DC-DC ZVS Buck regulators integrating controller, power switches, and support components all within a high-density System-in-Package (SiP).
The integration of a high-performance Zero-Voltage Switching (ZVS) topology, within the PI332x-00 series, increases point-of-load performance providing best-in-class power efficiency. The PI332x-00 requires only an external inductor, two voltage selection resistors and minimal capacitors to form a complete DC-DC switch-mode buck regulator.
Features & Benefits
• High‑Efficiency HV ZVS Buck Topology
• Wide input voltage range of 14 – 42V
• Power‑up into pre‑biased load ≤ 6.0V
• Parallel capable with single‑wire current sharing
• Input Over/Undervoltage Lockout (OVLO/UVLO)
• Output Overvoltage Protection (OVP)
• Overtemperature Protection (OTP)
• Fast and slow current limits
• Differential amplifier for output remote sensing
Product Nominal Output Rated IOUT Package Transport Media
PI3325-00-LGIZ 5.0V 20A 10 x 14mm LGA TRAY
Absolute Maximum Ratings
Notes: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the Electrical Specifications table is not guaranteed. All voltages are referenced to PGND unless otherwise noted.
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PI332x-00-LGIZ
Functional Block Diagram
VIN
PGND
SGND
SYNCO
PWRGD
Q1Q2
VCC
EN
SYNCI
TRK
EAO
EAIN
Power Control
+-
VDR
0Ω
ZVS Control
Digital Parametric Trim
VREF
CHF
CEAIN-INT
COMP
VSP+- VSN
VDIFF
VS1
VOUT
TESTx
RZI
Simplified block diagram
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Pin Description
Name Location I/O Description
VS1 Block 1 Power Switching Node: and ZVS sense for power switches.
VIN Block 3 Power Input Voltage: and sense for UVLO, OVLO and feed forward ramp.
VDR 5K I/OGate Driver VCC: Internally generated 5.1V. May be used as a bias supply for low power external loads. See Application Description for important considerations.
SYNCI 4K I
Synchronization Input: Synchronize to the falling edge of external clock frequency. SYNCI is a high impedance digital input node and should always be connected to SGND when not in use. The PI332x-00 family is not optimized for external synchronization functionality. Refer to Application Description of Parallel Operation for details.
SYNCO 3K OSynchronization Output: Outputs a high signal at the start of each clock cycle for the longer of ½ of the minimum period or the on time of the high-side power MOSFET.
TEST1 2K I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
TEST2 1K I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
TEST3 1J I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
TEST4 1H I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
TEST5 1E I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
PWRGD 1G OPower Good: High impedance when regulator is operating and VOUT is in regulation. Otherwise pulls to SGND.
EN 1F I/OEnable Input: Regulator enable control. When asserted active or left floating: regulator is enabled. Otherwise regulator is disabled.
SGND Block 5Signal Ground: Internal logic ground for EA, TRK, SYNCI, SYNCO communication returns. SGND and PGND are star connected within the regulator package.
TRK 1C ISoft Start and Track Input: An external capacitor may be connected between TRK pin and SGND to increase the rise time of the internal reference during soft start.
COMP 1B OCompensation Capacitor: Connect capacitor for control loop dominant pole. See Error Amplifier section for details. A default CCOMP of 4.7nF is used in the example.
EAO 1A O Error Amp Output: External connection for additional compensation and current sharing.
EAIN 2A I Error Amp Inverting Input: Connection for the main Vout feedback divider tap
VDIFF 3A O Independent Amplifier Output: Active only when module is enabled.
VSN 4A I Independent Amplifier Inverting Input: If unused connect in unity gain.
VSP 5A I Independent Amplifier Non-Inverting Input: If unused connect to SGND.
VOUT 6A,B Power Direct VOUT Connect: for per-cycle internal clamp node and feed-forward ramp.
PGND Block2 Power Power Ground: VIN and VOUT power returns.
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PI332x-00 Common Electrical Characteristics
Specifications apply for –40°C < TINT < 120°C, VIN = 24V, EN = High, unless otherwise noted.
[a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3” dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal.[d] Refer to Output Ripple plots.[e] Refer to Load Current vs. Ambient Temperature curves.[f] Refer to Switching Frequency vs. Load current curves.
Parameter Symbol Conditions Min Typ Max Unit
Differential Amp
Open Loop Gain [b] 96 120 140 dB
Small Signal Gain-Bandwidth [b] 5 7 12 MHz
Input Offset 0.5 1 mV
Common Mode Input Range –0.1 2.5 V
Differential Mode Input Range 2 V
Input Bias Current –1 1 µA
Output Current –1 1 mA
Maximum VOUT IVDIFF = –1mA 4.85 V
Minimum VOUT IVDIFF = –1mA 20 mV
Capacitive Load Range for Stability [b] 0 50 pF
Slew Rate 11 V/µs
PWRGD
VOUT Rising Threshold VPG_HI% 78 84 90 % VOUT_DC
VOUT Falling Threshold VPG_LO% 75 81 87 % VOUT_DC
PWRGD Output Low VPG_SAT Sink = 4mA 0.4 V
VDR
Voltage Setpoint VVDR VIN_DC > 10V 4.9 5.05 5.2 V
External Loading IVDR See Application Description for details 0 2 mA
Enable
High Threshold VEN_HI 0.9 1.0 1.1 V
Low Threshold VEN_LO 0.7 0.8 0.9 V
Threshold Hysteresis VEN_HYS 100 200 300 mV
Pull Up Voltage Level for Source Current
VEN_PU 2 V
Pull Up Current IEN_PU_POS VIN > 8V, excluding tFR_DLY 50 µA
Output Voltage Ripple VOUT_AC IOUT = 20A, COUT = 12 x 47µF, 20MHz BW [d] 55.7 mVP-P
Output Current IOUT_DC[e] 0 20 A
Current Limit IOUT_CL Typical current limit based on nominal 230nH inductor. 24 A
Maximum Array Size NPARALLEL[b] 3 Modules
Output Current, Array of 2 IOUT_DC_ARRAY2 Total array capability, [b] see applications section for details 0 [g] A
Output Current, Array of 3 IOUT_DC_ARRAY3 Total array capability, [b] see applications section for details 0 [g] A
Protection
Input UVLO Start Threshold VUVLO_START 12.9 13.8 V
Input UVLO Stop Hysteresis VUVLO_HYS 0.85 1.21 1.75 V
Input UVLO Response Time 1.25 µs
Input OVLO Stop Threshold VOVLO 44 47 V
Input OVLO Start Hysteresis VOVLO_HYS Hysteresis active when OVLO present for at least tFR_DLY 0.5 0.9 1.3 V
Input OVLO Response Time tf 1.25 µs
Output Overvoltage Protection, Relative
VOVP_REL Above set VOUT 20 %
Output Overvoltage Protection, Absolute
VOVP_ABS 6.7 7.37 V
[a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3” dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal.[d] Refer to Output Ripple plots.[e] Refer to Load Current vs. Ambient Temperature curves.[f] Refer to Switching Frequency vs. Load current curves.[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
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Specifications apply for –40°C < TINT < 120°C, VIN = 24V, EN = High, unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Unit
Timing
Switching Frequency fs
[f] While in Discontinuous Conduction Mode (DCM) only, SYNCI grounded
564 600 636 kHz
Fault Restart Delay tFR_DLY 30 ms
Synchronization Input (SYNCI)
Synchronization Frequency Range fSYNCI–50% and +10% relative to set switching frequency (fS), while in DCM operating mode only. [c] and [f] 300 660 kHz
SYNCI Threshold VSYNCI 2.5 V
Synchronization Output (SYNCO)
SYNCO High VSYNCO_HI Source 1mA 4.5 V
SYNCO Low VSYNCO_LO Sink 1mA 0.5 V
SYNCO Rise Time tSYNCO_RT 20pF load 10 ns
SYNCO Fall Time tSYNCO_FT 20pF load 10 ns
Soft Start, Tracking and Error Amplifier
TRK Active Range (Nominal) VTRK 0 1.4 V
TRK Enable Threshold VTRK_OV 20 40 60 mV
TRK to EAIN Offset VEAIN_OV 40 80 120 mV
Charge Current (Soft Start) ITRK 30 50 70 µA
Discharge Current (Fault) ITRK_DIS VTRK = 0.5V 8.7 mA
TRK Capacitance, Internal CTRK_INT 47 nF
Soft-Start Time tSS CTRK_EXT = 0µF 0.6 0.94 1.6 ms
Error Amplifier Transconductance GMEAO 7.6 mS
PSM Skip Threshold PSMSKIP 0.8 V
EAIN Capacitance, Internal CEAIN_INT 56 pF
Error Amplifier Output Impedance ROUT[b] 1 MΩ
Internal Compensation Capacitor CHF 56 pf
Internal Compensation Resistor RZI 5 kΩ
[a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3” dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal.[d] Refer to Output Ripple plots.[e] Refer to Load Current vs. Ambient Temperature curves.[f] Refer to Switching Frequency vs. Load current curves.
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Load Current (A)
Effic
ienc
y (%
)
2 4 6 8 10 12 14 16 18 2082
86858483
87888990919293949596
14V 24V 42VVIN:
Figure 1 — System efficiency, nominal trim, board temperature = 25ºC
Load Current (A)
Pow
er D
issi
patio
n (W
)
12345678
91011
2 4 6 8 10 12 14 16 18 20
14V 24V 42VVIN:
Figure 4 — System power dissipation, nominal trim, board temperature = 25ºC
Load Current (A)
Pow
er D
issi
patio
n (W
)
12345678
91011
2 4 6 8 10 12 14 16 18 20
14V 24V 42VVIN:
Load Current (A)
Effic
ienc
y (%
)
2 4 6 8 10 12 14 16 18 20
86858483
87888990919293949596
14V 24V 42VVIN:
Figure 2 — System efficiency, low trim, board temperature = 25ºC
Figure 23 — Output voltage ripple: nominal line, nominal trim, 50% load, COUT = 12 x 47µF ceramic
Figure 22 — Output short circuit, nominal line
Figure 20 — Output voltage ripple: nominal line, nominal trim, 100% load, COUT = 12 x 47µF ceramic
Figure 21 — Switching frequency vs. load, nominal trim Figure 24 — System thermal specified operating area: max IOUT at nominal trim vs. temperature at locations noted
Figure 25 — Output current vs. VEAO, nominal trim Figure 28 — Start up from VIN applied, nominal line, nominal trim, typical timing, PI3325 shown
Figure 26 — Small signal modulator gain vs. VEAO, nominal trim Figure 29 — Start up from EN, VIN pre-applied, nominal line, nominal trim, typical timing, PI3325 shown
Figure 27 — rEQ_OUT vs VEAO, Nominal Trim
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Functional Description
The PI332x-00 is a family of highly integrated ZVS Buck regulators. The PI332x-00 has an output voltage that can be set within a prescribed range shown in Table 1. Performance and maximum output current are characterized with a specific external power inductor (see Table 3).
For basic operation, Figure 30 shows the connections and components required. No additional design or settings are required.
ENABLE (EN)
EN is the enable pin of the converter. The EN Pin is referenced to SGND and permits the user to turn the regulator on or off. The EN default polarity is a positive logic assertion. If the EN pin is left floating or asserted high, the converter output is enabled. Pulling EN pin below VEN_LO with respect to SGND will disable the regulator output.
Remote Sensing
If remote sensing is required, the PI332x-00 product family is equipped with a general purpose op-amp. This amplifier can allow full differential remote sense by configuring it as a differential follower and connecting the VDIFF pin to the EAIN pin.
Soft Start
The PI332x-00 includes an internal soft-start capacitor to control the rate of rise of the output voltage. See the Electrical Characteristics Section for the default value. Connecting an external capacitor from the TRK pin to SGND will increase the start-up ramp period. See, “Soft Start Adjustment and Track,” in the Applications Description section for more details.
Output Voltage Selection
The PI332x-00 output voltage is set with REA1 and REA2 as shown in Figure 30. Table 1 defines the allowable operational voltage ranges for the PI332x-00 family. Refer to the Output Voltage Set Point Application Description for details.
Output Current Limit Protection
The PI332x-00 has a current limit protection, which prevents the output from sourcing current higher than the regulator’s maximum rated current. If the output current exceeds the Current Limit (IOUT_CL) for 1024μs, a slow current limit fault is initiated and the regulator is shutdown which eliminates output current flow. After Fault Restart Delay (tFR_DLY), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the excessive load is removed.
The PI332x-00 also has short circuit protection which can rapidly stop switching to protect against catastrophic failure of an external component such as a saturated inductor. If short-circuit protection is triggered the PI332x-00 will complete the current cycle and stop switching. The module will attempt to soft start after Fault Restart Delay (tFR_DLY).
Input Undervoltage Lockout
If VIN falls below the input Undervoltage Lockout (UVLO) threshold, but remains high enough to power the internal bias supply, the PI332x-00 will complete the current cycle and stop switching. The system will soft start once the input voltage is reestablished and after the Fault Restart Delay.
Figure 30 — ZVS Buck with required components
ZVS BuckVIN VS1
VOUTVSPVSN
VDIFF
EAINEAO
COMP
TRK
PGNDVDRSYNCOSYNCIPWRGDENTESTxSGND
CIN
REA2
L1
REA1
CCOMP
COUT
VIN VOUT
Table 1 — PI332x-00 family output voltage ranges
DeviceOutput Voltage
Nominal Range
PI3325-00-LGIZ 5.0V 4.0 – 6.5V
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Input Overvoltage Lockout
If VIN exceeds the input Overvoltage Lockout (OVLO) threshold (VOVLO), while the controller is running, the PI332x-00 will complete the current cycle and stop switching. If VIN remains above OVLO for at least tFR_DLY, then the input voltage is considered reestablished once VIN goes below VOVLO-VOVLO_HYS. If VIN goes below OVLO before tFR_DLY elapses, then the input voltage is considered reestablished once VIN goes below VOVLO. The system will soft start once the input voltage is reestablished and after the Fault Restart Delay.
Output Overvoltage Protection
The PI332x-00 family is equipped with output Overvoltage Protection (OVP) to prevent damage to input voltage sensitive devices. If the output voltage exceeds VOVP-REL or VOVP-ABS, the regulator will complete the current cycle and stop switching. The system will resume operation once the output voltage falls below the OVP threshold and after Fault Restart Delay.
Overtemperature Protection
The PI332x features an overtemperature protection (OTP), which will not engage until after the product is operated above the maximum rated temperature. The OTP circuit is only designed to protect against catastrophic failure due to excessive temperatures and should not be relied upon to ensure the device stays within the recommended operating temperature range. Thermal shut down terminates switching and discharges the soft-start capacitor. The PI332x will restart after the excessive temperature has decreased by 30ºC.
Pulse Skip Mode (PSM)
PI332x-00 features a Pulse Skip Mode (PSM) to achieve high efficiency at light loads. The regulators are set up to skip pulses if EAO falls below a PSM threshold (PSMSKIP). Depending on conditions and component values, this may result in single pulses or several consecutive pulses followed by skipped pulses. Skipping cycles significantly reduces gate drive power and improves light load efficiency. The regulator will leave PSM once the EAO rises above the Pulse Skip Mode threshold.
Variable Frequency Operation
Each PI332x-00 is preprogrammed to a base operating frequency, with respect to the power stage inductor (see Table 2), to operate at peak efficiency across line and load variations. At low-line and high-load applications, the base frequency will decrease to accommodate these extreme operating ranges. By stretching the frequency, the ZVS operation is preserved throughout the total input line voltage range therefore maintaining optimum efficiency.
Thermal Characteristics
Figure 31(a) and 31(c) thermal impedance models that can predict the maximum temperature of the hottest component for a given operating condition. This model assumes that all customer PCB connections are at one temperature, which is PCB equivalent Temperature TPCB °C.
The SiP model can be simplified as shown in Figure 31(b). which assumes all PCB nodes are at the same temperature.
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Figure 31 — PI332x-00 thermal model (a), SiP simplified version (b) and inductor thermal model (c)
(a)
(b)
SiP Power Dissipa�on PDSIP (W)
Thermal Resistance SiP Case TopθINT-TOP
oC / W
Thermal Resistance SiP PCB Equivalent
θINT-PCBoC / W
Case Top Temperature
TTOPoC
SiP PCB Common Temperature
TPCBoC
Maximum SiP Internal Temperature TINT ( oC )
(c)
Inductor Power Dissipa�on PDIND (W)
Thermal Resistance Inductor Case Top
θINT-TOPoC / W
Inductor Case TopTemperature
TTOPoC
Maximum Inductor Internal Temperature TINT ( oC )
θINT-LEAD1oC / W
TVS1oC
TVOUToC
Thermal Resistance Inductor Case Bo�om
θINT-BOTTOMoC / W
Inductor Case Bo�omTemperature
TBOTTOMoC
Thermal ResistancesInductor PCB Pads
Inductor PCB Pad Temperatures
θINT-TABoC / W
θINT-LEAD2oC / W
TTABoC
SiP Power Dissipa�on PDSiP (W)
Thermal Resistance SiP Case Top
θINT-TOPoC / W
θINT-VINoC / W
SiP Case Top Temperature
TTOPoC
TVINoC
Maximum SiP Internal Temperature TINT ( oC )
θINT-VS1oC / W
TVS1oC
θINT-PGND1oC / W
TPGND1oC
θINT-PGND2oC / W
TPGND2oC
θINT-SGNDoC / W
TSGNDoCSiP PCB Pad
Temperatures
Thermal ResistancesSiP PCB Pads
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θINT-TOP
the thermal impedance from the hottest component inside the SiP to the top side
θINT-PCB
the thermal impedance from the hottest component inside the SiP to the customer PCB, assuming all pins are at one temperature.
θINT-VIN
the thermal impedance from the hottest component inside the SiP to the circuit board VIN pads.
θINT-VS1
the thermal impedance from the hottest component inside the SiP to the circuit board VS1 pads.
θINT-PGND1
the thermal impedance from the hottest component inside the SiP to the circuit board at the PGND1 pads. PGND1 is pins 12A-K.
θINT-PGND2
the thermal impedance from the hottest component inside the SiP to the circuit board at the PGND2 pads . PGND2 is pins 2F-J, 3F-J, 4C-J, 5B-J and 6C-K.
θINT-SGND
the thermal impedance from the hottest component inside the SiP to the circuit board at the SGND pads.
The following equation can predict the junction temperature based on the heat load applied to the SiP and the known ambient conditions with the simplified thermal circuit model:
+
+1
θINT-TOP
1θINT-PCB
TTOP
θINT-TOP
TPCB
θINT-PCBPD +
(1)TINT =
Product System
Simplified SiP Thermal Impedances
Detailed SiP Thermal Impedances
θINT-TOP
(°C / W)θ
INT-PCB(°C / W)
θINT-TOP
(°C / W)θ
INT-VIN(°C / W)
θINT-VS1
(°C / W)θ
INT-PGND1(°C / W)
θINT-PGND2(°C / W)
θINT-SGND
(°C / W)
PI3325 110 1.7 110 3.4 4.8 33 33 91
Table 2 — PI332x-00 SiP thermal impedance
Where the symbol in Figure 31(a) and (b) is defined as the following:
θINT-TOP
the thermal impedance from the hot spot to the top surface of the core.
θINT-BOT
the thermal impedance from the hot spot to the bottom surface of the core.
θINT-TAB
the thermal impedance from the hot spot to the metal mounting tab on the core body, if applicable.
θINT-LEAD1
the thermal impedance from the hot spot to one of the mounting leads. Since the leads are the same thermal impedance, there is no need to specify by explicit pin number.
θINT-LEAD2
the thermal impedance from the hot spot to the other mounting lead.
Where the symbol in Figure 31(c) is defined as the following:
Table 3 — Inductor effective thermal model parameters
Product System
Inductor Part Number
Effective Thermal Impedances
θINT-TOP
(°C / W)
θINT-LEAD1,
θINT-LEAD2
(°C / W)θINT-BOTTOM
(°C / W)
θINT-TAB
(°C / W)
PI3325 FP2207R1-R230-R 11 9.4 6.8 N/A
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SiP Power Dissipation as Percentage of Total System Losses
Figure 32 — PI3325-00-LGIZ
Sip
Dis
sipa
tion
(% T
otal
Los
s)
40
50
60
70
80
90
100
14 18 22 26 30 34 38 42
VIN (V) <5% Rated Load 30% Rated Load
100% Rated Load
IOUT:
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Application Description
Output Voltage Set Point
The PI332x-00 family of buck regulators utilizes VREF, an internal reference for regulating the output voltage. The output voltage setting is accomplished using external resistors as shown in Figure 33. Select R2 to be at or around 1kΩ for best noise immunity. Use Equations 2 and 3 to determine the proper value based on the desired output voltage.
Soft Start Adjust and Tracking
The TRK pin offers a means to increase the regulator’s soft-start time or to track with additional regulators. The soft-start slope is controlled by an internal capacitor and a fixed charge current to provide a Soft-Start Time tSS for all PI332x-00 regulators. By adding an additional external capacitor to the TRK pin, the soft-start time can be increased further. The following equation can be used to calculate the proper capacitor for a desired soft-start time in excess of tSS:
where tTRK is the soft-start time and ITRK is a 50µA internal charge current (see Electrical Characteristics for limits).
In applications such as battery or super-capacitor charging where
the load is pre-biased, the PI332x can start into output voltages up to the externally applied trim setpoint, or the minimum absolute OVP, provided the value does not exceed 6V. For start up into loads which are pre-biased above 6V, an ORing FET or equivalent sub-circuit is required to decouple the buck output from the load during start up. In any application with a CV type load, the regulator must be configured in a constant-current mode of operation; the built-in current limit is a fault protection only.
There is typically either proportional or direct tracking implemented within a design. For proportional tracking between several regulators at start up, simply connect all PI332x-00 device TRK pins together. This type of tracking will force all connected regulators to start up and reach regulation at the same time (see Figure 34a).
For Direct Tracking, choose the PI332x-00 with the highest output voltage as the master and connect the master to the TRK pin of the other PI332x-00 regulators through a divider (Figure 35) with the same ratio as the slave’s feedback divider.
All connected PI332x-00 regulator soft-start slopes will track with this method. Direct tracking timing is demonstrated in Figure 34b. All tracking regulators should have their Enable (EN) pins connected together to work properly.
Figure 33 — External resistor divider network
EAO
EAIN
+-
VREF
CEAIN-INT
COMP
VOUT
RZI
CHF
R1
R2
VOUT = VREF •R1 + R2
R2(2)
R1 = R2 •VOUT – VREF
VREF
(3)
where VREF = VEAIN
(4)CTRK = (tTRK • ITRK ) – CTRK_INT
Figure 34 — PI332x-00 tracking responses
VOUT
1
VOUT
2
Master VOUT
VOUT
2
(a)
(b)
t
Figure 35 — Voltage divider connections for direct tracking
Master VOUT
R1
R2
SGND
TRK
PI332x
Slave
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Inductor Pairing
The PI332x-00 utilizes an external inductor. This inductor has been optimized for maximum efficiency performance. Table 3 details the specific inductor value and part number utilized for each PI332x-00.
The same inductor model may have different effective thermal impedances, depending on the model ZVS Buck paired with it. The thermal impedances are used in a virtual model of the inductor to estimate the maximum temperature, and the location of the maximum temperature may vary depending on the ZVS Buck model that the inductor is used with. This is because the effective thermal impedances are not only based on the geometry and materials used in the inductor, but include how the inductor power dissipation is distributed among core losses, DC copper losses, and AC copper losses. This distribution is dependent on the ZVS Buck model that uses the inductor.
Parallel Operation
Multiple PI332x-00 can be connected in parallel to increase the output capability of a single output rail. When connecting modules in parallel, each EAO, TRK, and EN pin should be connected together. EAIN pins should remain separated, each with an REA1 and REA2, to reject noise differences between different modules' SGND pins. Current sharing will occur automatically in this manner so long as each inductor is the same value. Refer to the Electrical Characteristics table for maximum array size and array rated output current. Current sharing may be considered independent of synchronization and/or interleaving. Modules do not have to be interleaved or synchronized to share current.
Due to the high output current capability of a single module and Critical Conduction Mode (CrCM) occurring at approximately 50% rated load, interleaving is not supported.
Use of the PI332x-00 SYNCI pin is practical only under a limited set of conditions. Synchronizing to another converter or to a fixed external clock source can result in a significant reduction in output power capability or higher than expected ripple.
Filter Considerations
The PI332x-00 requires low impedance ceramic input capacitors (X7R/X5R or equivalent) to ensure proper start up and high frequency decoupling for the power stage. The PI332x-00 will draw nearly all of the high frequency current from the low impedance ceramic capacitors when the main high side MOSFET(s) are conducting. During the time the MOSFET(s) are off, the input capacitors are replenished from the source. Table 6 shows the recommended input and output capacitors to be used for the PI332x-00 as well as per capacitor RMS ripple current and the input and output ripple voltages. Table 5 lists the recommended input and output ceramic capacitors manufacturer and part numbers. It is very important to verify that the voltage supply source as well as the interconnecting lines are stable and do not oscillate.
Input filter case 1 — Inductive source and local, external, input decoupling capacitance with negligible ESR (i.e., ceramic type):
The voltage source impedance can be modeled as a series RLINE LLINE circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified:
Where rEQ_IN can be calculated by dividing the lowest line voltage by the full load input current. It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance, Equation 6. However, RLINE cannot be made arbitrarily low otherwise Equation 5 is violated and the system will show instability, due to an under-damped RLC input network.
Figure 36 — PI332x-00 parallel operation
ZVS Buck#1
VIN VS1VOUT
VSPVSN
VDIFF
EAINEAO
COMP
TRK
PGNDVDRSYNCOSYNCIPWRGDENTESTxSGND
CIN_1 COUT_1
REA2_1
L1_1
REA1_1
CCOMP_1
VIN
EN
ZVS Buck#2
VIN VS1VOUT
VSPVSN
VDIFF
EAINEAO
COMP
TRK
PGNDVDRSYNCOSYNCIPWRGDENTESTxSGND
CIN_2 COUT_2
L1_2
CCOMP_2
VIN
EN
VOUT
VOUT
TRKEAO
TRKEAO
REA2_2
REA1_2
( )LLINE
CIN_INT + CIN_EXT • rEQ_IN
RLINE > (5)
(6)RLINE << rEQ_IN
Table 3 — PI332x-00 Inductor pairing
Product System
Value (nH)
MFR Part NumberMax Operating
Temp (°C)
PI3325 230 Eaton FP2207R1-R230-R 125
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Input filter case 2 — Inductive source and local, external input decoupling capacitance with significant RCIN_EXT
ESR (i.e., electrolytic type):
In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor LLINE.
Notice that the high performance ceramic capacitors CIN_INT within the PI332x-00 should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be:
Equation 8 shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT) – the system will be under-damped and may even become destabilized. As noted, an octave of design margin in satisfying Equation 7 should be considered the minimum. When applying an electrolytic capacitor for input filter damping the ESR value must be chosen to avoid loss of converter efficiency and excessive power dissipation in the electrolytic capacitor.
VDR Bias Regulator
The VDR internal bias regulator is a ZVS switching regulator that resides internal to the PI332x-00 SiP. It is intended primarily to power the internal controller and driver circuitry. The power capability of this regulator is sized for the PI332x-00, with adequate reserve for the application it was intended for.
It may be used for as a pullup source for open collector applications and for other very low power uses with the following restrictions:
1. The total external loading on VDR must be less than IVDR.
2. No direct connection is allowed. Any noise source that can disturb the VDR voltage can also affect the internal controller operation. A series impedance is required between the VDR pin and any external circuitry.
3. All loads must be locally decoupled using a 0.1μF ceramic capacitor. This capacitor must be connected to the VDR output through a series resistor no smaller than 1kΩ, which forms a low-pass filter.
Additional System Design Considerations
1. Inductive loads: As with all power electronic applications, consideration must be given to driving inductive loads that may be exposed to a fault in the system which could result in consequences beyond the scope of the power supply primary protection mechanisms. An inductive load could be a filter, fan motor or even excessively long cables. Consider an instantaneous short circuit through an un-damped inductance that occurs when the output capacitors are already at an initial condition of fully charged. The only thing that limits the current is the inductance of the short circuit and any series resistance. Even if the power supply is off at the time of the short circuit, the current could ramp up in the external inductor and store considerable energy. The release of this energy will result in considerable ringing, with the possibility of ringing nodes connected to the output voltage below ground. The system designer should plan for this by considering the use of other external circuit protection such as load switches, fuses and transient voltage protectors. The inductive filters should be critically damped to avoid excessive ringing or damaging voltages. Adding a high-current Schottky diode from the output voltage to PGND close to the PI332x-00 is recommended for these applications.
2. Low-voltage operation: There is no isolation from an SELV (Safety-Extra-Low-Voltage) power system. Powering low voltage loads from input voltages as high as 60V may require additional consideration to protect low voltage circuits from excessive voltage in the event of a short circuit from input to output. A fast TVS (transient voltage suppressor) gating an external load switch is an example of such protection.
Table 5 — Recommended input and output capacitor components
Table 6 — Recommended input and output capacitor quantity and performance at nominal line, nominal trim.
(7)rEQ_IN > RCIN_EXT
LLINE
CIN_INT • RCIN_EXT
< rEQ_IN (8)
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Layout Guidelines
To optimize maximum efficiency and low noise performance from a PI332x-00 design, layout considerations are necessary. Reducing trace resistance and minimizing high-current loop returns along with proper component placement will contribute to optimized performance.
A typical buck converter circuit is shown in Figure 37. The potential areas of high parasitic inductance and resistance are the circuit return paths, shown as LR below.
The path between the COUT and CIN capacitors is of particular importance since the AC currents are flowing through both of them when Q1 is turned on. Figure 38, schematically, shows the reduced trace length between input and output capacitors. The shorter path lessens the effects that copper trace parasitics can have on the PI332x-00 performance.
When Q1 is on and Q2 is off, the majority of CIN’s current is used to satisfy the output load and to recharge the COUT capacitors. When Q1 is off and Q2 is on, the load current is supplied by the inductor and the COUT capacitor as shown in Figure 39. During this period CIN is also being recharged by the VIN. Minimizing CIN loop inductance is important to reduce peak voltage excursions when Q1 turns off. Also, the difference in area between the CIN loop and COUT loop is vital to minimize switching and GND noise.
Figure 40 illustrates the tight path between CIN and COUT (and VIN and VOUT) for the high AC return current. The PI332x-00 evaluation board uses a layout optimized for performance in this way.
COUT
CIN
VIN
Figure 37 — Typical buck regulator
COUT
VIN C
IN
Figure 38 — Current flow: Q1 closed
COUT
VIN C
IN
Figure 39 — Current flow: Q2 closed
PGND
PGND
VOUTVS1
VIN
Inductor
ZVS-Buck SIP
Figure 40 — Recommended layout for optimized AC current within the SiP, inductor, and ceramic input and output capacitors
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D1
E1
L
D1E1
L
Recommended receiving footprint for PI332x-00 10 x 14mm package. All pads should have a final copper size of 0.55 x 0.55mm, whether they are solder-mask defined or copper defined, on a 1 x 1mm grid. All stencil openings are 0.45mm when using either a 5mil or 6mil stencil.
Recommended PCB Footprint and Stencil
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Package Drawings
AA1A2
LDE
D1E1
L1
AND POSITION
A A2
A1
D
E
A
M A
M
DETAIL A
D1
E1
DETAIL B
G E D A
1
L
L1
DETAIL B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
1
K
SOLDER MASK
3
METALLIZEDPAD
SEATING PLANE
DETAIL A
M A
M
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Revision History
Revision Date Description Page Number(s)
1.0 12/05/17 Initial release n/a
1.1 02/06/18 Added typical start-up waveforms 14
1.2 07/25/19Updated figure 28Removed note
1420
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