Pixel Sensor Development for High Radiation Environments ...€¦ · P-Epitaxial Layer P-Substrate...

Konstantinos Moustakas (ESR-5)

[email protected]

Pixel Sensor Development for High Radiation Environments in Modern CMOS Technologies

This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 675587

STREAM Final Conference, Geneva – 16/09/2019 [email protected]

Outline

E R-5


Outline Introduction

ATLAS-LHC

ATLAS-HL-LHC

Inner Outer

Time resolution [ns] 25 25

Particle Rate[kHz/mm2]

1000 10 000 1000

Fluence [neq/cm2] 2x1015 2x1016 1,5x1015

Ion. Dose [Mrad] 80 > 1000 80

Baseline hybrid approach: Separate sensor and electronics

optimization

Planar Pixel Sensor

New advancements in imaging CMOS processes: HV/HR

Enhanced charge collection & radiation tolerance

• High radiation level:

• NIEL up to 1016 neq/cm2s sensor

• TID up to 1Grad electronics

• SEU/SET memory, time critical blocks (CDR/PLL)

• High particle rate:

• occupancy, bandwidth high density, high speed data link

I. II.

LHC HL - LHC


Outline Introduction TJ - Monopix

TJ-Monopix1 & MALTA Submission

Wafer dicing, wire bonding

Mini-MALTA Submission

Mini-MALTA Characterization

11/2016 07/2017 01/2018 01/2018 - Present 08/2018 01/2019 - Present

TJ-Monopix2 Design

Present

TJ-Monopix1 & MALTA Characterization

TJ-Monopix1 & MALTA Design

TJ - Investigator first results (mod process)

Q2 2016

Vmin• Small sensor capacitance (Cd)

• Key for high performance• Small collection electrode

𝑷 ≈𝑺

𝑵≈𝑸

𝑪𝒅𝑪𝒅 ≤ 𝟑𝒇𝑭

• Radiation tolerance challenge• Modified process• Small pixel size

• Design challenges• Compact, low power FE• Compact, efficient R/O

DMAPS in TJ 180 nm: Concept Large scale demonstrator chip development

• MALTA• Asynchronous readout

• TJ-Monopix• Synchronous column-drain

R/O architecture

• Mini - MALTA: sensor fixes, improved efficiency

• TJ-Monopix2: Improved full-scale DMAPS

Talks by: ESR 8, 9 ,12

W. Snoeys et al. https://doi.org/10.1016/j.nima.2017.07.046

https://doi.org/10.1016/j.nima.2017.07.046



LE

TE

Data

Bu

s

BC

ID

To

ke

n

Rea

dF

ree

ze

Addr Pixel Logic

LE

TE

Addr

Column Controller

Trigger Memory

PreampPreamp

BC ID (delayed)Trig.Trig. Req.

PIXEL COLUMN

PERIPHERY

• Why Column Drain Readout Architecture for CMOS DMAPS?✓ Simple implementation

✓ Reduced area✓ Reduced crosstalk

✓ Fast readout with ToT capability✓ Has been used in the ATLAS b-layer (FE-I3)✓ Simulated to be capable of handling the ATLAS

HL-LHC L4 expected hit rate ≅ 𝟏𝟎𝟎 MHz/cm2

Simulation with monte carlo data & TJ-Monopix pixel paremeters

LE

TE

Da

ta B

us

BC

ID

To

ke

n

Re

ad

Fre

eze

Addr Pixel Logic

LE

TE

Addr

Column Controller

Trigger Memory

PreampPreamp




PIXEL COLUMN

PERIPHERY

1. BCID time stamp distribution

LE

TE

Da

ta B

us

BC

ID

To

ke

n

Re

ad

Fre

eze

Addr Pixel Logic

LE

TE

Addr

Column Controller

Trigger Memory

PreampPreamp




PIXEL COLUMN

PERIPHERY2. HIT information is recorded in

the pixel• Leading Edge: Hit ToA• Trailing Edge: ToT• Pixel Address

LE

TE

Da

ta B

us

BC

ID

To

ke

n

Re

ad

Fre

eze

Addr Pixel Logic

LE

TE

Addr

Column Controller

Trigger Memory

PreampPreamp




PIXEL COLUMN

PERIPHERY

3. A busy token flag is raisedand propagated throughthe column

LE

TE

Da

ta B

us

BC

ID

To

ke

n

Re

ad

Fre

eze

Addr Pixel Logic

LE

TE

Addr

Column Controller

Trigger Memory

PreampPreamp




PIXEL COLUMN

PERIPHERY4. The readout sequence is

initiated by the R/Ocontroller using the Readand Freeze signals

LE

TE

Da

ta B

us

BC

ID

To

ke

n

Re

ad

Fre

eze

Addr Pixel Logic

LE

TE

Addr

Column Controller

Trigger Memory

PreampPreamp




PIXEL COLUMN

PERIPHERY5. The pixel that has been hit and

has the highest priority (tokenarbitration) transmits dataover the common column bus

LE

TE

Da

ta B

us

BC

ID

To

ke

n

Re

ad

Fre

eze

Addr Pixel Logic

LE

TE

Addr

Column Controller

Trigger Memory

PreampPreamp




PIXEL COLUMN

PERIPHERY

6. Hit data is stored in the triggermemory (if one exists) or else iscontinuously transmitted afterarbitration over different columns



• 1x2cm2 size, 224x448 matrix, 36x40μm2 pixel size• No trigger memory, 4x40Mhz data transmission• Low power: < 𝟏𝟑𝟎 𝒎𝑾/𝒄𝒎𝟐 (70 𝒎𝑾/𝒄𝒎𝟐Analog, 𝟔𝟎𝒎𝑾/𝒄𝒎𝟐 Digital)

• 4 Flavors, that include:• Low-power column data-bus• Leakage compensation• AC-coupled pixels (front-side biasing)

P-well N-well P-well

Deep P-well (PWELL)

Spacing

P-Epitaxial Layer

P-Substrate


Deep P-well (PWELL)

Spacing NMOS PMOS

N- implant

NMOS

N- implant

CE

VCE

“HV” biasing option, up to 50V using custom MOM capacitor



40 μm

36

μm

• LE, TE are stored• Hit event is latched by the

Trailing Edge

• Hit flag is set (if no freeze)• Busy token is propagated

• The pixel is ready & has priority• Internal READ assertion → Data transmission

1

2

3

In-pixel R/O Logic

In-pixel Memory

2x2 Pixel Layout

1 2 3



2x2 Pixel LayoutAmplifier Discriminator“PMOS” reset

ToT

(ns)

Qin (e-)

Leakage Comp.

• Low power, compact FE, similar to MALTA (see previous talk)

• Optimized speed (25ns BX)• “PMOS” reset for linear ToT• Development of new leakage

compensation circuit40 μm

36

μm



• TJ-Monopix is fully operational

• 10 min 55Fe source capture• Both Mn Kα and Kβ X-ray peaks

are detected

• Now ENC (due to low Cd)• Simulation in agreement with

measurement

Analog capture

Digital readout

ToT (x25ns)

Voltage (V)

# H

its

# H

its

55Fe Spectrum

HIT

pro

bab

ility

Qin (e-)

HIT

pro

bab

ility

Measurement

Simulation

Single Pixel Injection Scan

6,5

Ke

VK

β

5,9

Ke

VK

α

FWHM≅55e-



• Full “PMOS” flavor injection scan, 25088 pixels• Threshold mean ≅ 270e-, total dispersion ≅ 31e-

• < 0.5% masked pixels, noise occupancy << 10-6 hits/BX • ENC mean ≅ 11e-, dispersion ≅ 0.8 e-

Threshold ENC

RTS noise



Qin (e-) Qin (e-)

# P

ixe

ls

“HV” flavorThreshold

“HV” flavorENC

55FE Spectrum, “HV” flavor

ToT (x25ns)

# C

ou

nts

UnirradiatedIrradiated

(1015 neq/cm-2)

Threshold 350 e- 570 e-

ENC 17 e- 23 e-

Efficiency 97% 70%

Efficiency, unirradiated

X (μm)X (μm)

Y (

μm

)

Y (

μm

)

Efficiency, irradiated

More details: Talk by ESR-6 tomorrow

• TJ-Monopix chips were irradiated@ JSI: Up to to 1015 neq/cm2 NIEL, 1 Mrad background TID

Charge trapping under the DPW

High Threshold

Efficiency drops by 27%

Improve charge collection

Decrease Min. Threshold

TJ-Monopix2



TJ-Monopix1 TJ-Monopix2

Chip Size 1x2 cm2 (224x448 pix) 1x2 cm2 (512x512 pix)

Pixel size 36 × 40 µm2 33.04 × 33.04 µm2

Noise ≅11 e- < 10e- (improved FE)

LE/TE time stamp 6-bit 7-bit

Threshold Dispersion

≅ 30 e- rms< 20 e- rms

(improved FE + tuning)

Minimum threshold

≅ 300 e- <150 e-

In-time threshold ≅ 400e- 250 - 300 e-

Efficiency ≅ 70 % (irradiated) > 95% (irradiated)

* Expectations

• Periphery, I/O features:• Command decoder, Trigger memory• 2x320 Mb/s LVDS, 8/10b encoding

• Submission: End of 2019

P-well N-well

Deep P-well (PWELL)

Spacing

P-Epitaxial Layer

P-Substrate


Deep P-well (PWELL)

Spacing NMOS PMOS

N- implant N- implant

CE

VCE

P-well N-well

Spacing

P-Epitaxial Layer

P-Substrate


Spacing NMOS PMOS

N- implant N- implant

CE

VCE

Deep P-well (PWELL) Deep P-well (PWELL)

• 7 “biasing” settings (threshold tuning)

• Charge collection improvement (tested with Mini-MALTA)• Process modification “fixes”, pixel size reduction• Lateral field enhancement

1

• Threshold reduction: FE improvement• Critical device optimization: ↑ Gain, ↓ ENC, ↓ σTHR

• In-pixel threshold tuning DAC, masking2

More details: Talk by ESR 9

More details: Talks by ESR 8, 12



40 μm

36

μm

33.04 μm

33

.04

μm

TJ-Monopix1 PixelTJ-Monopix2 Pixel

• Small pixel size• Aggressive routing, coupling• Single-ended transmission

• Long column• Significant RC effect

Long column impact to BCID

Correction by HIT delayLow-Voltage SRAM cellCurrent-mode bit line sensing (single-ended)

“Voltage mode”

“Current mode”

Vo

ltag

eC

urr

en

t


Outline Introduction TJ - Monopix RD53B CDR

RD53B Floorplan

• RD53 collaboration Joint effort between ATLAS and CMS

• TSMC 65nm technology: Logic density, TID tolerance

• New pixel readout FE chip for the HL-LHC

The RD53A chip bonded on the SSC PCB

• RD53A demonstrator chip has been fabricated successfully characterized• RD53B (pre-production chip) submission: Q4 2019

Jitt

er

Spe

cifi

cati

on

s • Command input to RD53B (160 Mbps)• Expected jitter: Jrms ≤ 5 ps• Will be increased by distortion and ISI from the

low mass cable

• RD53B data output (1.28 Gbps)• LPGBT automatic mode: Jrms ≤ 10 ps, Jpk-pk ≤ 60 ps• LPGBT manual mode: Jrms ≤ 40 ps, Jpk-pk ≤ 200 ps

• RD53A CDR: Locking, Jitter issues new RD53B CDR design



• Robust and reliable locking mechanism• PLL startup switch to CDR operation• Bang-bang alexander PD + Rotational FD

• Stable and good quality link: Low jitter• Loop optimization using behavioral models

with extracted block parameters

• Tolerance to TID effects• Large MOSFET devices, increased biasing

currents (VCO)• Simulation using radiation models

• Tolerance to SEE effects• TMR divider, counter and configuration• Bang-Bang loop (reduced PD and CP

sensitivity)

RD53B CDR Design Strategy



• PLL Mode startup• Input: 010101….



• “Normal” CDR Mode• Input: RD53 command



• Area: 1mm x 0.25mm, designed with RD53B floorplan in mind• 300pF metal filter capacitor, M1 – M5, M6 grid on top for shielding • Each block is placed in a separate deep n-well with common PSUB to reduce substrate noise effects• In RD53B 2mm x 0.3mm is dedicated for CDR, extra space filled with decoupling



• A dedicated test chip (2x2 mm2) was built to characterize the RD53B CDR performance, submitted 08/18• The environment, data path and supporting blocks are as close as possible to RD53B. It includes:

• LVDS command receiver• Serializer, PRBS generator & CML GTX fast data link cable driver• Bandgap, biasing DAC’s• Triplicated SPI configuration



Power consumption

Sample number Power [mW]

1 7.2

2 7.2

Simulation 6 (just CDR)

VCO tuning curve measurement

Measurement setup based on BDAQ53 DAQ

• First measurements conducted to verify the VCO tuning range and power consumption

• Very good agreement with simulation (slight shift due to temperature)



• Startup reliability was measured by power cycling and repeating the startup procedure (100 iterations)

• Different temperature, power supply conditions• No issues observed, the RD53B CDR is capable of successfully locking down to 0.9V

power supply voltage (1.2V nominal)

Set VDD

Power cycle

Send training pattern for 1 s

Send PRBS5 CMD

Check if VCO is at 1.28 GHz &

REC_CMD=CMD

Discharge LPF

X 1

00

Ch

ange V

DD

Lock success rate [%]

Temp.Sample number

VDD [V]

0.8 0.85 0.9 0.95 1.0 1.05 1.1 1.15 1.2 1.25

Room 1 0 0 100 100 100 100 100 100 100 100

Room 2 0 0 98 100 100 100 100 100 100 100

-20 °C 2 0 0 100 100 100 100 100 100 100 100



• Command Input: 160 Mb/s training pattern (0101…) (5ps Jrms)• Output: VCO CLK/2 (640 MHz), 1m SMA cables

• Command Input: 160 Mbps PRBS5 (5ps Jrms)• Output: 1.28 Gb/s PRBS15, 1m SMA cables

𝐉𝐑𝐌𝐒 = 𝟓 𝐩𝐬

𝐉𝐏−𝐏 = 𝟒𝟎 𝐩𝐬

𝐉𝐑𝐌𝐒 = 𝟔. 𝟕 𝐩𝐬

𝐉𝐏−𝐏 = 𝟓𝟕 𝐩𝐬



• Bonn X-ray machine• DUT kept at -14 °C• Chip 4 cm away from tube• X-ray tube biased with 40 kV• Using Al filter

Step duration [h]

Dose rate [Mrad/h]

TID after step [Mrad]

15 0.25 3.76

2 1.9 7.4

127 4.6 591

10.5 0.8 600

X-ray Irradiation Plan

Lock success rate [%]

TID [Mrad]VDD [V]

0.8 0.85 0.9 0.95 1.0 1.05 1.1 1.15 1.2

0 – 0.26 0 100 100 100 100 100 100 100 100

0.26 – 193 0 0 100 100 100 100 100 100 100

193 – 591 0 0 0 100 100 100 100 100 100

591 – 600 0 0 0 0 100 100 100 100 100

• Even at 600 Mrad the RD53B CDR was able to startup with 100% success down to 1V power supply voltage



• The VCO gets “slower” with radiation damage, higher VCTRL is required and gain is degrades by 6-10%• Even at 600 Mrad there is adequate VCTRL headroom (720mV @ 1.28GHz)• The radiation model used in the design process predicted an even higher shift

• The output 1.28 Gb/s PRBS15 data stream jitter (Jp-p) was measured for PRBS5 command input with 5ps Jrms

• A 13% increase was observed that is mainly attributed to duty cycle distortion caused by CMOS pre-driver of the CML stage

VCO Control Voltage @ 1.28 GHz Output Jitter, 5ps PRBS5 In, PRBS15 Out


Outline Introduction TJ - Monopix RD53B CDR Conclusion

Two major research developments in the framework of the HL-LHC: Design and Characterization

• TJ-Monopix1: CMOS DMAPS large scale demonstrator following a novel small collector electrode approach

• Fully functioning prototype with integrated standalone “column-drain” readout architecture

• High analog performance (low power, fast timing), High granularity

• RD53B CDR: CDR/PLL for the RD53 ATLAS/CMS readout chip that will be installed at the phase-II upgrade

• Robust phase locking mechanism, 100% startup success

• Low jitter: good quality, low BER data link

• Fully functional after irradiation to 600 Mrad TID

• Current Research: Design of TJ-Monopix2

• The efficiency drop after irradiation of TJ-Monopix1 has been understood and solutions are being implemented• Submission of a full scale prototype with improved sensor, front end and smaller pixel size (end of 2019)


Outline Introduction TJ - Monopix RD53B CDR Conclusion

• More than 10 Presentations in Dissemination and Outreach activities

• Participation in major conferences• Talks at the ATLAS upgrade week & Pixel

design reviews

• Two scientific publications as main author• 10.1109/NSSMIC.2017.8533114• 10.1016/j.nima.2018.09.100

• Co-authored 10 articles in scientific journals

Thank you!

https://doi.org/10.1109/NSSMIC.2017.8533114

https://doi.org/10.1016/j.nima.2018.09.100

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