December 2015

PowerDRC/LVS Overview

PV background2

Physical verification is a step in microchip design. A layout of new device is checked to find and fix errors before actual manufacturing

The check is done by special EDA software - Design Rule Check (DRC) tool

An error missing at this stage may lead to creating a malfunctioning microchip and cost multi-million dollar losses for semiconductor manufacturers

Another major factor is time. Physical verification is one of the longest stages in the designing process It could takes several days for DRC tool to make just one iteration on modern super large microchips.

Corporate background3

Fastest & most accurate DRC technology and cloud-ready PV-flow

Founded in 2009. Privately held by KM Core (www.kmcore.com)

World-wide presence: Headquarters, R&D and technical support team resides in Kiev, Ukraine Sales & Marketing provided by TEKSTART LLC ( US, Taiwan, Israel, Japan)

PowerDRC/LVS capabilities4

DRC - design rules checking in layout

LVS – layout vs schematic verification

NVN – schematic vs schematic netlists comparison

XOR – layout vs layout by layer comparison

QuickDiff – diffing of layout versions to ensure ECO (engineering change order)

Filler layers generation

Support of antenna rules, density rules, pads, latches and other special rules

Graphical diagnostics with visualization of violations, discrepancies and shorted nets

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Patent-pending One-Shot™ processing

WindowScanning

UnleashUsing

Core technology

Strip mode processing for multi CPU

One-shot ProcessingUnique, encapsulation of

rules, layers & operations

PowerDRC™6

The main idea of PowerDRC/LVS is to speed up the process of physical verification by using One-Shot™ processing that delivers maximum CPU efficiency per one rule check

Silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm

Fastest and most accurate native flat DRC engine on the market

Predictable performance and behavior

Multi-CPU and hierarchical operations for linear performance gain

Parallel processing 7

PowerDRC benefits from parallel processing of:independent groups of rules (blocks)independent parts of layout (strips)

Parallel tasks may be run in multi-CPU mode on:a single hostmulti host grids like Platform LSF or SGE/OGENEFELUS cloud servicecustom cloud platform

Scalability proven on 2, 4, 6, 8, 12, 16, 24, 32, 48 CPUs

QuickDiff purpose

When a small change is made to a design near tapeout (often called ECO - engineering change order),

the design team may want to make sure - by means of XOR - that that was the only change made.

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PowerDRC™- Performance on 1-32x CPUs9

PowerDRC™- Performance on 1-32x CPUs (cont.)10

Performance of XOR operation in multi-CPU mode 11

Performance of QuickDiff + XOR 12

PowerLVS™13

Supports 7 effective comparison algorithms applied automatically and dynamically depending on the type of encountered blocks to ensure accuracy at the highest level of performance

Silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm

Predictable performance and behavior

Supports extraction of array instances to get up to 10x performance increase

Provides Multi-label, Floating-label, Hier cells and Open nets reports

Graphical debug is provided by PowerRDE and Short Finder utility

PowerLVS performance

Process node: 40nmLP; Hard IP: analog, logic gates and memory cells, ~ 380 million physical gates

Extraction of all devices: 11 hrs + 5 more hrs for output

Comparison: 12.5 hrs

Total LVS time: 28.5 hrs using 1 CPU core and 128 GB of RAM

Process node: 4um Hard IP: LCD 1280x960: analog IP and pixel cell array, ~ 50 million physical gates

Extraction of all devices: 2 min

Comparison: 1 hr and 50 min

Total LVS time: 1 hr and 52 min using 1 CPU and 8 GB of RAM

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Unique features

Advantages from using efficient FLAT engine natively Extremely efficient usage of hardware resources (RAM, cache, CPU load) Predictable performance

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Run and Debug Environment (PowerRDE™)16

Allows user to:

Adjust DRC and LVS run parameters

Save them in a run configuration file

Read a saved configuration

Run PowerDRC/LVS

View run progress

Review results

Debug violations, etc.

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Short Finder utility (graphical LVS debug component)17

Suggests a short location Shorted net polygons in a

table format Allows to assign label for

selected polygon Allows to mark a polygon as

‘deleted’ Recalculates the shortest path Interactive work in KLayout

editor

PowerDRC/LVS integration18

PowerDRC/LVS has interoperability with:

Cadence Virtuoso – CDBA and OA

SpringSoft Laker – Native

AWR Analog Office - Native

KLayout – Native

Symica DE – Native

Synergic Partnership (AWR) AWR Corporation has been POLYTEDA OEM partner since 2009. PowerDRC/LVS was integrated with Analog Office suite and is available for all Analog

Office customers. More information and demo video are available at:

www.polyteda.com/products-demowww.awrcorp.com/products/analog-office

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Supported technology nodes20

Sign-off

Availableupon request

UMC IHP Silanna AMS L Foundry

40nm: G & LP65nm: LL, LP & SP180nm: G & LL

250nm130nm 250nm (GX, FX) S35 150nm

MOSIS SCMOS

500-180nm

To check availability of other rule sets please contact POLYTEDA directly

To get hand-on experience

Order trial version of PowerDRC/LVS online at: www.polyteda.com/contact-us/submitrequest

PowerDRC/LVS 2.2 – is officially available from POLYTEDA since Dec 21, 2015

• Try cloud version of PowerDRC/LVS as SaaS on NEFELUS Cloud - www.nefelus.com

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Licensing details• PowerDRC/LVS is licensed on per-CPU basis separately for DRC and LVS

• PowerRDE GUI cockpit requires its own license (PowerRDE)

• Filler layers generation feature (PowerFIL) requires its own license

• XOR and QuickDiff operations (PowerLVL) require their own license

• Licensing employs FlexLM license manager

• Licenses are bound either to hostID (MAC-address) or disk serial number or dongle flexID

• Usual license duration is 1 year

• Licenses are valid for all minor version updates but not for major ones, i.e. license for 2.2 is valid for 2.2.1 but not for 2.3

• Short-term licenses may be granted for trial purposes

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Support policy• POLYTEDA is ready to provide offline (email) technical support based on

additional Support and Maintenance Agreement (available).

• In urgent cases a hot fix version may be sent to the customer as soon as the issue is solved.

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