Programable Logic Devices - Amazon Web...

Programable Logic Devices

William Sandqvist [email protected]

In the 1970s programmable logic circuits called programmable logic device (PLD) was introduced. They are based on a structure with an AND-OR array that makes it easy to implement SOP expression

PLD structure


f 1

AND plane OR plane

Input buffers

inverters and

P 1

P k

f m

x 1 x 2 x n

x 1 x 1 x n x n

Programmable Logic Array (PLA)


f

P 1

P 2

f

x 1

x 2 x 3

OR plane

AND plane

P 3

P 4

Both AND and OR arrays are programmable

Programmable Array Logic (PAL)


Only the AND array is programmable

f 1

P 1

P 2

f 2

x 1 x 2 x 3

AND plane

P 3

P 4

Register output


In the earlier PLD circuits there were • combinatorial outputs

• register outputs (output with a flip-flop)

For each circuit there were a fixed number of combinational and register outputs

To increase flexibility the macrocell where you could choose if an output would be a combinatorial or a register output was introduced.

Macrocels ia a PLD


f 1

To AND plane

D Q

Clock

Select Enable

Flip-flop

With a programmable multiplexer one can select the type of output

PAL


Programing of PLDs


Complex PLDs (CPLD)


PLD were quite small (PALCE 22V10 had 10 flip-flops)

For bigger programmable circuits a structure consisting of several PLD-like block was developed.

CPLD (MAX)


CPLD structure


PAL-like block

I/O b

lock

PAL-like block

I/O block

PAL-like block

I/O b

lock

PAL-like block

I/O block

Interconnection wires

Programing with JTAG


Modern CPLDs (and FPGAs) can be programmed by downloading programming information via a cable Download will usually use a standard port: JTAG-port

(a) CPLD in a Quad Flat Pack (QFP) package

Printed circuit board

To computer

(b) JTAG programming

JTAG programing


You can program the chips when they are soldered to the circuit board - from inside the programmer you can select which chip you want to program with the JTAG connector.

FPGA chips


CPLD:s are based on the AND-OR array, and it becomes difficult to make really large circuits FPGA (Field Programmable Gate Array) circuits using a different concept based on logical blocks

FPGA-structure


LUT-LookUp-Table


0/1

0/1

0/1

0/1

x1

x2

f

Two-input LUT

Programmable cells 1

0

1

0

1

0

A LUT with n inputs can realize all combinational functions with n inputs. The usual size in an FPGA is n=4

Ex. LUT for XOR-gate


0

1

1

0

x1

x2

f

Two-input LUT

1

0

1

0

1

0

2 1

1 1 00 1 11 0 10 0 0

x x f

Logic block in FPGA


Out

D Q

Clock

Select

Flip-flop In 1 In 2 In 3

LUT

A logic block of an FPGA consists of a LUT, a flip-flop, and a mux to select register output.

Interconnexion matrix in FPGA


0 1 0 0

0 1 1 1

0 0 0 1

x 1

x 2

x 2

x 3

f 1

f 2

f 1 f 2

f

x 1

x 2

x 3 f

• Blue cross: connection is programmed • Black cross: connection is not programmed

DE2 University Board


Cyclone II EP2C35 FPGA – Datorteknik-course

Cyclone II logic element


Cyclone II Family


(3) Total Number of 18x18 Multipliers DE2

Stratix III Family


DE3 Board

Multiple processors on an FPGA


Nios II

Nios II

Very powerful multiprocessor systems can be created on an FPGA!

• Nios II is a so-called 'soft-processor' (32-bit) which can be implemented on an Altera FPGA • Today's FPGAs are so large that multiple processors can fit on a single FPGA chip

ASIC


• An ASIC (Application Specific Integrated Circuit) is a circuit that is madi in a semiconductor factory • In a full custom integrated circuit you in principle tailors the whole circuit • In an ASIC have certain work steps already been made to reduce design time and cost

ASIC, gate array


In an Gate Array the gates (or transistors) are allready on the silicon.

ASIC, gate array


One only creates links between inputs, gates, and outputs

f 1

x 1

x 3

x 2

Comparison ASIC, FPGA


Initial Cost Cost per part Performance Fabrication Time

FPGA Low High Low Short

Gate Array (ASIC)

Standard Cell (ASIC)

High Low High Long

Design Trade-Offs


Design Time

Performance

Microprocessor

Programmable Logic

Gate Array

Standard Cell

Full Custom


Sekvenskretsar med VHDL


NEXT STATE DECODER STATE REGISTER

OUTPUT DECODER

State

Clk

Input- signals

Output- signals

Moore-machine

Model a State Machine in VHDL


• In a Moore-machine we have three blocks

– Next-state-decoder – Output-decoder – State-register

• These blocks execute in parallel

Quickie Question …


which logic gate corresponds to the following VHDL code










Processes in VHDL


• An architecture in VHDL can consist of several processes • Processes are executed in parallel • A process is written as a sequential program

Moore-machine processes


• For a Moore-machine, we can create three processes

– Next-state-decoder – Output-decoder – State-register

Internal signals


• Moore-machine contains internal signals

– Next state – Present state

• Theese signals are declared in the architecture-description

The vending machine in VHDL

COIN RECEIVER

COIN_PRESENT

GT_1_EURO

EQ_1_EURO

LT_1_EURO

DEC_ACC

CLR_ACC

SYSTEM CONTROL

DROP

DROP_READY

CHANGER_READY

RETURN_10_CENT

DROP BOTTLE

COIN RETURN


ACCUMU-LATOR

We use bottle vending machine (system control) from last lecture as a concrete VHDL example

Vending machine entity


COIN_PRESENT

GT_1_EURO

EQ_1_EURO

LT_1_EURO

DEC_ACC

CLR_ACC

SYSTEM CONTROL

DROP

DROP_READY

CHANGER_READY

RETURN_10_CENT

Reset_n

Clk

ENTITY Vending_Machine IS PORT ( -- Inputs

coin_present : IN std_logic; gt_1_euro : IN std_logic; eq_1_euro : IN std_logic; lt_1_euro : IN std_logic; drop_ready : IN std_logic; changer_ready : IN std_logic; reset_n : IN std_logic; clk : IN std_logic; -- Outputs

dec_acc : OUT std_logic; clr_acc : OUT std_logic; drop : OUT std_logic; return_10_cent : OUT std_logic); END Vending_Machine;

Clk and Reset (active low) is also needed!

Vending machine architecture


• The architecture describes the function of the vending machine • We define

– internal signals for present and next state – three processes for next-state-decoder, output-decoder and state-register

State diagram

(a) Wait for coin input (b) Register the coin (c) Coin is registered (3 cases)

(d) Drop bottle (e) Reset sum (f) Return 10 Cent (g) Decrement sum with 10

Cent


Internal signals


• We need to create a data type for the internal signal • Since we describe the states we use an enumeration type

with values a,b,c,d,e,f,g • We declare a variable for the current state

(current_state) and one for next state (next_state)

ARCHITECTURE Moore_FSM OF Vending_Machine IS TYPE state_type IS (a, b, c, d, e, f, g); SIGNAL current_state, next_state : state_type; BEGIN -- Moore_FSM …

We want to keep our "clever” state encoding


• If we do not specify the encoding state then the synthesis tool chooses the coding.

• We can force it to a specific encoding with attributes (NOTE Attributes are dependent on synthesis tool and thus not portable!)

ARCHITECTURE Moore_FSM OF Vending_Machine IS TYPE state_type IS (a, b, c, d, e, f, g); -- We can use state encoding according to BV 8.4.6

-- to enforce a particular encoding (for Quartus) ATTRIBUTE enum_encoding : string; ATTRIBUTE enum_encoding OF state_type : TYPE IS "000

001 011 110 111 100 101"; SIGNAL current_state, next_state : state_type; BEGIN -- Moore_FSM …

Block schematic


D

D

D

Next State Decoder

COIN_PRESENT

LT_I_EURO

EQ_I_EURO

GT_I_EURO

DROP_READY

CHANGER_READY

A

B

C

DA

DB

DC

A

B

C

Output Decoder

DROP

CLR_ACC

DEC_ACC

Clk

Clk

Clk

RETURN_I0_CENT

• Signals A,B,C describes present state • Signals DA, DB, DC describes next state



which statemachine corresponds to the VHDL code


Quickie Question … which statemachine corresponds to the VHDL code

Next-State-Decoder


• Next-State-Decoder describes as a process • Sensitivity list contains all input signals that 'activates' the process

Next-State-Decoder


• Usually the sensitivity list contains all the inputs to the process

NEXTSTATE : PROCESS (current_state, coin_present, gt_1_euro, eq_1_euro, lt_1_euro, drop_ready, changer_ready) –- Sensitivity List

BEGIN -- PROCESS NEXT_STATE …

Next-State-Decoder


• We now use a CASE statement to describe for each state conditions for the transition from a state to the next state

… CASE current_state IS WHEN a => IF coin_present = '1' THEN next_state <= b; ELSE next_state <= a; END IF; WHEN b => IF coin_present = '0' THEN next_state <= c; ELSE next_state <= b; END IF;

Next-State-Decoder


• We can simplify the description, by specifying a default value for the next state

… next_state <= current_state; CASE current_state IS WHEN a => IF coin_present = '1' THEN next_state <= b; END IF; WHEN b => IF coin_present = '0' THEN next_state <= c; END IF; …

It is important that we specify all options for the next_state signal. Otherwise, we implicitly gets an expression next_state <= next_state which will genarate a latch!

Next-State-Decoder


• We end the CASE statement with a WHEN OTHERS statement. Here we specify that we should go to a certain state (a) if we end up in a unspecified state

…

WHEN g => next_state <= c; WHEN OTHERS => next_state <= a; END CASE; END PROCESS NEXTSTATE;

Output-decoder


• Output-decoder is described as a own process

• Sensitivity list contains only the state as outputs only depend on the state

Output-decoder

OUTPUT : PROCESS (current_state) BEGIN -- PROCESS OUTPUT drop <= '0'; clr_acc <= '0'; dec_acc <= '0'; return_10_cent <= '0'; CASE current_state IS WHEN d => drop <= '1'; WHEN e => clr_acc <= '1'; WHEN f => return_10_cent <= '1'; WHEN g => dec_acc <= '1'; WHEN OTHERS => NULL; END CASE; END PROCESS OUTPUT;


State register


• The State register is modeled as a synchronous process with asynchronous reset (active low)

CLOCK : PROCESS (clk, reset_n) BEGIN -- PROCESS CLOCK IF reset_n = '0' THEN -- asynchronous reset (active low) current_state <= a;

ELSIF clk'event AND clk = '1' THEN -- rising clock edge current_state <= next_state;

END IF; END PROCESS CLOCK;

Mealy-machine?


• A Mealy machine can be modeled in the same way as the Moore machine

• The difference is that output-decoder is also dependent on the input signals

• Process modeling outputs also need to have the inputs in the sensitivity list!

More about VHDL


• The sample code for bottle vending machine available on the course website

• Look at the study material of "VHDL synthesis" on the course website

• Both Brown/Vranesic- and the Hemert-book includes code samples


Laboratory - codelock • Task: to write VHDL code for a code lock that opens with the code "the last four digits of your Social Security number”. • Hint: a VHDL "template" for a simplified code lock that opens with the code "number one".


Code lock – classic example!


Moore – ”Gedanken Experiments” on Sequential Machines 1956

Code lock 0-1-0 That example is listed in Moore's classic essay from 1956.

Template-program


Templat-program for a simplified code lock that opens for the code "1", a little bit too easy it seems ...!

Power On/Off

Open the lock with your Social!


• Now it's time to rewrite the VHDL code to open the lock for the last four digits of your social security number!

(If you are preparing code for your Social Security number, then two in a lab group contribute with one half each of the code in the lab).


Date post:	13-Jun-2020
Category:	Documents
Upload:	others
View:	4 times
Download:	0 times

Programable Logic Devices - Amazon Web...

Documents