Prototype of SRAM by Sergey Kononov, et al.

1. Project Overview

The goal of the project is to create a SRAM memory layout that provides maximum utilization of the space on the 1.5 by 1.5 mm chip. Significant portion of that space is dedicated to the I/O Pads, living approximately 1 mm^2 for the memory array and the control circuitry. The size of the basic memory cell is, for the most part, dictated by the type of the technology used to produce the chip. The calculation provided in the memory array block description have shown that in the most optimal case up to 4 Kbits of the 6-transistor CMOS memory cells can be fitted on the space provided, living very limited amount of space for the rest of the logic gates that need to be placed on the chip. The Figure 1.1 shows the locations of each of the blocks on the chip.

Figure1.1 Block Locations The chip features 4 kilobytes of the SRAM CMOS memory. The logical representation of the memory array has 32 rows and 128 columns. In order to fit all of the memory cells on the chip 32 of these columns have been placed on the chip as a separate block. Besides memory storage the chip contains several other blocks that provide functionality necessary to access and maintain the data stored in the array. The memory read operation is self-timed. This is accomplished through the use of the timing pulse that is generated every time the new address is put on the data lines. It is used by the precharging block as well as the control blocks to determined when it is time to initialize the necessary transactions. The precharging block is responsible for the equalizing and the precharging of the bit lines of the chosen column to 5V. Once the column is pre-charged the proper row is selected and the data becomes available to the associated sense amplifiers. At every transaction 8 bits of the memory are accessed and fed into the 8 sense amplifiers, which allow to read the data as soon as the voltage difference on the lines becomes appropriate. This voltage difference is significantly smaller then would be required if

the data was accessed without the use of the sense amplifiers. This acquired speed-up is the primarily reason for the use of the sense amplifiers on the chip. The access of the columns and rows is done using row and column decoders. In order to minimize the required space, the corresponding decoders are implemented 2 and 3-bit predecoders, the outputs of which are fed into 2-bit AND gates located at the foundation of the memory array.

2. Block description

Memory Cell

The memory cell layout and schematic are provided in the figures 2.1 and 2.2 accordingly.

Figure 2.1 Memory Cell Layout There are two main concerns when designing the memory cell. One is to guarantee that once the precharging is done and the pass transistors of the cells are enabled that initial voltage spike on the negative bit line does not cause the transition of the cell into the opposite state. Such situation is prevented through the sizing of the n-transistors and pass-transistors of the memory cells in a way that guarantees that the voltage across the pmos transistors never drops below threshold value. To achieve this, their width-to-length(W/L) sizes has to satisfy the values calculated using the formulas below. These formulas are the result of the equating of the currents of the involved transistors at the critical stages. Once the required ratio for the nmos to pass transistor sizing is established it becomes impossible to write to the cell by puling the zero bit line up, which means that the writing to the cell is done by pulling the positive bit line down. In order for this to happen the proper ratio has to exist between the W/L sizes of the pass and pmos transistors of the cell. The second set of

calculation establishes the required ratio. The results below were calculated using following values: V_DD=5V; V_TN=0.66; V_TP=-0.915; k_n/k_p=2 The ratio of the W/L values of the pass transistors to nmos transistors of the memory cell has to be: (W/L)_pass/(WL)_nmos < (2(V_DDV_TN)-3V_TN^2)/(V_DD-2V_TN)^2=0.39 The ratio of the W/L values of the pmos transistor to the pass transistors has to be: (W/L)_pmos/(WL)_pass < k_n'/k_p' *(2(V_DDV_TN)-3V_TN^2)/(V_DD+V_TP)^2=0.63 As a result the W/L ratio PMOS transistors has to be approximately ¼ of the NMOS transistors: P_MOS=0.63*0.39=1/4NMOS The values picked in order to achieve required ratios were: NMOS PMOS PASS 1800/600 900/1200 900/750

Figure 2.2 Memory Cell Schematic Due to the crucial role of the proper sizing of all involved transistors in the whole datapath, the testing of the memory cells and associated peripheral cells was done in a form of a single test. The description of this test and the associated waveform is provided in the document after the description of all of the cells used in the test. Precharger.

The significant portion of the read and write cycles is dedicated to the decoding of the address. Once the address of the cell is decoded the reading and writing process starts. Without sense amplifiers in order to guarantee that the proper values were read, the end of these cycles would have to be delayed to guarantee that the bit lines reach the rail voltages. The sense amplifiers allow to avoid such delays through amplification of the difference between the bit lines. In order to do this reliably and fast, they require the input voltages to be equalized to some predetermined value. This functionality in the circuitry is provided by the precharger cells. The schematic and the layout of that cells are presented in the Figures 2.3 and 2.4 accordingly.

Figure 2.3

Figure 2.4 Sense amplifier.

This block provides 2 stage amplification. During first stage the input voltages are first equalized and shifted to the 2.5 voltage value. The circuit is timed(using global pulse), so that once the minimum required voltage difference is reached the evaluations goes into the second stage, during which this difference is amplified and outputted to the tristate buffer. The schematics of the both stages and the corresponding layout is presented in the figures 2.5 and 2.6.

Figure 2.5

Figure 2.6

Test of the memory cells.

The testing of the circuitry has been done using single

memory, sense amplifier, pass transistor and the precharger cells. In order to do the proper simulation the capacitance is attached to the bit line inputs. The capacitance is placed to account for the parasitic capacitance resulting from the connection of the bit line to 32 cells that each memory column is made of. The testing is done in two stages: during first stage the ability of the set-up to change the value in the circuit by pulling the positive line down is tested. Then the ability to output proper(inverted) values is tested. The resulting waveform is presented in Figure 2.10. Figures 2.7 – 2.9 show the schematic, layout and test bench circuits used for simulation. Due to the fact that the result of the schematic is dependent upon the sizing of the transistors and the fact that the minimum size that could be set up on the schematic is greater then actual values used in the circuit, only the simulation of the extracted layout was done.

Figure 2.7 Schematic of the circuit for the test of memory cell.

Figure 2.8. Layout of the test circuit for the memory cell

Figure 2.9 Test bench for the memory cell

Figure 2.10 Timing of the memory cell On the timing diagram the following waveforms are shown: • Pulse is the signal that is used to control the precharging and equalizing stage of the reading cycle. When the pulse cycle is high the precharging and equalizing of the bit lines is done. In order to ensure the proper reading of the data stored in the memory cell, this pulse has to be wide enough to guarantee that both of the bit lines(Bl and Bln) are equal to 5V. The time it takes to precharge bit line from zero to 5 V establishes the minimum width of the pulse.

• Delayed pulse is the signal that is used to control each of the sense amplification cells. It is created inside each of the sense amplification cells. It provides the same functionality for the sense amplification cells as the pulse signal for the precharging cell. It provides a

way to slightly delay the sense reading of the values on the bit lines.

• The stored and stored_b signals are the actual voltages inside the memory cell.

• The Bl and Bln are the signals that correspond to the bit lines. These lines are connected to the memory cell through the pass transistors that are controlled by the word line. They are also connected to the i/o lines through the column pass transistor.

• I/O signals are the signals that are produced on the lines connecting memory cell with the sense amplifier and the write circuitry. The writing is done by pulling one of this lines down and the other line up and enabling the column pass transistors. In the test the column pass transistors are always enabled.

• The output signal it the value that is used to drive the tristate output buffer. During the high stage of the delayed pulse the output is at high Z value. When the sensing occurs it is established to the inverse of the stored value.

• The output_b signal is the actual signal generated inside the sense amplifier. It drives the output signal described above. As can be seen from the waveform during the precharge stage it is shifted to the 2.5V volts. Once the pulse goes low the sense amplifier drives it to the inverse of the voltage stored in the memory cell. At this point it is connected to the output circuitry.

The 5-bit line and 4-bit column decoders are both implemented using 2 stages: the stage of predecoders and the stage 2-bit AND gates. The column decoder uses 2 2-bit predecoders, and the line decoder uses one 2-bit and one 3-bit predecoder. In the case of the line decoder the outputs from the predecoder cells are used to drive the associated word lines of the memory array, while the column decoders are activated in groups of eight and are used to drive the pass cells located in the pass block that control access between the bit lines of the columns of the memory array and the i/o lines.The following pictures contain the layouts and schematics of the decoder circuitry cells

Figure 2.11 Pass gate

Figure 2.12 Pass gate

Figure 2.13 2 2-bit predecoders

Figure 2.14 2 2bit predecoders

Figure 2.15 One 3-bit predecoder

Figure 2.16 One 3-bit predecoder Pulse generator

One of the main components of the control circuitry is the pulse generator. It is implemented using 8 xor gates that are connected to two inputs:the address lines and their delayed equivalent. Once the signal on any of the address lines changes the output of the xor gates goes high due to the fact that it takes time for the delayed signal to catch up with the primary value. The circuitry is presented in the Figure 2.17.

Figure 2.17 Pulse generator In order to prevent the unnecessary switching when the chip is not selected the input from the input address buffer into the pulse generator is maintained at the same value through the use of the intermediate latch, controlled by the chip enable signal. This way as soon as the chip is enabled the pulse will be generated if the address is different from previous cycle when the chip was enabled. Otherwise the valid values are already stored in the output buffer and no additional action is required except for enabling the output buffer.

3. Dual Port SRAM

SRAM cell redesigned for dual port operation. The dual port consists of two read ports and one write port. The six transistor SRAM cell is replaced by a positive edge triggered D-flip flop with two tri-state inverting buffers. Overall memory consists of 32X32 array, accessible in 8bit data width (total 128 bytes).

Figure 2.18 Rev 1 SRAM cell consisting of a positive edge triggered D-flip flop with two tri-state inverting buffers.

Figure 2.19 Rev 2 SRAM cell consisting of a positive edge triggered D-flip flop with two tri-state inverting buffers.

Figure 2.20 Rev 3 SRAM cell consisting of a positive edge triggered D-flip flop with two tri-state inverting buffers.

Figure 2.21 Rev 3 SRAM cell data switching simulation.

Figure 2.22 Complete 32X32 dual port SRAM block.