Puneet AroraESCUG, 09

Abstraction Levels in SoC Modelling

Agenda

• Introduction• Abstraction levels• Terminologies• Implementation• Implementation Example• Adaptors• Conclusion and References

Introduction

• SoC Modelling: Software model / Executable representation of SoC

• Various use cases– Functional verification– Early s/w development– HW/SW partitioning, resource sharing– Architecture Exploration– Verify memory and bus designs– Cycle accurate h/w models

Abstraction Levels

• Required to cater to different use-cases• Control amount and frequency of

communication• Control simulation speed and accuracy• SystemC signal: RTL• TLM2.0 (Payload / Phases): Higher

abstractions

Terminologies ..

Popular Terminology• Programmer's View: functional correct, fast

models for embedded software development• Architect's View: explore design features

like bus-width, memory organization, die-area etc

• Verification View: cycle-accurate modelling, simulate actual timing and memory requirements, closest to RTL

Terminologies ..

OCP-IP modelling kit• Introduces four levels

– TL1: cycle accurate modelling, supports all dataflow signals of OCP through extensions and phases

– TL2/TL3: approximate timed modelling, fewer extensions and phases

– TL4: loosely timed modelling, phases are not used, blocking transport mechanism is used

– Compatible with OSCI BP wherever possible

Terminologies ..

OSCI TLM2.0• Provides generic framework for memory

mapped busses• Defines a Base protocol• Provides infrastructure for extending base

protocol to model at different abstraction levels

• Recommends two coding styles• Abstraction levels not well defined

Terminologies ..

STARC TLM Guideline• Uses timing and data granularity axis to

define abstraction levels• Combines points on these axis to define

Abstraction levels• Timing : UnTimed, ApproximatelyTimed,

CycleAccurate• Data : TRansaction, BusPhase, BusCycle,

BusSignal

Source: STARC TL Guideline, 2nd Edition

Terminologies ..

Terminologies ..

Timing Accuracy

Data Granularity

Mapping of the OSCI Abstraction Levels

Untimed Approximate CycleAccurateTransaction OSCI LTBusPhase OSCI ATBusCycleBusSignal

Terminologies ..

Timing Accuracy

Data Granularity

Mapping of the OCP Abstraction Levels

Untimed Approximate CycleAccurateTransaction OCP TL4BusPhase OCP TL3BusCycle OCP TL2BusSignal OCP TL1

Source: STARC TL Guideline, 2nd Edition

Mapping UseCases

Implementation

• By extending OSCI TLM2.0– blocking and non_blocking transport APIs– blocking can use wait, temporal decoupling– non_blocking uses phases and PEQs– Extend protocol for lower abstraction levels or

bus specific features• typedef generic_payload• Define new payload• Define new phases

Implementation ExampleOCP-IP Modelling Kit

• Support for advanced communication protocols at various abstraction levels– Built on top of TLM2.0– Payload extensions– Phase extensions– Master Sockets with memory management for

payload and extensions– Slave sockets with PEQ for timing annotations

Implementation Example ..

OCP-IP TL1• Cycle accurate using extensions & phases• Support for individual beats of burst transfers• Different from OSCI BP

– Enforces END_X for every BEGIN_X– Allows phase overlap– Disallows use of TLM_COMPLETED(no

shortcuts)– Modules synchronized at boundary of same

clock and supports non-default timing

Implementation Example ..

OCP TL2

• Used for Approximate Timed coding styles• Acts as bridge between TL1 and TL3• Phases like TL1 but exact clocking is

optional• Used for intra-burst timing

Implementation Example ..

OCP TL3

• Data phases are not used• Some extensions are not used as intermediate

timing is not captured• Maximum interoperability with OSCI BP• Different bursts are indistinguishable as data

transfer completes in one go• Synchronized at interface method calls

Implementation Example ..

TL3 example :phases same as OSCI BP

Implementation Example ..

TL3 example :request_accept_delay and response latency is zero

Implementation Example ..

OCP TL4

• loosely timed coding style of OSCI BP• Phases are not used• Transfer completes when b_transport returns• Detail timing behavior not modelled

Implementation Example ..

Adapters

TL3 Slave

TL3 Slave

RTL Master

TL1 Module

InterConnect

Models at different abstraction levels are to be connected-Skip intermediate phases by combining them-May need to arrange data within themselves

TL1 Master to TL3 SlaveTL1 M TL3 SAdapter

Beg_RespBeg_Resp

Beg_Req

Beg_Data

Beg_Data

Beg_Req

End_Resp

End_Resp

Adapters

TL4 M

TL4 Master to TL3 SlaveTL3 SAdapter

b_transportnb_tr ( beg_req)

nb_tr ( beg_resp)

wait()

Return b_transport

Adapters

Conclusion

• OSCI TLM2.0 can be extended to implement different abstraction levels. OCP-IP TLM Kit extends TLM2.0 for OCP-IP bus protocol.

• Models at different abstraction levels can be easily connected using adapters

References

• OSCI TLM2.0 User Manual• OCP-IP TLM Modelling Kit Manual• STARC TLM Guide, 2nd Edition

Questions

SoC Modelling Services (SystemC, TLM2.0)info@circuitsutra.com