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RADIATION-HARDENED CMOS DEVICES FOR LINEAR CIRCUIT APPLICATIONS

By

T. J. Sanders and K. A. Ports

ABSTRACTIn the past, the use of MOS devices in a radiation en-vironment has normally been restricted to applicationsrequiring a 15 volt power supply or less. This paperdiscusses a new process for manufacturing high-voltage(30 volt) radiation-hardened CMOS devices for linearcircuit applications. Devices have been fabricatedwhich demonstrate hardness above 2 Mrads(Si). Thispaper also discusses necessary controls and designrules for this process.

INTRODUCTIONA linear-application MOS device differs from its digi-tal-application counterpart in that it must sustaindrain-to-source voltages of 30 volts or higher withoutbreaking down (as opposed to about 15 volts for digitaldevices). This requirement affects both the design ofthe device and the process by which it must be fabrica-ted. Therefore, there is no a priori guarantee thatthe excellent total dose hardness attainable with digi-tal MOS devices can be reproduced in devices designedand built for linear applications.The goal of the program discussed in this paper hasbeen to investigate the hardness of linear MOS devicesand to formulate device and process design rules forthe fabrication of radiation-hardened, linear MOSfield effect transistors. The resultant devices wereto have BVDSS 30 volts, and resistance to totaldose gamma irrE dTation comparabledto that of digitalMOS devices in the Mrad(Si) range of exposure.

EXPE RI MENTALThe metal gate CMOS process utilized to fabricate thehardened devices employed four diffusions. All high-temperature deposition and diffusion steps were per-formed according to standard Harris production speci-fications, and the junction depths, sheet resistivi-ties and process controls were the same as those nor-mally specified for non radiation-hardened parts.

The photoresist processing was standard, with wet etch-ing and plasma photoresist stripping being done on mostlevels. The necessary process controls implemented foroptimum radiation hardness have been discussed previous-ly.1The devices used N-type <100> silicon for the start-ing substrate. The first step in the process is toform the P- well for the body of the N-channel transis-tor. The final surface concentration of this layer iscritical in determining the threshold voltage of theN-channel transistor. This is followed by the N-chan-nel source and drain formation. These diffusions havethe relatively light concentrations necessary toachieve high BVDSS for the N-channel transistor.The next step in the process is the P+ photoresistfollowed by the heavy boron deposition and diffusion.P-channel sources and drains as well as P+ guard ringsare made with this diffusion. The last diffusion pro-cess forms N+ contact regions and N+ guard rings. TheN+ contact diffusion is required because the lightlydoped N-type source and drain surface concentration isnot sufficient to give low resistance contacts withaluminum metallization.

The authors are with Harris SemiconductorMelbourne, Fla.

N CHANNEL P CHANNEL

FIGURE 1CROSS SECTION OF HARDENED MOS DEVICES

The fabrication techniques required for growing theradiation-hardened gate oxide have been investigatedin great detail. Oxides grown at a wide variety oftemperatures in both dry oxygen2 and hydrogen plusoxygen ambients have been studied. In addition, oxideannealing at various temperatures and times has beeninvestigated.3 As a result, what is believed to bethe optimum process has been experimentally found, andit appears that for oxide thicknesses greater than1,000 angstroms, a hydrogen plus oxygen ambient issuperior to dry oxygen.Following the gate oxidation and anneal, contact aper-tures are formed and aluminum is deposited using aflash evaporation technique. After the interconnectphotoresist, the devices are sintered at 5000C in anitrogen ambient. Passivation silox is then depositedand defined to form the final structure.

Cross sections of typical devices are illustrated inFigure 1. The devices themselves were specifically de-signed for hardness and feature gate oxides which ex-tend from the gate region out to heavily-doped guardrings around each device. This prevents source-drainleakage in N channel devices after irradiation due tosurface inversion of the P- well under the radiation-soft field oxide surrounding the source and draindiffusions. Data was taken on devices having drawnchannel lengths of 10, 18 and 20 microns (.4, .7 and.8 mils), and respective channel widths of 51, 89 and203 microns (2.0, 3.5 and 3.0 mils).Each device was characterized initially and again with-in two hours after irradiation. Each unit was irradiat-ed only once. Irradiation was done with a Cobalt 60gamma source at the rate of about 145 rad(Si)/Sec. Durning exposure, the units under test were mounted insockets and could be biased electrically to simulatenominal or worst-case operating conditions for hard-ness considerations. In one experiment, hardness ver-sus gate bias was analyzed for a given process varia-tion. For all other irradiations, the biasing was asfollows: N channel device drains and gates were at +10volts: N channel sources and bodies were at 0 volts.P channel device drains were at -10 volts; P channelsources, bodies and gates were at 0 volts. This bias-ing scheme was used because earlier experiments atHarris with digital, metal-gate CMOS test circuits hadshown it to give uniform, worst-case results. It alsoallowed correlation of the present results to thoseobtained on the digital devices. As will be notedlater, increasing the bias voltages to 20 volts hadlittle effect on the threshold shifts.

0018-9499/78/1200-1465$00.75 (i 1978 IEEE 1465

IVTI1VOLTS N-CHANNEL

0

500 1000 1500

GATE OXIDE THICKNESS - A

FIGURE 2THRESHOLD VOLTAGE VERSUS GATE OXIDE THICKNESS FOR P-WELL

SURFACE CONCENTRATION = 1.0xl017cm-3

35-

30-

IBVDSSIVOLTS

25-

20-

500

P-CHANNEL

N-CHANNEL

I1000

GATE OXIDE THICKNESS--1500

FIGURE 3DRAIN-SOURCE BREAKDOWN VOLTAGE VERSUS GATE OXIDE

THICKNESS FOR P-WELL SURFACE CONCENTRATION=1.OxlOl7Cm-3

VTNVOLTS

0-2X61016 P WFHI SUJRICE CONCFiiTRATION

FIGURE 4N-CHANNEL TRANSISTOR THRESHOLD VOLTAGE VERSUS P-WELLSURFACE CONCENTRATION FOR 103O0 GATE OXIDE THICKNESS

RESULTS AND DISCUSSION

Units representing a variety of gate oxidation and an-nealing processes were irradiated to determine the re-lative efficacy of dry oxygen and pyrogenic ambientsinproducing radiation hard ned devices. For oxide thick-nesses greater than 1000, the pyrogenic ambient provedsuperior to the dry oxygen. Because of this improvedperformance, all of the characterization data presentedbelow is for the optimized pyrogenic gate oxidation pro-cess. All of the oxidations were oerformed,under care-fully controlled conditions of cleanliness and oxida-tion furnace preparation.The preirradiation characteristics of these devices werea strong function of both gate oxide thickness and P-well surface concentration. Figures 2 and 3 respective-ly illustrate the gate oxide thitkness dependence ofthreshold voltage and BVDSS. These parameters wereessentially independent of device geometry. As expected,the threshold voltage monotonically increases in magni-tude with increasing oxide thickness, corresponding to adecrease in gate oxide capacitance. The breakdown vol-tage, however, falls off with decreasing oxide thickness.This phenomenon is caused by the voltage across the gateoxide controlling the electric field in the silicon,and the effect determines the minimum gate oxide thick-ness which is acceptable for use in MOS devices for lin-ear circuit applications.

Figures 4 and 5 illustrate the effects of P- well sur-face concentration on N channel device preirradiationcharacteristics. In Figure 4, the threshold voltage isseen to increase with increasing surface concentration,as is expected from simple theory. Figure 5 illustratesthe drop in BVDSS associated with increasing P- welldoping. This latter effect determines the maximumallowable P- well surface concentration for linear Nchannel MOS devices.

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I

GAMMA FLUENCE (MEGARADS Si)0.5 1.0 1.5

-

tox

940 A

1130 A

1390 a1580

151

10 I I2X1016 1 X 1017 5 X 1017

P-WELL SURFACE CONCENTRATION -car/cc

FIGURE 5N-CHANNEL TRANSISTOR BREAKDOWN VOLTAGE VERSUS P-WELLSURFACE CONCENTRATION FOR 1030 GATE OXIDE THICKNESS

Units were irradiated with doses ranging from 0.1 to1.5 Mrads(Si) and the results are plotted in Figures 6through 8. Figures 6 and 7 illustrate the thresholdvoltage shifts (&VT) induced by radiation as a func-tion of gamma dose for a variety of gate oxide thick-nesses. Consistent with expected results, the minimumoxide thicknesses correspond to minimum threshold vol-tage shifts. Wafer-to-wafer variation in thresholdvoltage shift for wafers with a common gate oxidation-anneal process was nominally on the order of 10% andwas rarely more than 30%. Over the range of radiationdoses investigated, it was noted that there is a mono-tonic decrease in threshold voltages for P channel de-vices with increasing dose, while the threshold voltageshift for N channel devices appeared to saturate atabout the 0.5 Mrad(Si) dose level for all oxide thick-nesses. The thinnest gate oxides produced exceedinglyhard devices, and experiments are presently underwayat Harris to test the feasibility of pyrogenic gate ox-idations for devices and circuits specifically designedfor digital applications. We note in passing thatthreshold voltage shifts measured at one microamp draincurrent (AVT1) are a good approximation to the zero-current threshold voltage shifts (AVTo). The differ-ence between the two ranged from zero to about 100millivolts.IAVTol was typically 50 millivoltsgreater tha4jAVTlI for N channel devices and typically50 millivolts less than LAVT1I for P channel devices.

FIGURE 6N-CHANNEL TRANSISTOR THRESHOLD VOLTAGE SHIFT VERSUS TOTAL

DOSE FOR VARIOUS OXIDE THICKNESSES

GAMMA FLUENCE (MEGARAD - Si)1.0

FIGURE 7P-CHANNEL TRANSISTOR THRESHOLD VOLTAGE SHIFT VERSUST'OTAL

DOSE FOR VARIOUS OXIDE THICKNESSES

1-

I VT IVOLTS

.5 -

Figure 8 shows the zero-current threshold voltage shiftfor a 1.0 Megarad gamma dose as a function of gate oxidethickness. The P channel threshold shifts were moresensitive to gate oxide thickness variation than werethe N channels. Least-squares-fit lines through thedata points indicated that the magnitude of the thresh-old shifts varied as tox2.6 for P channel devices andas tox1.7 for N channel devices. The indication isthat the gate oxidation cycle must be carefully designedand controlled to consistently yield the thinnest accep-table gate oxide if the full potential hardness of lin-ear MOS devices is to be routinely achieved.Data on BVDSS was also taken on test units after expos-ure to radiation. No change of more than 0.5 volts inthis characteristic was noted for any of the processvariations or test device geometries analyzed in thisi rives ti gati on.

.2-

SLOPE= 1.7

SLOPE = 2.6

* N-CHANNEL

X P-CHANNEL

.1 I

500 1000

GATE OXIDE THICKNESS (R)

2000

FIGURE 8LOG-LOG PLOT OF THRESHOLD VOLTAGESHIFT VERSUS GATE OXIDE THICKNESS

1467

30-

25 -

BVDSSVOLTS

20-

07

-0.5 -

A VT(VOLTS)

-1.0 -

-1.5-

I

I

In contrast to the variable gate-oxide-thickness re-sults, radiation hardness was found to be a very weakfunction of P- well surface concentration. The unitsanalyzed in this case were fabricated with the samepyrogenic gate oxidation-anneal process as those forthe variable gate oxide thickness investigation. Thegate oxide thickness was 1030A. The resulting thresh-old voltage shifts after irradiation for the 0.4 mildrawn device varied less than 0.2 voltsover the entirerange of P- well surface concentrations.The magnitude of the shifts were consistent with thedata in Figure 6 and were nearly independent of surfaceconcentration except for very high concentrations athigh radiation doses. Even in this extreme casethere was little degradation in hardness.The effects of different gate biases up to 20 voltsduring irradiation were also investigated. The P chan-nel transistor shows essentially no variation ofthreshold voltage shift as a function of gate bias.The N-channel transistor has a saturating characteris-tic of threshold voltage shift as a function of gatebias. The +10 volt bias used in the results describedabove gives approximately the worst case threshold vol-tage shift.Radiation hardness was found to be independent of de-vice geometry for the three devices used in this in-vestigation. As a result, a circuit designer can havecomplete flexibility in choice of device geometries,at least within the limits of the geometry range analyz-ed here.

CONCLUS IONSThe results of this investigation confirm that a pyro-genic gate oxidation process can yield total dose rad-iation hardened MOS devices with BVDSS characteristicscompatible with the breakdown voltage requirements forlinear integrated circuits. Excellent hardness charac-teristics were obtained by growing the gate oxide in acarefully cleaned furnace in a pyrogenic hydrogen plusoxygen ambient and then annealing the oxide so grown ina nitrogen ambient.The optimuW gate oxide thickness was determined to beabout 1100A. This thickness provided BVDSS values ofover 30 volts while leading to threshold voltageshifts of less than one volt at 1.5 Megarad-Si for bothN channel and P channel devices.

An upper limit of jxjO17cm-3 for the P-well surfaceconcentration for N channel devices must be set forlinear circuit applications because of BVDSS considera-tions. Though proper device design is critical forradiation hardness, there are no serious design re-strictions on the channel widths and effective lengths.Design rules are Leff >0.3 mils for N channel devicesand Leff>0.2 mils for P channel devices.

Harris Semiconductor is presently applying this tech-nology to conventional dielectrically isolated mater-ial to achieve latch-up free circuits. Radiation-har-dened CMOS Analog Switch and Multiplexer circuits fab-ricated by the processes discussed in this paper willbe appropriate for many space and strategic applica-tions.

ACKNOWLEDGMENTSThe authors wish to thank Mr. D. Pierce and Mr. J.Greene for characterizing the test devices and perform-ing the irradiations, Ms. L. Woodall for typing thepaper, and Ms. J. Koster for preparing the manuscript.The use of the Florida Institute of Technology gammasource is also acknowledged.

REFERENCES

1. Sanders, T. J., "CMOS Hardness Assurance ThroughProcess Controls and Optimized Design Procedures",IEEE Trans. Nucl. Sci., NS-24, 2051, (1977).

2. Hughes, H., Baster, R. D., and Phillips, B.,"Dependence of MOS Device Radi ati on-Sensitivityon Oxide Impurities", IEEE Trans. Nucl. Sci.,NS-19, 256 (1972).

3. Derbenwick, G. and Gregory, B., "Process Optimiza-tion of Radiation-Hardened CMOS Integrated Cir-cuits", IEEE Trans. Nucl. Sci., NS-22, 2151 (1975).

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