Code: 9A02601 B.Tech III Year II Semester (R09) Supplementary Examinations December/January 2014/2015 POWER SEMICONDUCTOR DRIVES (Electrical and Electronics Engineering) Time: 3 hours Max Marks: 70 Answer any FIVE questions All questions carry equal marks ***** ***** 1 (a) Draw and explain speed-torque characteristics of semi converter feeding a D.C series motor. (b) Derive the speed, torque equations of a fully controlled converter connected to separately excited D.C motor with continuous current operation with necessary waveforms. 2 Explain the speed-torque characteristics of a separately excited dc motor connected to a three phase semi controlled converter. 3 Explain with neat diagrams the merits and demerits of mechanical braking, dynamic braking and regenerative braking. 4 (a) Explain the operation of two quadrant chopper feeding to a separately excited DC motor and also draw the current and voltage wave forms for continuous current operation. (b) Discuss with the suitable diagrams I quadrant and II quadrant choppers. 5 State and discuss various methods of speed control of induction motors. 6 Explain the working of 3-phase, 3 pulse cyclo-converter fed induction motor with the help of a neat sketch 7 A 3-phase, 400 V, 50 Hz, 4-pole, 1400 rpm, Y-connected wound rotor induction motor has the following parameters referred to the stator: R s = 2 Ω, R 1 r = 3 Ω, X s = X 1 r = 3.5 Ω. The stator to rotor turns ratio is 2. The motor speed is controlled by static Scherbius drive. The inverter is directly connected to the source. Determine: (i) The speed range of the drive when ∞ max = 165°. (ii) The firing angle for 0.4 times the rated motor torque and a speed of 1200 rpm. (iii) Torque for a speed of 1050 rpm and firing angle of 95°. 8 (a) Distinguish between separate control and self control of synchronous motors. (b) Why cyclo-converter fed synchronous motors are preferred for low speed R09 www.jntuking.com www.jntuking.com www.jntuking.com
Transcript
Code: 9A02601
B.Tech III Year II Semester (R09) Supplementary Examinations December/January 2014/2015POWER SEMICONDUCTOR DRIVES (Electrical and Electronics Engineering)
Time: 3 hours Max Marks: 70 Answer any FIVE questions
All questions carry equal marks *****
*****
1 (a) Draw and explain speed-torque characteristics of semi converter feeding a D.C series motor. (b) Derive the speed, torque equations of a fully controlled converter connected to separately excited
D.C motor with continuous current operation with necessary waveforms.
2 Explain the speed-torque characteristics of a separately excited dc motor connected to a three phase semi controlled converter.
3 Explain with neat diagrams the merits and demerits of mechanical braking, dynamic braking and regenerative braking.
4 (a) Explain the operation of two quadrant chopper feeding to a separately excited DC motor and also draw the current and voltage wave forms for continuous current operation.
(b) Discuss with the suitable diagrams I quadrant and II quadrant choppers.
5 State and discuss various methods of speed control of induction motors.
6 Explain the working of 3-phase, 3 pulse cyclo-converter fed induction motor with the help of a neatsketch
7 A 3-phase, 400 V, 50 Hz, 4-pole, 1400 rpm, Y-connected wound rotor induction motor has thefollowing parameters referred to the stator: Rs = 2 Ω, R1
r = 3 Ω, Xs = X1r = 3.5 Ω. The stator to rotor
turns ratio is 2. The motor speed is controlled by static Scherbius drive. The inverter is directlyconnected to the source. Determine: (i) The speed range of the drive when ∞max = 165°.
(ii) The firing angle for 0.4 times the rated motor torque and a speed of 1200 rpm.(iii) Torque for a speed of 1050 rpm and firing angle of 95°.
8 (a) Distinguish between separate control and self control of synchronous motors. (b) Why cyclo-converter fed synchronous motors are preferred for low speed
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Code: 9A02602
B.Tech III Year II Semester (R09) Supplementary Examinations December/January 2014/2015POWER SYSTEM ANALYSIS
(Electrical and Electronics Engineering) Time: 3 hours Max Marks: 70
Answer any FIVE questions All questions carry equal marks
*****
*****
1 For the network shown in figure given below, draw its graph and mark a tree. How many trees will this graph have? Mark the basic cut sets and basic loops and form the bus incidence matrix A, Branch path incidence matrix K and also the basic loop incidence matrix.
2 (a) Explain what do you mean by partial network. (b) Explain why often use bus admittance matrix rather than bus impedance matrix in the load flow studies.
3 (a) Explain Gauss – Seidel method of load flow solution with flow chart. (b) Explain the classification of various buses in load flow analysis and describe the need for reference bus.
4 (a) Differentiate FDLF and NR method of load flow solutions. (b) Explain dc load flow solution of a power system.
5 The four generators are interconnected as shown in figure below. All reactance are referred to their respectiveMVA and all the generators are solidly earthed. Calculate the short circuit MVA if there is a 3Φ short circuit atpoint F.
6 Three resistances of 10, 15 and 20 ohms are connected in star across a three phase supply of 200 V per phase. The supply neutral is earthed while load neutral is isolated. Find the currents in each load branch and voltage of load neutral above earth. Use the method of symmetrical components.
7 Discuss the importance of the power system stability study and also briefly express the methods to improve stability.
8 The transfer reactances between a generator and an infinite bus bar operating at 200k under various conditions on the interconnector are: Prefault 150 Ω per phase During fault 400 Ω per phase Post fault 200 Ω per phase If the fault is cleared when the rotor has advanced 60 degrees electrical from its prefault position, determine the maximum load that could be transferred without loss of stability.
G1: 20MVA, j0.05 pu
G2: 50MVA, j0.05 pu
G4: 50MVA, j0.08 pu
G3: 20MVA, j0.08 pu
F
30 MVAJ0.04 p.u.
40 MVAJ0.05 p.u.
40 MVAJ0.05 p.u.
50 MVAJ0.05 p.u.
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5
4 3
2 1
5 4
3 2 1
6
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Code: 9A02603
B.Tech III Year II Semester (R09) Supplementary Examinations December/January 2014/2015POWER SYSTEM OPERATION & CONTROL
(Electrical and Electronics Engineering)
Time: 3 hours Max Marks: 70 Answer any FIVE questions
All questions carry equal marks *****
*****
1 Explain Input-Output characteristics of a steam generator unit with multivalve effect.
2 A power system operates an economic load dispatch with a system of 60 Rs/MWh. If raising the output of plant-2 by 100 kW (while the other output is kept constant) results in increased power losses of 12 kW for the system, what is the approximate additional cost per hour if the output of this plant is increased by 1 MW?
3 Explain decomposition technique for hydro thermal scheduling.
4 Explain about the mathematical modeling of speed governing system.
5 A 100 MVA, 50 Hz turbo alternator operates at no-load at 3000 rpm. A load of 25 MW is suddenly applied to machine and steam valves to the turbine commence to open after 0.6 sec due to the time lag in the governor operation. Assuming inertia constant H = 4.5 kW-sec/kVA of generator capacity, calculate the frequency to which the generated voltage drops before the steam flow commences to increase to meet the new load.
6 Explain how a proportional controller gives the coarse control of frequency.
7 (a) Compare the synchronous condensers with mechanically switched capacitors and inductors. (b) Distinguish between source and load compensations
8 Explain the operation of Deregulated power system with a neat sketch
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Code: 9A04602
B.Tech III Year II Semester (R09) Supplementary Examinations December/January 2014/2015MICROPROCESSORS & MICROCONTROLLERS
(Common to EEE, ECE, CSE, EIE and E.Con.E)
Time: 3 hours Max Marks: 70 Answer any FIVE questions
All questions carry equal marks *****
*****
1 (a) Explain memory addressing modes of 8086. Give an example for each addressing mode.(b) What is the purpose of Trap flag? Discuss how debugging feature is provided with the help
of Trap flag in 8086.
2 Write an ALP in 8086 to find the largest and smallest of a set of 8-bit numbers.
3 (a) Explain need and importance of DMA.(b) Discuss about static RAM and EPROM with reference to 8086.
4 (a) What are the different modes of 8255?(b) Explain the 8255 interfacing to 8086 in mode 0.
5 (a) Explain about USB with necessary example and analysis.(b) Give the voltage levels of RS232. Give two features of RS232.
6 With a neat diagram explain the working principle of 8253.
7 (a) Write a program to load accumulator, DPH and DPL using 8051.(b) What is subroutine or procedure?
8 (a) Explain the addressing modes of MCS-96.(b) Clearly explain the Instruction set of MCS-96.
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Code: 9A10504
B.Tech III Year II Semester (R09) Supplementary Examinations December/January 2014/2015LINEAR & DIGITAL IC APPLICATIONS
(Common to EEE & MCT)
Time: 3 hours Max. Marks: 70 Answer any FIVE questions
All questions carry equal marks
***** 1 (a) Derive the expression for voltage gain, input resistance and output resistance of dual input
balanced output differential amplifier. (b) Classify integrated circuits based on their packages and temperature ranges.(c) Elaborate the concept of virtual ground in op-amp.
2 (a) Draw the circuit diagram of astable multivibrator using an op-amp and explain its operation.Mention any two applications.
(b) Discuss about log amplifier and mention its applications.
3 (a) Draw the functional schematic of 555 timers and describe in detail how this IC can be usedto realize a monostable multivibrator.
(b) Describe how a PPL IC can be used for implementing amplitude and frequencydemodulations.
4 (a) Draw the circuit for CMOS OR-AND-Invert (OAI) logic gate and explain its functioningclearly with the help of functional table.
(b) Draw the resistive model of a CMOS inverter and explain its behavior for LOW and HIGHoutputs.
5 (a) Explain sinking current and source current of TTL output. Which of the above parameterdecide the fan-out and how?
(b) What are the precautions to be taken while handling CMOS logic gates?
6 (a) What is the importance of time dimension in VHDL and explain its function?(b) Write a VHDL program in behavioral style to generate a clock with off time and on time
equal to 10ns.
7 (a) Design 1:8 demultiplexer using two 1:4 demultiplexer.(b) Explain the top-level design of ALU using VHDL with its function table.
8 (a) Differentiate between a latch and flip-flop.(b) Design a 3-bit binary synchronous counter.(c) With the help of the master-slave type S-R flip-flop explain how edge triggered operation
becomes possible.
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Code: 9AHS701
B.Tech III Year II Semester (R09) Supplementary Examinations December/January 2014/2015MANAGEMENT SCIENCE (Common to EEE and ECC)
Time: 3 hours Max Marks: 70 Answer any FIVE questions
All questions carry equal marks *****
*****
1 Compare and contrast the Fayol’s principals of management and Taylor’s scientific management theory.
2 What is organization? Explain the significance of organization chart for a unit.
3 Define control chart. What is the importance of control charts in controlling the quality of a product?
4 (a) Describe the various stages of product life cycle.(b) Explain how strategies keep changing in time with changes in the stages of product life cycle.
5 What are the two basic methods of payment of wages? Explain the merits and demerits of thetwo methods.
6 Prepare the network and determine the earliest time, latest time and slack for activity. Alsoidentify the critical path.
7 (a) Define Mission. Explain the components of mission statement. (b) What do you understand by strategic business unit? Discuss its role and relevance in corporate
planning.
8 (a) Define business process re-engineering. Explain the advantages of re-engineering. (b) What are the characteristics of BPR?
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