Recent progress and current issues in Sic semiconductor devices for power applications

C.M.Johnson, N.G.Wright, M.J.Uren, K.I?Hilton, M.Rahimo, D.A.Hinchley,A.P.Knights, D.J.Morrison, A.B.Horsfall, S.Ortolland and A.G.O'Neill

Abstract: A review of current issues in Sic device processing technology is followed by a critical assessment of the current state-of-the-art and future potential for Sic powcr devices. Material quality, ion implantation, the SiC-Si02 interface and the thermal stability of contacting systems are all identified as requiring further work before the full range of devices and applications can be addressed. The evaluation of current device technology reveals that SIC Schottky and PIN diodes are already capable of increased power densities and substantially improved dynamic performance compared to their Si counterparts. Although direct replacement of Si devices is not yet economically viable, improvements in system performance and reductions in total system cost may be realised in the short term. Widespread use will, however, require continued improvements in wafer quality while costs must fall by a factor of ten. Finally, the development of new and improved packaging techniques, capable of handling increased die temperature and high thermal cycling stresses, will be needed to fully exploit the potential of SIC.

1 Introduction

The continuing drive for improved performance, better control and reduced costs in electronic systems has stimu- lated many remarkable advances in semiconductor technol- ogy in recent years. Submicron Si technology has provided the capability to integrate many millions of transistors on a single die while advances in power semiconductor technol- ogy have yielded wafer-scale gate tum-off (GTO) thyristors capable of controlling many megawatts of power.

In spite of these advances, the workhorse semiconductor technology, Si, is generally limited to operation at junction temperatures below 200°C and to deviccs with voltage blocking capabilities of less than a few kilovolts by virtue of its intrinsic physical properties. This imposes restrictions in key application areas. For example, in-engine sensors and controls for the automotive and aerospace sectors would benefit from a 250°C ambient technology while power transmission controls would benefit from higher (> 10kV) blocking vohge switches. In addition, many power elec- tronic systems would derive benefit from reduced cooling requircmcnts as a consequence of being able to operate at higher junction tcmperatures.

0 EE, 2001 IEE Proceedingy online no. 200101 Mi DOL 10.1049/ipCds:20010166 P a p fmt reccived 2nd December 1999 and in final r e v i d fonn loth N o v a - ber 2000 C.M. Johnson, N.G. Wright, D.J. Momson, A.B. Horsfall, S. Ortolland and A.G. ONeU are with the Depattsnent of Electrical and Electronic E n ~ ~ n g , Univemity of Newade, Newcastle upon Tyne, NE1 7RU, UK M.J. Uren and K.P. Hilton are with the Defence Research and Evaluation Agency, Malvm, Worcestershire, WR14 3PS, UK M. Ral~imo and D.A. Hinchley arc with &melab, Coventry Road, Lutter- worth, Leicestershire, LE17 4JB, UK A.P. Knights is with the School of Electronic Engineering, Information Tech- nology and Mathematics, University of Surrey, Guilaord, Surrey GU2 5XH, UK

Wide band-gap semiconductors, such as Sic, GaN and diamond, offer the potential to overcome both the temper- ature and voltage blocking limitations of Si. In essence, the high voltage capability derives from the fact that the critical electric field of the material increases with band-gap while the high temperature capability derives from a reduction in intrinsic carrier concentration with increasing band-gap. The idealised, theoretical performance advantages of wide band-gap semiconductors have been known for some time (see for example [l]) but only recently has it been possible to realise some of these advantages in fabricated devices. This paper presents an overview of the most recent devel- opments in Sic semiconductor devices for power applica- tions and highlights some of the key issues that must be addressed before large-volume commercialisation becomes viable.

1. I Material availability and quality Sic has a large number of different crystallographic forms or polytypes. Of these, 6H-Sic has the most developed growth technology on account of its relatively large volume usage as a substrate for GaN blue LEDs. The preferred material for many power electronic applications is, however, 4H-SiC, which exhibits an on-axis mobility nearly ten times that of 6H-Sic. At present commercial 4H-Sic wafers are available in sizes up to 50" diameter while 6H-Sic wafers are available in sizes up to 75" diameter with 100" at the research stage. Substrates are available in both low resistivity (n- and p-type) and semi-insulating forms [2], although the moderate to high resistivity substrates desirable for high voltage devices are not availa- ble. Devices are, therefore, fabricated on homoepitaxial layers, which are routinely grown to thicknesses of over l 0 O p with doping densities as low as 1014m-3 using hot wall chemical vapour deposition (CVD) [3 ] . High-level carrier lifetimes for this material are typically of the order of several hundred nanoseconds [4] making it suitable for the fabrication of devices with voltage blocking capabilities approaching 10 kV.

101 TEE Pmc.-Circzrils Devices S ~ S I . , Vol 148. No. 2. April 2001

Historically, thc major difficulty with Sic has been the presence of micropipes in the substrates and epilayers. As a singlc micropipe through a junction will destroy its voltage blocking capability, the availability of zero micropipe mate- rial is essential if large area devices are to be realised with acceptable yield. The presence of micropipes has thus been a key obstacle to commercialisation. Howcver, with mate- rial reported with micropipe densities as low as O . l / c ” at the research level (reduced from over 1 000/cm2 in just a few years) [2], indications are that SIC is now adequate lo fabri- cate devices several millimetres square with reasonable yield [ S , 61. Emphasis on defects is now switching from micropi- pes to closed-corc screw dislocations as there is a positive correlation between dislocation density and reduced break- down voltages [7, 81. Indications are that a dislocation density of less than IO’cm” is desirable for fabrication of power devices [8] (current values arc typically around 104cm-*). A further dificulty concems the uniformity of epilayer doping and thickness across the wafer (typical results showing 4‘yo std. dev. on thickness and 8% std. dev. on doping) and the uniformity of doping betwecn runs (typically 40%) [2].

2 SIC processing technology

Sic has a relatively mature processing technology. All the basic process steps, such as doping (by implantation and during epitaxy), etching (plasma techniques), oxide growth, Schottky and ohmic contacts have been successfully dem- onstrated [9]. There are, however, several key processing issues which currently limit the performance of fabricated devices and are worthy of further mention.

2. I Ion implantation Ion implantation is employed widely for local p-type and n- typc doping of Sic. Thc most frequently used implantcd ions are aluminium (AI) and boron (B) for p-type, nitrogen (N) and phosphorus (P) for n-type. Key issues in Sic implantation technology include the reduction of lattice damage occurring during implantation, successful electrical activation of the dopants and prescrvation of good surface morphology. Performing the implantation at elevated tem- perature is a common way to reduce the lattice damage and reduce the requirements for subsequent annealing [ 101. Typical implantation temperatures are: 400°C for Al [ 111, 500°C for N [12], 800°C for P [13]. These temperatures are saiciently high to obtain good electrical conductivity after annealing but not so high as to cause surface dissociation andior large vacancy clusters [14].

The annealing conditions must be precisely determined, both for reordering the crystal and diffusing the dopants into substitutional sites. In addition, evaporation of both silicon and dopants must be avoided if the surfacc stoichi- ometry is to be preserved. This is particularly important in cases where the surface layer forms an active part of the device, for example in MOSFET and MESFET channel regions. Two main approaches to preserving the surface exist: (i) matcrial encapsulation with AlN, graphite [15]; (ii) increased Si partial pressure in the furnacc rcactor, eithcr with silane gas [16] or with Sic-coated pieces [17]. Several authors have given results for optimum electrical activation [18-20]. In all cases, it appears that good electrical activa- tion is only possible if the annealing temperature exceeds 1550°C.

2.2 Oxides on Sic One of the principle benefits of silicon carbide i s that it oxidises to form a stable surface layer of silicon dioxide,

IO?

releasing carbon dioxide in the process. However, the dctailed properties of that oxide and in particular the inter- face between the Sic and the SiOz are significantly different from Si [21]. Fig. 1 shows the band offsets between Si02 and SIC and shows that there is a nearly symmetric barrier for electrons and holes. This means that leakage currents are low even at elevated temperature [23, 241.

9.OeV SiOp

I 2.95

I T

2.85 GH-SIC

t 3.2

1

I 3.1 5 eV

1 2.70 Si

T 4.75

1 Fig. 1 Agamul et nl $1) Thc high dcndty of inlcrface statcs just below the 4H Sic conduction band edge is shown.

Enq hcuul &ets uf SI, 6H unid 4H SIC with respect tu SO, (nftr

The oxidation rate is crystal orientation dependent and is far slower on the Si face than the C face, with, in general, much better properties found for the oxide on the Si face. Oxidation tempcratures are normally around 1100°C and, unlike Si, a post oxidation anneal in a hydrogen ambient is usually reported to havc little effect at reducing interface state density [24]. Interface state density on p-type material can be rcduced to levels bclow 1011cm-2eV-* in the lower half of the gap by the usc of a re-oxidation anneal below I000”C in a wet ambient [25]. However, this treatment does not seem to improve the density of states in the upper half of the gap [26]. Interface state densities on the 4H polytype rise very rapidly towards the conduction band edge, typi- cally exceeding IO”cm-*eV-’, whereas on 6H the density is an order of magnitude lower. This has been ascribed to a carbon related acceptor which is located just below the con- duction band edge for 4H but within the band for 6H (see Fig. 1) [27]. These defects have not been successfully removed by any standard surface treatment or post oxida- tion anneal.

The best N channel inversion mode MOSFETs fabri- cated on 6H show electron mobilities of -100cm2Ns with a negative temperature coefficient, whereas 4H shows

s of at best 25 and usually much lower and with an activated mobility [28, 291. The fluctuations in potential resulting from the charge in the interface states near the conduction band edge appear to be responsible for this very disappointing mobility particularly for 4H (301. As a result, most recent work on power devices has employed the 6H polytype.

The breakdown and reliability properties of SiO, are crucial for all MOS devices, but unfortunately the situation is not as favourable as it is for Si. The dielectric constant of

IEE P~oc.-Circrrits Devices S,yst., I‘d. l4K. No. 2, April 20111

SiOz is -3.9 whereas it is -10 for Sic, so any normal surface field will be -2.5 times higher in the oxide than the Sic. Hence, to gain the full benefit of the -2.5MVicm breakdown field of Sic, the oxide must withstand 6.25 MVI cm, which is highcr than is reliably usable, even on silicon. High field stressing of oxides has shown that oxides grown in a wet ambient break down at lower fields than dry grown oxides [3 11, and that extrapolated time-dependent- dielectric-breakdown lifetimes of 10 years can only be obtained on n-type at fields less than SMVicm at room temperature. Studies have shown that the lifetime for oxides drops rapidly at elevated temperatures [32], with a vulnerability to negative bias-stress instability [33]. Electron injection into the oxide is more efficient than for Si due to the lower barrier and the induced defects are more stable [24]. In addition, the barrier for injection of holes is much lower than in Si, which is unfortunate since holes are particularly damaging to oxides [34].

2.3 Contacts Ohmic contacts to both n and p-type material have been demonstrated in 4H Sic with specific contact resistivities of the order of 10-5Rcm2 [35, 361. To achieve this, it has proved necessary lo use rapid thennal annealing (RTA) of the wafer at temperatures as high as 1400°C. The majority of contacts are based around Ni and AI (for 11- and p-type, respectively) although these are generally not stable at temperatures above 400°C. To take advantage of the full potential for high temperaturc operation of 4H Sic devices, contacts that are thermally stable to 600°C over long peri- ods are required. Recent work based on AL'NilWIAu contact structures on p-type 4H Sic have shown longevity of over lOOh at 600°C with a contact resistance of 10-3Clcm2 [37J Other work has shown similar results using a variety of materials including TaC [38] and AlSi [39] alloys.

Several groups have reported excellent quality room teni- perature Schottky diodes, with the barrier height dependent on the metal chosen. This demonstrates that the Fermi level is not pinnal at the surface of the 4H Sic. Values of qB vary from 1.lOeV (Ti) to 1.73eV (Au), which are mark- cdly larger than those observed on Si or GaAs. This increase in qB makes Sic an ideal material for high-voltage, high-temperature, low-leakage current Schottky diodes. Surface preparation, prior to deposition of the Schottky contact, has been shown to bc a key factor in achieving good performance with sacrificial thermal oxidation being the optimum technique [40].

2.4 Edge termination and passivation Many of the techniques applied to Si deviecs are also appli- cable to Sic. For example, field plates [41, 421, guard rings and junction termination extensions [43, 441 have all been used to good effect. Another simple technique involves the implantation of a high dose of inert ions (either Ar [45] or B [46]). In this case the damage caused by the implant causes a high resistivity region to be formed close to the surface which acts in a manner similar to semi-insulating polycrystalline silicon (SIPOS). The reverse leakage performance of Ar and B implanted edge terminations may be improved by low temperature (600°C) annealing [47]. Passivation of the Sic surface is not trivial and has yet to be fully understood. The effects of inadequate passivation have been observed in microwave MESFETs, where this leads to degradation of gain under CW operation [48]. Power switching devices, on the other hand, appear to perform well with conventional Si passivation treatments such as polyimide.

IEE Proc.-Circuirs Dcvims SjJ.st.. Vd. 14K. No. 2, April 2001

3 State-of-the-art in Sic devices

The theoretical benefits of SIC semiconductor technology, including predicted device operating temperatures of over 800°C and voltagc ratings up to 25kV , havc been known for some timc (sec for example [l]). Practical realisation has been some time coming but continuing research now appears to be bearing fruit (Table 1).

Table 1: Headline performance figures for fabricated SIC power devices

Device

Diode

MOSFET

MESFET

SIT

JFET

IGBT

BJT

Thyristor

Performance highlights

600V, 60A MPS 16"' die area

6.2kV PIN

3.85kV Schottky

2.5kV, 40A PIN, 20-40mmz die area

2.6kV lateral DIMOS

1.8kV, 0.4A vertical TIMOS, 1 mm2 die area

439V, 1A ACCUFET, 2.2"' die area

MESFET with fm,,50GHz 80W CW at 3.1 GHz , single die

400W pulsed power at 1.3GHz, multi-die

1.8kV, 1.5A vertical device, 2.3"' die area

400V, 1A p-channel device, 2"' die area

1.8kVI 2.5A npvn device, 1.4mm' die area

700V GTO with 800A/cm2 performance

2.6kVI 12A GTO, 3.1 mm2 die area

1.4kV UMOS

Reference

[51

1491

1501

1511

[521

1531

1541

1551

156.571

[58,591

1671

1601

1611

1621

1631

1641

3. I RF power devices Sic microwave power devices have already achieved con- siderable maturity with performance which considerably exceeds that available from other semiconductors. There are two basic device variants which have been successfully fabricated: the M ESFET and the static induction transistor (SIT) [65, 661. Both are basically Schottky gate controlled majority carrier devices with the MESFET having a surface channel for higher frequency use and the SIT a vertically oriented channel Tor larger voltage handling.

Northrop-Grumman has largely focused on the SIT and has achieved the highest RF powers to-date. This has included a module which generating 400W pulsed a1 I.3GHz (16 devices of ~ 5 m m source width) and a module which produced 78W at 2.9GHz or 47W at 4GHz (4 devices of 12.9" width). 1 kW and 2.5kW high definition television transmitter modules have been made for 850MHz operation. This technology has outstanding power and voltage handling, but due to the higher parasitic elements associated with the use of a conducting substrate is limited to use below about SGHz [67].

On the other hand, the MESFET has higher frequency and power density capability (up to 5OGHz jko-y [S6, 571 and 4.6Wimm of gate width [58, 59]), however, most effort has focused on power operation up to 4GHz . Fig. 2 shows a close-up of a power MESFET fabricated by DERA at Malvern, UK, which is typical of the technology employed. Multiple gate fingers are used to reduce gate resistance, with a thick gold-plated airbridge used to pro- vide a low inductance interconnection between the source fingers. This technology has achieved 16.9W at 4GHz with 40'% PAE from a 1.55 x 0.65" chip with three paralleled devices of total 7.5mm gate width [68]. The highest pub- lished power to-date has been achieved by Cree Research

103

who obtained 8OW CW at 3.1GHz with 38% PAE from a 0 . 7 ~ long, 48" wide device operating at 58V vT was 9GHz and ji,,, 20GHz ) [58, 591. Some reports have indi- cated that trapping can influence the power peformance [48,69,70], but the recent announcement by Cree that they are making a MESFET avaihbble commercially indicates that the problems can be solved. The device will deliver 1OW over 400MHz-2.5GHz and is designed for use at the mobile base-station power rail voltage of 48V [71].

Fig. 2 Put f mu,lfkger power MESFET slzoiving fow 0 . 7 p long gate ,fingers with xol airhr ge uzterconrzecting the source fuzgers

3.2 Power switching devices In the power switching device sector, demonstration of a full range of power device types has been possible. However, progress towards devices with realistic current handling capabilities and high breakdown voltages has been hampered by poor material quality. This situation is now beginning to alter with several research teams report- ing good performance from relatively large area devices [5,511.

3.3 Sic power Schottky diodes Fast recovery diodes play an important role in most power electronic circuits as freewheeling and/or snubber compo- nents. Since the introduction of the insulated gate bipolar transistor (IGBT), diodes in many circuits have been subjected to even higher voltage and current levels, and have been required to switch at much higher frequencies (>lOkHz). It is now widely recognised that silicon fast recovery diodes have reached their limit and that they are now the limiting factor in IGBT circuits from 600V to 2.5kV and above.

Both Si and GaAs power Schottky diodes are widely used in low voltage (< 300V) applications on account of their low switching losses and positive temperature coeffi- cient, which makes them suitable for parallel operation. At higher voltages, Si and GaAs Schottky diodes exhibit high on-state losses thus offsetting their advantage when com- pared to silicon PIN diodes. Sic Schottky diodes, on the other hand, can be based on much thinner, more heavily doped material (on account of the higher breakdown field) and thus exhibit relatively low on-resistance. For example, an ideal SiC Schottky diode formed on a 10 p, epilayer doped 5 x 10'5cm-3 might attain a breakdown voltage approaching 18OOV or roughly I O times higher than that possible in Si whilst achieving a specific on resistance of 2ms2cm2. Table 2 presents a comparison of static and dynamic characteristics for a state-of-the-art 1.6kV silicon PIN diode and the expected performance of an equivalent Sic Schottky diode. Key advantages include ease of paral- leling, low switching loss and tolerance of high dildt. The only significant disadvantages are a lunited surge current capability and increased reverse leakage currents at elevated temperatures (although this should improve with material quality).

Many groups worldwide have been quick to recognise the potential of SIC Schottky diodes and, with recent improvements in material quality. some impressive practi- cal demonstrations have resulted [5, 501. Total yields of over 50% have been obtained for 1.5mm2 diodes and detailed studies of performance and reliability have revealed no significant problems [6]. Figs. 3 and 4 show, respectively, the static and dynamic characteristics of a 1200V, 8A Sic Schottky diode fabricated at the University of Newcastle [72]. Of particular note is the low level of

Table 2: Performance comparison for 16OOV Si PIN diode and SIC Schottky diode

Static characteristics

On-state voltage @ 25°C

Temperature coefficient always +ve -ve or +ve

Leakage current @ 125°C Max. junction temperature 350°C 150°C

Voltage rating suitable for 300-16OOV only suitable for 16OOV

Dynamic characteristics 1.6kV Sic Schottky Diode 1.6kV silicon PIN diode

Reverse recovery losses small capacitive effect high

IGBT turn-on switching losses low high

Electromagnetic interference EM1 low high @ high diidt

Stray inductance dependence low high

Forward current dependence low high

Temperature dependence none high

Dynamic avalanching none yes @ high di/dt(limiting)

Snappy recovery none yes @ high di/dt (limiting)

Surge current capability moderate excel lent

1.6 kV Sic Schottky diode

Ni: 1.5V @ 250A/cm2 Ti: 1.OV @ 250A/cm2

5.0mA/cm2 @ 10OOV/125"C

1.6kV silicon PIN diode

2.0V @ 100A/cmZ

0.5mA/cm2 @ 1000 Vi125"C

104 IEE Proc.-Ciwuirs Devicrs Sjst., Vol. 148. No. 2, April 2001

reverse recovery current, which is independent of tempera- ture and results in significantly reduced device switching losses. Current work is focused on packaging (see for example Fig. S), characterisation and reliability testing of similar diode dies. Devices such as this offer the opportu-

I O 1 U / q a /

-1600 -1200 -800 -400

I) 0.5 1.0 1.5 2.0 2.5 3.0 - -50 voltage, V

4 -100 4

-200 0

-250 I j -300 Fig. 3 ured ut 300Kj

Static I-V chwteristirsfbr a 1200 V XA Sic Schottlg~ di& (nzeas-

-15 1 -20 I I I I I I

0 50 100 150 200 250

time. ns

0 Sic diode at ]unction timpcralures of 25°C and 125°C (curvcs overlay one mothcr) 0 Si diode at junction temperaturc of 25°C A Si diode at junction temperature of 125°C

Fig.5, 5m x 5mm Sic Schottky diocle die m t e d on a molybdfmolz spare " i e U siarzdavd TO-3 packuge

TEE Pmc.-Ci,crrils Device, Sy'sr., Vol. 148, h'o. 2, April 20Vl

nity to free system designers from the current limitations of Si PIN diodes and are expected to form one of the first commercial applications of Sic in the power electronics sector.

3.4 Sic power MOSFET technology Of the major classes of power semiconductor, the MOSFET probably has the greatest strategic importance in s i c power electronics, largely because it offers a practical solution for majority carrier operation at voltage ratings approaching SkV. Although many devices have been demonstratcd on 4H-Sic (see for example[S2, S3]), the measured on-state performance has been rather disappoint- ing, largely because of the relatively poor effective channel mobility. Recently, however, devices fabricated on the 6H polytype have yielded some particularly impressive results with performance figures which outstrip those possible in Si by an order of mdgnitude[%].

A further complicating factor is that the field in the SiC must be limited to around lMV/cm to avoid excessive electric fields in the oxide. This necessitates suboptimal choices of epilayer doping and thickness. Buried channel or depletion mode devices such as the ACCUFET [5S, 731 are attractive because they move the high field away from the SiC/SiOz interface resulting in reduced surfacc field and an improved lifetime. 6H appears to be the material of choice for MOSFETs fabricated on the Si face, but recent results for transistors fabricated on the (1 120) surface have shown encouragingly higher mobility for both 4H and 6H [74].

3.5 Power JFET and static induction transistor Like the MOSFET, thc vcrtical JFET and static induction transistor (SIT) are majority carrier devices and have the potential to yield fast switching, high voltage devices with a low on-resistance. JFETs and STTs do not, however, exhibit the low channel mobility of the MOSFET and they are thus promising devices for applications in which the normally on characteristic is not a severe disadvantage, for cxample in a cascode connection with a normally off device such as a Si MOSFET [60]. Indeed, the vertical JFET described in [60] currently represents the best performance achieved to date in a Sic majority carrier active switch, dis- playing an Ron of just 24.5mQcm2 for an 1800V device. JFETs have also been shown to be suitable for operation at high juiiclion temperatures [7S].

3.6 Power bipolar devices Sic offers the potential to fabricate double injected devices, such as the PIN diode or thyristor, with blocking voltages exceeding 2SkV . To attain such high voltages requires thick, lightly doped voltage blocking regions with long carrier lifetimes. For example a 2SkV Sic punch-through diode would require around 2 0 0 p of material doped 5 x 1013cm or less with a high-level lifetime of around 20p. It is worth noting that an equivalent Si device would require a 2mm voltage blocking layer doped 1012 cm-3 or less with a lifetime of at least 400p! At present, Sic growth technol- ogy does not yield lightly doped substrates and epitaxial layers are limited in thickness to less than l o o p with measured high-level lifetimes at best around S00ns [24]. This places an upper limit of around l0kV on the voltage blocking capability of any practical device.

Further limitations arise from the built in junction volt- age drop, which is an unavoidable feature of any bipolar device and is around 2.0' for Sic compared to around 0.7V in Si. As a consequence, the on-state voltage of any Sic bipolar device is likely to be higher than its Si equiva- lent, even at the 5kV level. The principal electrical advan-

105

rages of Sic bipolar devices at voltage blocking levels below current Si limits will thus be confined to switching speed improvements resulting from the thinner voltage blocking layer and reduced active device area. In addition, MOS gated structures such as thc IGBT will only be effec- tive if the epilayer resistance dominates the on-resistance of the equivalent MOSFET structure. With current Sic MOS technology, a 4H-Sic IGBT would only be effective at voltage blocking levels exceeding 4kV (in Si, IGBTs become effective at around 300v). Finally, the presence of deep levels, associated with common p-type dopants such as AI and B, gives cause for concem about the integrity of voltage blocking structures under dynamic conditions. This places an upper limit on the reverse dddt that can be applied without generating a dynamic punch-through con- dition [76].

In spite of these drawbacks, some impressive results have been reported for more conventional forms of bipolar power semiconductor. PIN diodes have been demonstrated with blocking voltages exceeding 6kV [49] and with die areas up to 40mm2 and current ratings of up to 40A for inclusion in 2.5kV power modules alongside Si IGBTs [51]. Recently some very promising results have been reported for power bipolar junction transistors (BJTs) [62]. These devices exhibit a relatively high current gain (-20), and an effective on-resistance of just 1 0.8niQcm2 (the lowest of any Sic power switch reported thus far) with a positive temper- ature coefficient. Note that the BJT structure does not suf- fer from the high forward voltage drop of other bipolar devices. Both conventional and GTO thyristors have been demonstrated at voltage levels between 400V and 2.6kV [63, 641 and recently a p-channel IGBT has been fabricated [hl]. Note that an n-type substrate is preferred to thc more typical p-type substrate found in Si devices on account of the relatively high resistivity of p-type Sic substrates (typi- cally 2.5D.m for p-type compared to 0.015Qcm for n- type).

3.7 Comparison with Si power switching devices A key parameter used to evaluate a particular power switching device or technology, is the power switching or VA density. This is calculated by taking the product of maximum on-state current (at some specified case tempera- ture) and rated off-state voltage and dividing this by the die area. It, therefore, represents the efficiency with which the semiconductor die area is utilised in a particular switching function. Fig. 6 presents data, based on published figures, for a range of Sic devices. As might be expected, the MOSFET-based devices show the lowest switch VA densi- ties, at around 10&300W/mm2, while high voltage power bipolar devices show most efficient use of die area display- ing switch VA densities as high as 11,000W/mm2. These figures may be compared with values for existing commer- dal Si power MOSFETs (around 150W/mmz), IGBTs (between 700 and 1400W/mm2 at 1200v). It is clear that existing Sic devices, with the exception of MOS devices, already offer significantly higher power densities than current Si devices. In addition SiC devices benefit from the improved dynamic performance available from majority carrier technology at high voltage. For example, several groups have employed Sic Schottky diodes in conjunction with Si IGBTs and have shown combined IGBT-diode turn-on losses reduce to around one-quarter of those obtained with a Si PIN diode [5, 771. Even where a minor- ity carrier Sic device i s used, the thinner voltage blocking region and accompanying lower lifetimes mean greatly

1 Oh

reduced levels of stored charge. ABB have reported switch- ing losses for their 2.5kV , 150A Sic PIN diode/Si IGBT modules of just 3.8% of those obtained with a Si PIN diode

I Sic bipolar-

t 2 103 104

reverse voltage, V

Fig.6 sipwe rmn obtiuhcd from published re,suN.~ Solid lines show theoretical limits (see terti

Vulues of device switch VA (reverse volts xfor~vmi current) per

0 Infineon (6H. vertical, 300K [54] + Cree (6H p-channel IGBT) [61] 1 Infineon (JFET 12MJV) [GO] A Daimler Chiysler (Ihmiii- MPS) [SI A Liiikoping (Schottky) [SO] 0 Cree (4H G ' p [64] 0 AI1B (20mni pin diode) [51] + commercial Si MOSFETs X commercial Si IGBTs Shaded symbols: 0 Cree (4H, ACCU DMOS) [55] 0 Crcc (BJT) [62] A NewGutle (6mm' Schottky) 0 Cree (pin diode) [4]

Any comparison of Sic power device technology with currcnt Si technology should take account of the future potential of the material tcchnologics as well as the current stale-of-the-art. The curves superimposed on Fig. 6 show idealised switch VA ratings based on the ultimate power dissipation limits of the packaged die. For Si devices a maximum packagc dissipation of 500 W/cm2 and a junction tcmpcrature of 125°C have been assumed while figures of 1500Wicm' and 325°C have been taken for Sic. This reflects a typical 'best practice' single-side cooled packaging technology with a specific thermal resistance of 0.2CW-'cm2. For the bipolar devices a range of values is shown, reflecting the feasible range of carrier lifetimes. It is of interest to note the cross-over points for the unipolar and bipolar curves: for Si this is 15&300V (a figure which agrees well with typical practice) while for Sic the value is in the range 150G2500V. For both Si and Sic devices, power dissipation and hence switch VA density is limited by the packaging technology rather than the semiconductor die. In fact, the estimated temperature drop across the dies, based on a 3 0 0 ~ thick wafer at the stated junction temperatures, is relatively small at around 25K for Si and 60K for Sic. A further complicating factor in the case of SiC devices is the need to operate the die at high junction temperature (> 250°C) to obtain high power densities. Such temperatures are outside the range of many conventional packaging techniques and the thermal cycling strcsscs produced would exceed those found in all Si applications. Improvements to current power device packaging solutions must therefore be found beforc Sic devices can approach anything like their full potential.

IEK Proc.-Cirruils Ilrvicc.~ Sv.r t . , Vol. 148, No. 2, April 2001

4 Commercialisation

Although it is clear that a substantial market exists for Sic, the rate of commercialisation will bc limited by the materi- als technology and, more importantly, cost. At present, the cost of Sic substrates exceeds those of Si by a factor of nearly 100. Although less Sic is needed to perform an equivalent function (current densities may be up to I O times higher than in Si), this is not sufficient to offset the addi- tional wafer costs. In addition, the processing costs for Sic are still relatively high, while those for Si are Calling as the market for power semiconductors continues to expand. The net effect is that something approaching a factor of 10 reduction in both the cost of the starting material and the cost of processing is needed before SiC can compete with Si on equal terms. Whcrc a net system advantage can be dem- onstrated, however (e.g. reduced cooling cost outweighs extra die cost), thc bencfits of Sic may bc realised in thc shorter term. It is, therefore, probable that Sic will find its first power electronic application in medium voltage (400V < V,, < 3kV) SchottkyPIN diodes Tor use in combination with Si IGBTs. For more specialist applications, where Si technology cannot compete directly (e.g. hostile and high temperature environments), the cost limitation is less rele- vant, however, the need to recover the Tu11 costs on a rela- tively small initial market may stifle development.

5 Concluding remarks

SIC, with its potential for operation at higher voltages, temperatures and power densities than Si, is well poised to revolutionise power semiconductor Lechnology. Most of the major classes of power semiconductor have been demon- strated at research level and Sic is already beginning to penetrate thc RF scctor at tlic conmcrcial levcl. Indccd, thc materials technology has now advanced to the point where large volume commercialisation of elementary power device structures, such as Schottky and PIN diodes, is possiblc. although not yet economically viablc. There are, however, key technological issues, including material quality, ion implantation, the Sic-SiO, interface and the thermal stabil- ity of contacts and passivation systems, which must be resolved if the full market potential of Sic is to be realised in active power switches.

6 Acknowledgments

This work was supported in part by the UK Engineering and Physical Sciences Research Council (EPSRC) under the SCEPTRE project (research grant GRiL62320) and in part by Technology Group 7 of the U K MOD Corporate Rescarch Programme.

7 References

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