STMicroelectronics Mentor Graphics

®

Reliability simulation in CMOS 90nm design using Eldo

Chittoor Parthasarathy, Emmanuel Vincent

STMicroelectronics (Crolles)

Philippe Raynaud, Cyril Descleves

Mentor Graphics (Grenoble)

20 Sep 04 2Reliability simulation in CMOS 90 nm design using EldoCrolles®

Introduction

Aggressive device performances are required in modern CMOS

technologies

– SoC, multiple devices � less degrees of freedom

– Overdrive / unscaled Vdd : more performances expected

Reliability margins better quantified, but are narrower than before

Exhaustive OLT (Operational Life Test) of final product is quite

difficult

– Products are convergence driven

� difficult to optimize OLT with respect to planning, execution and costs

� expensive to correct any reliability problems occurring at this level.

Intrinsic reliability : move from management at process level

towards a « process/design » co-management

NBTI is a new limiting failure mode for modern technologies which

requires this co-management intrinsic reliability

20 Sep 04 3Reliability simulation in CMOS 90 nm design using EldoCrolles®

Goal of this presentation

To present an open solution for reliability

assessment developed within a circuit

simulator (Eldo from Mentor Graphics)

– To discuss some of the features that are useful in

translating different issues of device reliability for

the actual circuit operating conditions.

To present its application to NBTI

degradation in 90nm technology

20 Sep 04 4Reliability simulation in CMOS 90 nm design using EldoCrolles®

Reliability simulation

Spurt of DiR (Design in Reliability) tool development during

early 1990’s, in universities (UC,Berkeley[1], UI,Urbana-

Champaign[2], University of Southern California[3], as well as

a few companies (TI[4], Philips[5]) lead to automated tools to

check intrinsic reliability.

– Hot-carrier, gate oxide, electro migration issues

� Targeted at small circuits.

– Activity on further development decreased during the late 90’s

� In part due to perception of effective reliability control at technology

level.

– Usage of these tools typically confined to specific groups

– Detailed analysis of tools can be found for example in [6].

20 Sep 04 5Reliability simulation in CMOS 90 nm design using EldoCrolles®

Reliability simulation

Advanced technologies and newer aging issues (such as

NBTI [7]) have recently renewed interest amongst both

technology and design communities to have a DiR solutions.

Increasingly, there is a push to have reliability analysis

methodology integrated into the design flow.

– Designers increasingly aware and uncomfortable with reducing

reliability margins

� Seek more quantitative and relevant reliability guidelines.

� Tools preferred where available.

20 Sep 04 6Reliability simulation in CMOS 90 nm design using EldoCrolles®

Reliability simulation integration into design methodology

Robustness and integration into SPICE models.

– SPICE is the sole representative of the actual device that a

designer has.

� Many physical effects have begun to be packed within SPICE

definition (Process corners, mismatch, mechanical stress, …)

– The device model parameter definition is quite complex

� Uses subcircuits

� Actual parameters are derived from several interlinked

coefficients

– The coefficients associated to reliability are an additional but

independent part of SPICE model

� Enable simulation with or without reliability

20 Sep 04 7Reliability simulation in CMOS 90 nm design using EldoCrolles®

Eldo

Reliability model (Eldo UDRM)

•Extended model card

•Extra object Library

Reliability Simulation – Flow

Nominal Results

Aged Results

Comparison

Stress analysisAging related

commands

Description of

Transistor Stress

as function of

Activity

Standard BSIM model

Netlist

Simulate Fresh

Model Parameters

(Fresh)

Simulate Aged

Reliability

parameters

Description of BSIM

parameters

evolution as

function of Stress

Updated BSIM3/4

parameters

Stress File

Optional

20 Sep 04 8Reliability simulation in CMOS 90 nm design using EldoCrolles®

Stress assessment – 1/3

Minimal overhead for the designer

– Ease of use: just add the .AGE command

– Minimum CPU time impact using on-the-fly processing

� No need to store large amounts of data

� No separate time required for reliability analysis.

Eldo UDRM (User Defined Reliability Model)

– Flexible modeling: model implemented via an API and

compiled into an Eldo dynamic library

– models can be updated with the latest developments on the

physics/experimental front

� Important, since the physical understanding of the phenomenon

such as NBTI is continuously evolving

� Saturation after long durations of stress

� AC effects

� Spice Degradation components, etc

20 Sep 04 9Reliability simulation in CMOS 90 nm design using EldoCrolles®

Eldo UDRM API - access functions

The API provides read access functions to

– instance parameters (W, L…)

– usual quantities (Vdsat, Vth, Isub…)

– parameters of the stress model (user defined,

unlimited)

– parameters of the “parameter update model” (user

defined, unlimited)

– global variables (simulation time, temperature…)

and read/write access functions to

– model parameters (VTH0, U0…)

20 Sep 04 10Reliability simulation in CMOS 90 nm design using EldoCrolles®

Eldo UDRM API - required functions

User-defined functions required to fully define

an aging mechanism :

– register parameter names and default values for

the stress model

– register parameter names and default values for

the “parameter update model”

– define the equations of the stress model (Eldo

handles the integration automatically)

– define the equations of the “parameter update

model”

20 Sep 04 11Reliability simulation in CMOS 90 nm design using EldoCrolles®

Stress assessment – 2/3

Simulate for a unit cycle

of the given input vector

Take the operating points and

estimate the degradation(Age)

Stress = t * f(operating conditions)

Extrapolate

degradation at the

requested time

Working PrinciplesThe “Stress” is modeled

linearly with respect to “t”

-ease of integration

Degradation(t) = (Stress) n

� During reliability simulation, the device parameter evolutions are

computed according to the operating condition, and the transistor is

simulated with the modified SPICE parameter set to represent

degradation.

where T is the time of the unit simulation,

and Age is the desired time for the reliability simulation

∫•=T

0

f(operating conditions) dtAge

TStress

LINEARIZATION

INTEGRATION

20 Sep 04 12Reliability simulation in CMOS 90 nm design using EldoCrolles®

Stress assessment – 3/3

Limitless number of stress vectors

– Can be used to store additional data during the

stress analysis

�Stress analysis can be made more complete and closer to

the physical reality by storing some important information

during the stress assessment for later sets of simulation runs

� The second set of simulations (performance impact

assessment) are entirely independent from the first simulation,

except for the stress file.

� By storing the conditions of stress, certain decisions can be

made during the second simulation run

e.g., saturation of degradation

20 Sep 04 13Reliability simulation in CMOS 90 nm design using EldoCrolles®

Design in Reliability – Impact Assessment

During the subsequent simulation run(s), the BSIM3 or BSIM4 model parameters specified through the UDRM are updated to reflect the characteristic of the aged device

Flexibility in analysis: the subsequent simulation can be in a different operating mode than the first simulation via the stress file loading– The calculated stress is stored in a simple file and can be used for multiple “aged” simulations

– For designers, it is helpful to assess performances in different modes of the circuit

– For reliability model developer, it helps to verify impact of model parameter update.

Simulation “Mode 1”

Fresh

Stress File

Simulation “Mode 1”

Aged

Simulation “Mode 2”

Aged

Simulation “Mode 3”

Aged

20 Sep 04 14Reliability simulation in CMOS 90 nm design using EldoCrolles®

Negative Bias Temperature Instability

NBTI – is a DC stress

– Without any requirement of mobile carriers

– Proportional to applied Vgs and Temperature

– Causes uniform degradation across the oxide interface

– Causes change mainly in the linear parameters (Vth and mobility

related parameters)

– No geometry dependence

– Phenomenon complicated with evolving findings with respect to

mechanism, behavior and model [8 ],[9 ]

– The details of the simpler version of the NBTI model spelt out here.

nmkTEaVgs tLeeD ⋅⋅⋅⋅=∆ − /γβ

∫−

=T

nmkT

Ea

Vgs dtLeeNStress0

/1)***( γβ

nStressCP )(*1=∆

NBTI Model

Integral form

Spice Parameter update

20 Sep 04 15Reliability simulation in CMOS 90 nm design using EldoCrolles®

NBTI degradation simulation

Vth is used to monitor the degradation

Parameters seen to change (depending on device family)

– Vth, u0, ua, nfactor

– Saturation regime changes as well as length dependence

seen to arise directly from the changes in the above

parameters

Vth evolution with time

1 10 100 1000 10000 100000time(s)

DVth

(a.u

)

Vgs1

Vgs2

Vgs3

I-V linear regime: impact of stress

0 0.2 0.4 0.6 0.8 1 1.2

Vgs(V)

Ids(a

.u)

Fresh Id-Vd

Degraded Id-Vd

20 Sep 04 16Reliability simulation in CMOS 90 nm design using EldoCrolles®

Tpd fresh

Tpd aged

Delta

Threshold

>20 mVDelta: 56ps

Example of simulation results

Buffer - Delay Increase IO Input - Threshold change

20 Sep 04 17Reliability simulation in CMOS 90 nm design using EldoCrolles®

Conclusion

Eldo UDRM – an open model for reliability simulation

– Scope to include effects arising due to specificity of degradation

� Relaxation

� AC effects

� Long term saturation

Implementation for different device families from the

90nm node onwards at ST

– Designers can now quantify the reliability assessment of circuit

blocks.

NBTI model evolving. Interface open to consider the

new effects.

20 Sep 04 18Reliability simulation in CMOS 90 nm design using EldoCrolles®

Bibliography

[1] C.Hu,”IC reliability simulation”, IEEE J.Solid State Circuits, vol.27, March 1992, pp241-246

[2] Y.Leblebici and S.M.Kang, “Simulation of MOS circuit performance degradation with emphasis in VLSI design-for-reliability”, Proc.1989 IEEE ICCAD, October 1989, pp492-495

[3] B.J Sheu et al, ”An integrated circuit simulator – RELY”, IEEE J.Solid-State Circuits, vol 24, April 1989, pp.473-477

[4] S.Aur et al, “HOTRON – A circuit hot electron effect simulator”, Proc. 1987 IEEE ICCAD, November 1987, pp 256-259

[5] MM Lunenborg et al, “PRESS, A Reliability Circuit Simulator with Built-In Hot-Carrier Degradation Model”, Conf Proc ESREF, Bordeaux/Arcachon, France, October 1993, pp157-161

[6] Y.Leblebici and S M Kang, “Hot-carrier reliability of MOS VLSI circuits”, Kluwer Academic Publishers

[7] N.Kimizuka et al, “NBTI Enhancement by Nitrogen Incorporation into Ultrathin Gate Oxide for 0.10-um gate CMOS generation”, Symposium on VLSI Technology Digest, 2000, pp.92-93

[8] V Huard et al, “A thorough investigation of NBTI MOSFET degradation “, Special Issue on NBTI, Microelectronics Reliability, in press

[9] M.Denais et al, “On-the-fly characterization of NBTI in ultra-thin gate-oxide PMOSFETs”, to be presented, IEDM 2004.