RF Amplifier Analysis and Design

Critical Specifications:Input impedance: Zin

Load Impedance: ZL

Frequency of operation (upper and lower 3 dB frequencies)• Maximum “undistorted” Power into ZL

• Voltage Gain , Power Gain• Efficiency (Pout(max)/PDC)

Power Supply Requirements (VDC, IDC)

Remember: Design is the reverse of analysis. If you can’t analyze a thing, you cannot design a thing.

An analysis problem has one correct solution. A design problem can have many solutions.

Transistor Equivalent Circuits

DC ModelFor Bias Analysis/Design

AC ModelFor Amplifier

Analysis/Design(Common Base)

Equivalent AC ModelFor Amplifier

Analysis/Design(Common Emitter)

Device VBE IB , IC , IE re=1/gm

NPN 0.7 v > 0 0.026v/IE

PNP -0.7 v < 0 -0.026v/IE

Transformer Conventions

ss p

p

s s p p

ps p

s

nv v

n

v i v i

ni i

n

2 '

p s psl

s p p s

pl p s l

p

v n nvR

i i n n

vR n n R

i

Typical RF Amplifier

DC Equivalent AC Equivalent

'

'

0.026 v 1=

1

1 1

Pe p u T u

E m C

c P lT TL

c T TP l

Lr R Q X Q

I g C

R R RB XQ

G X XR R

1 2

1B BE B E

CC B BB

V V I R

V V VI

R R

Book Example: Fig 1-11DC/Bias Analysis

2 k

10 k

1 k

1. Assume is large, so IB can be neglected. Then:

2. Compute IE

3. Compute re

4. Check Assumption 1. Current through the base bias resistors is 1 mA. The base current can be neglected if it is less than 5% of the resistor current, or .05 mA.

…Since > 25, our assumption is valid

12 v

2 k12v 2v

2 k 10 kBV

VB

2v 0.7v1.3mA

1 k 1 kB BE

E

V VI

26mv20

1.3mAer

1.3 mA0.05 mA 25

1 1E

B

II

AC Analysis

3

,

b p loutv t

in in

i R R RvA

v v

3,

p l c mv t

e e c

R R R R gA

r r G

3

31 =

inp l

e p l

in e

vR R R

r R R R

v r

This is a general result that we will use over and over again! (eq 1-24)

k 35 43680Tup XQR

k 2.75012 2

2

ls

pl R

n

nR

k 7.2||||3 plc RRRR

136 20

k 7.2,

e

ctv r

RA

Include the transformer:

dB 1.213.1112

136vA

-6

-12

20 x 10 436

105 x 10TT

LX

C

Parasitic Coil Resistance

Transformed Load Resistance

Total AC Collector Resistance

Transistor Voltage Gain

Frequency Analysis

Mhz 47.32

10

TLCf

2.6436

2700

T

c

c

TL X

R

G

BQ

kHz 5562.6

Mhz 47.303

LdB Q

fBW

Input Impedance ( = 50) 633 2051||k 10||k 21|| eBBin rRR

Power Gain dB 321616

50

6333.11 22

2

2

l

inv

inin

ll

in

lP R

RA

Rv

Rv

P

PA

Saturation Margin

Cutoff Margin

VCC

VE

IC

vC

AC Load Line

IC

iC

vCEVCE

Q Point(quiescent)

Cutoff: iC ~ 0

Saturation: vCE ~ 0

'

1Slope c

c

GR

Max P-P Undistorted Collector Voltage Swing

For Symmetrical Clipping:

If Then cutoff limits amplitude.

If Then saturation limits amplitude.

' optc CE CR V I

' ' optc cR R

' ' optc cR R

'0 P C c CEV I R V

Example 1-4 AC Load Line(Fig 1-11)

IC = 1.3 mA

iC

vCEVCE = 10.7 v

'

1 1Slope 0.37 mA/v

2.7cR k

Max P-P Undistorted Collector Voltage Swing:

V0-pk = 3.5 v

5.1 mA

14.2 v

Maximum Undistorted Power Output

22

0

,max

3.5

120.85 mW

2 100

0.7 dBm

spk

p

ol

nV

nP

R

This will occur when the input voltage is 26 mv 0-pk

or 18 mv RMS

Design is all about verification/validation and iteration. For this DC bias scheme, the optimum total AC collector resistance at resonance should be :

…which is greater than the transformed load resistance of 7.2 k. If the 5 k resistor were eliminated, we would have

DiscussionSince the author neglected to do the load line analysis, he failed to detect the fact that with 40 mV rms input (56.5 mV 0-pk), the collector voltage would want to swing 7.7 V 0-pk. Since the maximum 0-pk voltage swing determined by the load line is 3.5 V the amplifier will go into cutoff and the tops of the sine waves will be clipped.

' opt 10.7 1.3 8.23c CE CR V I v mA k

|| 6 kc l pR R R

This is still less than Rc’(opt), but . . ..

,

8.5 k425

20 c

v te

RA

r

42528.35 29 dB

15vA

2 63328.35 10175 40 dB

50PA

850019.5

436c

LT

RQ

X

3

3.47 Mhz178 kHz

19.5dBBW

. . . and the gains are:

Now

and 11.25 35 8.5c l pR R R k k k

250 15 11.25lR k

1070014.6 15

50p

s

n

n

1 1 1 1 1 110.7

35 8.23 8.23 35 ll l

R kR k k R k k

This requires a transformer turns ratio of:

. . . We can make Rc’ = Rc’(opt) if we can make || 8.23 kc l pR R R

iC

vCEVCE = 10.7 v

'

1Slope 0.1176 mA/v

cR

Max P-P Undistorted Collector Voltage Swing:

V0-pk = 10.7 v

2.56 mA

21.7 v

IC = 1.3 mA

New AC Load Line

Maximum Undistorted Power Output

22

0

,max

10.7

155.1 mW

2 100

7.1 dBm

spk

p

ol

nV

nP

R

This will occur when the input voltage is 25.2 mv 0-pk

or 17.3 mv RMS

Limited by saturation

Performance Summary

The table below summarizes the performance changes introduced by removing the 5k resistor and changing the turns ratio from 12 to 15:

Parameter Before After

Voltage Gain 21 dB 29 dB

Power gain 32 dB 40 dB

Max Undistorted Power -0.7 dBm 7.1 dBm

Bandwidth 556 Khz 176 KHz

Voltage, Current, and Power

2 2,

,

sin 1 sin

sin 1 sin

1 sin cos

2

C C c C

CE CE ce CE

C CE DC t

DC tAV

i I I I

v V V V

P I V P

PP

2

,

,

sin

sin

sin sin

sin

2

ac C CE CE ac

ac CE

ac ac ac C CE

ac DC t

DC tAV

i I v V v

v V

P i v I V

P P

PP

For the Transistor:

For the AC Collector Load:

Assume Maximum Power Output Condition:

Ic = IC Vce = VCE

,DC t C CEP I V