Verifying Power Domains in AeroFONE®

Subrata RoySenior Design Engr, Wireless

10/23/06

www.silabs.com

2

Silicon Labs Portfolio

Products8-bit, 8051, Mixed-Signal MCUsFixed-Function solutions

ProductsFM TunersSiRX™ STB ReceiverXM Satellite Receiver

ProductsModemVoicePowerTiming

ProductsAero® TransceiversAeroFONE®

Power AmplifierRF Synthesizers

Core CapabilitySystem on a Chip

Core CapabilityTuner and Demod Integration

Core CapabilityPLL and High Voltage Expertise

Core CapabilityRF design in CMOS

MCUBroadcastWirelineWireless

3

AeroFONE® based Design

Si4700 FM Tuner

Si4300T Power Amplifier

Si4905 AeroFONE:TX, ABB, DBB, PMU,

Battery Charging Circuitry

CP2102 USB to UART Bridge

4

AeroFONE® Power domains

♦ Motivations for Multiple Power DomainsPower Saving : power what you needPower Saving : power as much as you need;

Voltage scaling for different operating modesBackbias RAM, powerdown ROM

Different voltages needed by the functionNoise isolation

♦ Voltage RegulatorsVpermanentVgpioVext_memoryVcore (Linear regulator, DCDC regulator)VanalogVRFVcustom_digital1Vcustom_digital2

5

Power Control Feedback loop

VoltageRegulators

Power domains

Battery

♦ The chip controls its power♦ Make sure it is not stuck in a bad state; e.g., waiting for input through an

un-powered path while powering-up

control status

P_ctl

Vdd

6

Power Verification-1

♦ Specify Map blocks to Power domain Reset & clocks Voltage modes, dynamic operating modes (load current)input power domains, output power domainspre-power domains : domains powered up before this blockpost-power domains: domains powered after this block is powered

up

♦ Design :RTL: signal connectivity

Interface Cells between power domains (level shifters, logic & noise isolators) have explicit supply pins; these cells are custom designed Analog components have explicit supply pins

7

Power Verification-2

♦ Static Verification: Checks conditions independent of stimulus; assuming specified constraints

all inputs of the domain are definedEvery domain can be reset at power upCorrect level shiftingAll outputs to post-power domains are at 0 during ramp-upLot of painful scripting & reviews

♦ Dynamic Verification : functional operation of the device exercising different power domains & power modes

All possible power up sequencesAll possible sequences of power modesUse AMS methodology

8

Assertions

♦ Check that the system is always in valid system power states

♦ Check that a transition from 1 valid system power state to another valid system power state satisfies all necessary conditions

♦ ExamplesIf Vext_memory is in low power mode then no access to memoryIf Vgpio is in low power mode then no access to gpio pins except for some keypad pins

9

Power Verification-3

♦ Power Goals♦ Design Level: Characterize Power usage of different blocks

in different modes♦ System Level: Use information from Power Characterization

to build system level power modelsExample: DRX2 : 8 slots of p1-mode, 2 slots of p2-mode out of 816 slots

10

Modeling

♦ The quality of dynamic verification depends on modeling♦ Interface Cells: level shift, logic & noise isolators

Voltage levels of power supply pins are modeled in Verilog-AMSAny error in voltage levels is indicated by driving X to logic signals as well as global error flagsLump any effect of the digital load to the Voltage signals of the interface cell

♦ All registers/outputs in a un-powered domain are forced to X♦ The impact of power(vdd) on signals connected to an

interface cell are modeled within the Verilog-AMS model of the interface cell

♦ Voltage RegulatorsModel impact of controls signals on voltage outputsFocus is on modeling the loop between Digital & analog domainfeedback loops within the analog are ignored

11

Interface Cells- AMS model

♦ New disciplines are defined for hv/lv logic in AMS♦ AMS connectrules define the electrical equivalent of

logic_hv/lv♦ AMS automatically inserts connectors based on type

Logic_hv Logic_lvLS_12.CellAMS-model

vdd2vdd1

logic_hv_to_electrical connector

electrical_to_logic_lv connector

12

Summary

♦ Static Verification is well defined but requires lot of adhocscripting – standardization will have big impact here

♦ Dynamic verification Better modeling of effects of system power states using AMSFor unmodeled effects we use constraints to restrict digital behavior

Example: Vgpio low power mode only allows access through some kepad pins

Large number of combinations of power states and their sequencing7 Regulators 3 power on events (power on key, RTC alarm, Charger insertion)Some regulators completely hardware controlled (configured by input pins); some are software controlledBased on ordering of input events and subsequent software control there are many possible sequences

13

Wish List

♦ Efficient way to model effects of power modes/states♦ Extension of our current modeling language (Verilog) but

more efficient than AMS♦ Some Objections

different instances have different power contexts, keep power information seperate from designlanguage constructs can address these issues (e.g., parameters, vunit binding in systemverllog)