VLSI DESIGN 1998, Vol. 7, No. 2, pp. 131-141 Reprints available directly from the publisher Photocopying permitted by license only (C) 1998 OPA (Overseas Publishers Association) Amsterdam B.V. Published under license under the Gordon and Breach Science Publishers imprint. Printed in India. SCOAP-based Testability Analysis from Hierarchical Netlists C. P. RAVIKUMAR a’* and H. JOSHI b aDepartment of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, India; bSynopsys, Inc., Milipitas, CA (Received 27 July 1995) Circuits of VLSI complexity are designed using modules such as adders, multipliers, register files, memories, multiplexers, and busses. During the high-level design of such a circuit, it is important to be able to consider several alternative designs and compare them on counts of area, performance, and testability. While tools exist for area and delay estimation of module-level circuits, most of the testability analysis tools work on gate-level descriptions of the circuit. Thus an expensive operation of flattening the circuit becomes necessary to carry out testability analysis. In this paper, we describe a time and space-efficient technique for evaluating the well known SCOAP testability measure of a circuit from its hierarchical description with two or more levels of hierarchy. We introduce the notion of SCOAP Expression Diagrams for functional modules, which can be precomputed and stored as part of the module data base. Our hierarchical testability analysis program, HISCOAP, reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a systematic manner. The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential. We show that our algorithm also has a straightforward parallel realization. Keywords: Hierarchical testing, testability analysis, SCOAP, hierarchical netlist 1. INTRODUCTION Testability-driven synthesis of digital systems requires a method to measure the testability of a circuit given its structural description. Thus various architectures for the same circuit can be compared and less testable designs can be rejected in favor of the more testable ones. High-level synthesis has traditionally considered cost func- *Corresponding author. tions such as area and performance. However, in the recent past, much effort has been expended on testability-oriented synthesis [9, 1,6]. Many fast algorithms for estimation of area and performance have been reported in the literature; these estima- tion tools can easily take advantage of the hierarchy in the circuit to reduce the computation in arriving at an estimate. However, no testability analysis tool which works on a hierarchical 131
Transcript
VLSI DESIGN1998, Vol. 7, No. 2, pp. 131-141Reprints available directly from the publisherPhotocopying permitted by license only
(C) 1998 OPA (Overseas Publishers Association)Amsterdam B.V. Published under license
under the Gordon and Breach SciencePublishers imprint.
aDepartment of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, India;bSynopsys, Inc., Milipitas, CA
(Received 27 July 1995)
Circuits of VLSI complexity are designed using modules such as adders, multipliers,register files, memories, multiplexers, and busses. During the high-level design of such acircuit, it is important to be able to consider several alternative designs and comparethem on counts of area, performance, and testability. While tools exist for area anddelay estimation of module-level circuits, most of the testability analysis tools work ongate-level descriptions of the circuit. Thus an expensive operation of flattening thecircuit becomes necessary to carry out testability analysis. In this paper, we describe atime and space-efficient technique for evaluating the well known SCOAP testabilitymeasure of a circuit from its hierarchical description with two or more levels ofhierarchy. We introduce the notion of SCOAP Expression Diagrams for functionalmodules, which can be precomputed and stored as part of the module data base. Ourhierarchical testability analysis program, HISCOAP, reads the SCOAP expressiondiagrams for the modules used in the circuit, and evaluates the SCOAP measure in asystematic manner. The program has been implemented on a Sun/SPARC workstation,and we present results on several benchmark circuits, both combinational andsequential. We show that our algorithm also has a straightforward parallel realization.
Testability-driven synthesis of digital systemsrequires a method to measure the testability of acircuit given its structural description. Thusvarious architectures for the same circuit can becompared and less testable designs can be rejectedin favor of the more testable ones. High-levelsynthesis has traditionally considered cost func-
*Corresponding author.
tions such as area and performance. However, inthe recent past, much effort has been expended ontestability-oriented synthesis [9, 1,6]. Many fastalgorithms for estimation of area and performancehave been reported in the literature; these estima-tion tools can easily take advantage of thehierarchy in the circuit to reduce the computationin arriving at an estimate. However, no testabilityanalysis tool which works on a hierarchical
131
132 C.P. RAVIKUMAR AND H. JOSHI
description of the circuit is hitherto known. SinceVLSI systems are built using building blocks suchas adders, multipliers, register files, memories,multiplexers, and busses, traditional gate-leveltestability analysis tools will not be very usefulfor testability estimation. Flattening a hierarchicaldescription to the gate-level is an expensiveprocess, and is prohibitively expensive if it mustbe iterated for each alternate design.
Present work on testability-driven synthesis usessimple measures for testability, such as the numberof self-loops in the structure graph of the circuit.The disadvantage of such a measure is that it isspecific to the style of testing; thus, self-loopsreduce the testability of a circuit when built-in self-test (BIST) is employed. Technology-independenttestability analysis tools such as SCOAP [3],PREDICT [10], and STAFAN [4] would be moreappropriate when the testability of the circuit mustbe gauged without committment to the test style.SCOAP [3] gives integral numerical estimates ofthe controllability and observability of signal linesin a given circuit; a low SCOAP value indicates ahigh testability and vice versa. PREDICT usessignal robabilities as estimates of controllabilityand observability [10]. STAFAN [4] estimatesthese probabilities through a statistical samplingof input vectors, and can be used to predict thefault coverage of a random test set withoutactually performing a fault simulation. A recentlypublished comparative analysis of various testabi-lity analysis tools indicates that SCOAP givesmore authentic measures of testability than manyother estimation tools [2].SCOAP has been effectively used as a testability
analysis tool in.solving the Partial Scan Designproblem in [8]. The partial scan design problem isto determine the smallest subset of flip-flops which,when scanned, would give the maximum faultcoverage; the SCOAP measure of the scannedcircuit gives a good estimate of this fault coverage.Techniques such as Simulated Annealing [8] andGenetic Algorithms [7] have been used for solvingthe scan selection problem. In these algorithms,SCOAP measure is used as a part of the cost
function that estimates the improvement in faultcoverage by modifying the scan set. Since SCOAPis used repeatedly in such applications, it isdesirable to have an efficient implementation ofthe algorithm. In this paper, we describe HIS-COAP-a hierarchical implementation of SCOAPthat operates on a hierarchical netlist descriptionof the circuit. Our algorithm is efficient both inspace as well as in computation time.
In the following section, we explain the theorybehind HISCOAP algorithm, which involves theconcept of SCOAP Expression Diagrams (SED).With an n-input, m-output logic module, a naiveapproach would require the storage of
2m SEDs, corresponding to the zero and onecontrollabilities of each primary output.n SEDs, required for computing the observabi-lities, one for each primary input.
We show that space optimization can beachieved by merging the 2m+ nSEDs into two,one for controllability and another for observabi-lity. We also examine other optimizations inmemory space that are possible in storing theSED.The theory behind the HISCOAP algorithm is
developed in Section 2 and an implementation ofHISCOAP is discussed in Section 3. Performanceresults of HISCOAP on some benchmark pro-blems are described in Section 4. Section 5 presentsour conclusions.
2. SCOAP FOR MODULAR CIRCUITS
Goldstein introduced the SCOAP testability mea-sure for both combinational and sequential circuitsin [3]. With each signal line 1 in the circuit, weassociate six testability measures, CCo(l), CCI(I),CO(l), SCo(I), SC(I), and SO(l). CCo(I) is thecombinational 0-controllability of the signal line l;it represents the number of combinational assign-ments that must be made to other nodes in thecircuit in order to set I to logic 0. The higher thevalue of CCo(I), the poorer the 0-controllability
TESTABILITY ANALYSIS 133
of I. CC(I), the combinational 1-controllability, issimilarly defined. The combinational observabilityCO(l) is a measure of (a) the number of combina-tional nodes between the node I and the primary-outputs, and (b) the number of combinationalassignments necessary to propagate the value onto one of the primary outputs. SCo(I) is thesequential 0-controllability of line 1, and representsthe number of time frames that will be required tojustify the node 1 to 0. SO(l) is the sequentialobservability of node/, and is defined in a mannersimilar to CO(l), except that we count the numberof sequential nodes and the number of sequentialnode assignments.For basic standard cells such as AND, OR,
NAND, NOR and NOT, D flip-flops, and fanoutpoints, Goldstein showed that the controllabilitiesof the gate output can be related to the controll-abilities of the gate inputs through simple alge-braic expressions. These expressions have twotypes of operators, namely the "min" operatorand the "+" operator. As an example, thecontrollabilities of the output c of a two-inputAND gate can be related to the controllabilities ofits two inputs a and b as follows.
CCo(c) min(CCo(a), CCo(b)) + 1 (1)
CC1 (c) CC (a) + CC (b) + (2)
The above equations can be compactly repre-sented in the form of a matrix as explained in [3]. Ifwe have to compute the controllabilities for signallines in a larger circuit composed of basic gates, weapply the expressions for each individual gate. Thestarting point of the evaluation are the primaryinputs, whose combinational controllabilities aredefined to be 1. The SCOAP expressions are theniteratively applied until a convergence is obtained[3]. Observabilities are similarly computed. Thereader is referred to [3] for a more detailedexposition of SCOAP.When large circuits of VLSI complexity are
involved, the above technique can be quiteexpensive both in terms of CPU time and memoryrequirement, the reason being that SCOAP re-
quires a gate-level netlist description as input. Inthis paper, we overcome this problem by comput-ing SCOAP measures from a hierarchical netlist.Hierarchical descriptions of circuits are commonlyused in practice due to their compactness and theirusefulness in mixed-mode simulation. The HIS-COAP algorithm described in this paper makes itunnecessary to flatten the hierarchical netlist into agate-level netlist. The one-time overhead in ourapproach is in the form of a preprocessing step,which computes SCOAP Expression Diagrams foreach module.
For a single output combinational circuit on nprimary inputs labelled Xi, X2,...,Xn, we definetwo types of SCOAP Expression Diagrams forthe output Y. The 0-SED of line Y is adiagrammatic representation of the expressionfor CCo(Y). Refer to Figure 1. The 0-SED is adirected acyclic graph with two types of nodes,labelled ’min’ and ’+’. Each node correspondsto the output of a gate in the circuit, and is labelled’+’ or ’min’. The label for a node x is decidedbased on the nature of the gate whose output is x,and the value to which x must be set in order todrive Y to 0. Each edge of the form (i,j) in the 0-SED is given a weight, equal to the r-controll-ability of line i, if the line must be driven to logiclevel r in order to set Y to 0. In the example circuitof Figure 1, in order to set the outputfto 0, one ofthe signals d or e must be driven to 1. Thus welabel the nodef as ’min’. Further, the edges (e, f)and (d, f) are given weights equal to CCI(e)and CCI(d) respectively. The remaining nodesare similarly labelled and the edges similarlyweighted.The 1-SED for an output Y of an n-input
combinational circuit is defined in a mannersimilar to 0-SED. Figure 2 shows the 1-SEDfor the outputf of the sample circuit of Figure 1.We now explain how the 0-SED and 1-SED are
useful in computing the controllabilities and
134 C.P. RAVIKUMAR AND H. JOSHI
CC(b) CC(a) CCO(a)
CCI(c)__C/b) CCO(a)CCO(c)
CCCI(d)
CCO(O
FIGURE A sample circuit and the 0-SED for its output f.
CCO(b)
observabilities of signal lines in a circuit. Let usfirst restrict ourselves to an n-input, 1-outputcombinational circuit. Given the 0-SED and 1-SED for the primary output Y, we can evaluate theSCOAP combinational controllabilities for all thelines by a simple top-down traversal of the 0-SEDand the 1-SED. In the example of Figure 1, thecalculations proceed as follows.
CC (b)CC (a)CCo(a)CCo(b)CC (c) 2 / depth
CCo(c) + depth
CC (e) min(CC (b) + CC (c)) + depth1 / depth
CC (d) min(CCo(a) + CCo(c)) + depth
+ depth
CCo(f) min(CCl(e) + CCI(d)) + depth1 / 2. depth
The 1-SED of Figure 2 can be used similarly tocompute the remaining controllabilities. Thussimple breadth-first traversal of the 0-SED and
CCl(O
FIGURE 2 The 1-SED for outputf of the sample circuit.
1-SED is sufficient to compute all the controll-abilities in a combinational circuit.
2.1.1. Storage Optimization
We first note that both the 0-SED and 1-SED neednot be stored in memory, since one can beobtained from the other through a complementoperation. Complementing involves changing
TESTABILITY ANALYSIS 135
procedure Control(Y)(* Y is the output of combinational circuit *)begin
Locate the 0-SED of Y;While traversing the 0-SED of l/" top downbegin
Let be the output of the current node;Let the label on edge beCompute
endComplement the 0-SED to obtain the 1-SED ofWhile traversing the 1-SED of Y top downbegin
Let be the output of the current node;Let the label edge be COo(Z); (* Note that *)Compute CCo();
endend
FIGURE 3 Computing SCOAP controllabilities from opti-mized SED.
CC0(a)
CCI(e)cCI(d){CC0(0, eel(0}
FIGURE 4 SED-C for primary outputf of sample circuit.
every’+’ label to a ’min’, changing every ’min’label to a ’+’, changing the weight CCI(X) toCCo(x) and changing the weight CCo(x) to CCI(X).The above technique works for all circuitscomposed of NAND, NOR, AND, OR, andNOT gates only. For an example, the reader isreferred to the 0-SED of Figure 1; complementingit using the rules mentioned above yields the 1-SED of Figure 2. When this optimization techni-que is used, the procedure of Figure 3 wouldsuffice for computing all the SCOAP controllabi-lities.
Further storage optimization can be achieved instoring the 0-SED itself, by noting the following.If, for some signal x, both CCo(x) and CCi(x)appear as edge weights in the 0-SED, then effort isduplicated in computing them again from the1-SED. We can eliminate this redundancy bydeleting the subgraph supported on the edgeweighted by CCI(X) from the 0-SED. To illustratethis point, we refer the reader to the 0-SED inFigure 1. Note that both CCl(c) and CCo(c)appear in the 0-SED. We can eliminate the nodessupported by CCI(C) to obtain the compact SEDshown in Figure 4. However, we must add a fanoutedge (marked CCI(C) in the Figure) to enable thecomputation of all the controllability values thatdepend on CCl(c). Using the compact 0-SED, thecomputation ofcontrollability values is modified asshown in Figure 5. We refer to the compact SED asSED-C in this paper.
procedure Control-C (Y)(* Y is the output of combinational circuit *)begin
Locate the compact SED of Y;While traversing SED-C of Y top downbegin
Let be the output of current node;compute CC0();complement the node label;compute
endend
FIGURE 5 Computation of controllabilities from SED-C.
We now consider the general case of an n-input,m-output combinational circuit and explain howthe above optimizations can be used. Consider thecompact SED-C for two primary outputs Y andY2; there are controllability terms that arecommon to their SED-C. Instead of recomputingthese controllabilities while traversing the SED-Cof Y2, the controllability values can be passed ondirectly as inputs to the SED-C of Y2. To enablethis, we create links from the SED-C of Y1 toSED-C of Y2.
2.2. SED for Observability Calculation
After the signal controllabilities have been com-puted, the signal observabilities can be calculatedusing algebraic expressions as discussed in [3].Once again, we use an expression diagram forrepresenting the set of observability expressionsassociated with a primary input X. For the input a
136 C.P. RAVIKUMAR AND H. JOSHI
of the sample circuit in Figure 1, the relevant SEDis shown in Figure 6. The SED-O is also an aeyeliedirected graph with nodes labelled ’+’ or ’min’.The edges of an SED-O are weighted with theappropriate controllability or observability value.
It may be observed that some observabilityvalues appear on more than one SED-O in a givencircuit. For instance, CO(e) and CO(c), which arecomputed while traversing the SED-O for primaryinput a, may be directly used in traversing theSED-O for primary input b. In order to enable thisreuse, we add links from the SED-O of a to SED-O of b. Thus, insome sense, the SED-O for all theprimary inputs are threaded together into oneobservability expression diagram. Figure 7 showsthe complete observability expression diagram forall the primary inputs of the sample circuit ofFigure 1.
2.3. Sequential Circuits
The SCOAP expression diagrams SED-C andSED-O introduced in the previous section applyonly to directed acyclic structure graphs. The sameexpression diagrams can be used for computingtestability values for sequential circuits (namely,SC1, SCo, and SO); for this, the SED-C and SED-O are to be traversed iteratively until the testabilityvalues converge, as suggested in [3]. When extend-
FIGURE 6 SED-O for primary input a of sample circuit. Thenotation a-> is used to indicate the first fanout branch ofsignal a.
FIGURE 7 SED-O for the entire sample circuit.
ing the SED-C and SED-O to sequential circuits,we must bear in mind the following two points.
The flip-flops are represented by nodes that arelabelled ’*’. (In this paper, we shall assume thatonly D-type flip-flops are used as memoryelements in the circuit. We also allow permitfeedback paths without memory elements in thesequential circuit). In an SED-C, such a nodereceives the eontrollabilities of three input lines,namely, the D-input, the reset line, and the clockline; the node has a single output edge corre-sponding to the controllability value of the Qoutput. SCo(Q) and SC(Q) can be related to thecontrollabilities of the three inputs D, reset, andclock using the expressions given in [3]. In anSED-O, a node with label ’*’ receives four inputlines corresponding to the three eontrollabilitiesand one observability (namely SCl(Cloek),SC0(Cloek), and SC0(Reset), SO(Q)).Due to feedback, there will be cycles in theresulting SED-C and SED-O. The testabilityvalues on the feedback lines are unknown tobegin with, and must be initialized to .Further, to make use of the top-down traversalalgorithm introduced in the previous section,we need to break the cycles in the SED-C andSED-O by removing the edges.
A sequential circuit is shown in Figure 8 and theSED-C and SED-O for this circuit are given inFigure 9.
TESTABILITY ANALYSIS 137
d->l
FIGURE 8 A sequential circuit.
CCl cco
{CCO(a),CCl(d)}
SED-C
CCO()mCCO(b) CCO(cd)}(e), /CCO(c),CCl()} CO(d.>l)
CO(a)
CO(a)
SED-O
FIGURE 9 SED-C and SED-O for the example sequentialcircuit.
2.4. Storage Requirements
For a combinational circuit with n primary inputs,g gates each with a fan-in off or less, m primaryoutputs, and I internal nodes, the SED-C containsI+m nodes and no more than f.g edges. If thenumber of fanout branches is fo, The SED-Ocontains I+ n +fo nodes and no more thanf. (I+ n+fo) + n edges. Since a fixed amount of storage isrequired per node and per edge, we can concludethat the space complexity for combinationalcircuits is linear in the number of gates in themodule. For a sequential circuit, the storagerequirements for SED-C and SED-O are of thesame order of magnitude.
3. HISCOAP ALGORITHM
Consider a hierarchical netlist description of acircuit such as an 8-bit array multiplier. Thecircuit is composed of multiplier cells connectedusing a regular interconnection pattern. In orderto compute the SCOAP testability of such amodular design, we can take advantage of a two-level hierarchy in the description. The top leveldescribes the interconnection among the multi-plier cells, and the second level describes the gate-level netlist of a single cell. A single copy of SED-Cand SED-O for the multiplier cell is sufficient forcomputing the SCOAP testability values for all thelines in the multiplier circuit. The HISCOAPalgorithm works on the hierarchical netlist de-scription of the multiplier. The overall HISCOAPalgorithm is described below in pseduo-code(procedure HISCOAP-NonFeedBack). The algo-rithm uses breadth-first traversal for visiting all themodules in the circuit. This algorithm applies onlyto circuits without any feedback. (Note that a non-feedback circuit does not mean the circuit is purelycombinational. The modules of the circuit may besequential circuits such as shift registers, serialadders, etc. However, no feedback lines must existfrom one module to another). It is easy to extendthe algorithm of HISCOAP-NonFeedBack to thecase when the circuit does have feedback lines. Thealteration required is to initialize the controllabil-ity values on all the non-PI lines to o, initialize theobservability values on all non-PO lines to o.
Within the breadth-first traversal, we do not testfor the condition that all input controllabilities areavailable or all output observabilities are available.The entire algorithm is repeated until the test-ability values on all the lines have converged tosome value.
procedure HISCOAP-NonFeedBack ( )begin
for each type of module M in the circuit doif SED-C(M) or SED-O (M) not alreadyavailable
in module database then
138 C.P. RAVIKUMAR AND H. JOSHI
beginconstruct SED-C (M) and SED-O (M);enter the expression diagrams in moduledatabase;
endQueue: NULL;for each primary input I in the circuit do
add the module fed by I to Queue;while (Queue is not empty) dobeginE := delete (Queue);if module instance E is colored then skip;if all input controllabilities to module Eare available then
begincolor module instance E;Find the SED-C for module type of E;Using the input controllabilities of E,initialize the edge weights of SED-C;Traverse SED-C and find the controllabilitieson internal nodes associated with E;
Update the output controllabilities in thetestability table;
for each primary output O of module Eadd the module fed by O to Queue;
end elseadd E to Queue;
endQueue: NULL;for each primary output O in the circuit do
add the module whose output is O to Queue;Remove the color on all module instances;while (Queue is not empty) dobeginE := delete (Queue);if module E is colored then skip;if all output observabilities of module E
are available thenbegin
color module E;Find the SED-O for module type of E;Using the input controllabilities and
output observability of E,initialize the edge weights of SED-O;
Traverse SED-O and find the observabil-itieson internal nodes associated with E;
Update the input observabilities in thetestability table;
for each primary input I of module Eadd the module which feeds I to Queue;
end elseadd E to Queue;
endend
4. EXPERIMENTAL RESULTS
The HISCOAP algorithm described in the pre-vious section has been implemented on a Sun/SPARC workstation in programming language C.The software is composed of about 3000 lines ofcode.Both feedback and non-feedback circuits can be
handled by our program. We have tested theprogram on a number of benchmark circuits suchas
n-bit Carry Look Ahead Adder (CLA) com-posed of 4-bit CLA modules. We use thenotation addn_hl to describe these circuits.n-bit CLA composed of full-adders and CarryLookahead circuitry. We use the notation addnto describe these circuits.n-bit array multiplier composed of multipliercells. We use the notation multn_hl to describethese circuits.Bit-serial adder composed of shift registers anda full adder.Some ISCAS 89 sequential benchmarks.
We have compared the performance of theHISCOAP algorithm with that of a gate-levelimplementation of SCOAP. In order to accom-plish this, we have implemented a circuit flattenerwhich uses macro expansion to convert a hier-archical description into a gate-level description.
TESTABILITY ANALYSIS 139
Table I compares the running time of HIS-COAP working on a hierarchical netlist with thatof the conventional SCOAP algorithm working ona gate-level netlist. Several observations can bemade from this table. First,the running time of theHISCOAP algorithm grows modestly with in-creasing circuit size. Thus, the execution time for a64-bit CLA composed of 4-bit CLAs grows onlyby a factor of 3 in comparison to the running timefor a 4-bit CLA. Thus, a 16-fold increase in circuitsize does not reflect in the execution time ofHISCOAP. This can be contrasted with the runtime of the SCOAP algorithm, where the executiontime increases by a factor of 87. Secondly, we notethat HISCOAP offers a substantial reduction inexecution time when compared to the SCOAPalgorithm. For instance, the gate-level SCOAPalgorithm requires 12.28 seconds (excluding thetime for flattening the hierarchical description) forhandling the circuit add32_hl, whereas HISCOAPtakes only 0.33 seconds for the same circuit. Thecomputational overhead in HISCOAP includes thereading of SED files and initialization of the SEDdata structures. Thus, if the circuit size is small incomparison to the module size, this overhead canovershadow the advantages of hierarchical imple-mentation of SCOAP. For instance, HISCOAPshows a speedup of less than for the circuitadd4_hl. We conclude that HISCOAP is onlymeritorious when used with circuits which have alarge number of copies of the same module. Thereis also an overhead of storage space in HIS-COAP-the SED data structures must be stored
for each type of module. This overhead will benegligible when the circuit has many copies of thesame type of module. Finally, the complexity ofeach module also plays a crucial role in determin-ing the execution time of HISCOAP. In thecircuits addn_hl, the module is fairly complex byitself, namely, a 4-bit CLA. On the other hand, inthe circuits addn, the module is a much simplerone, namely, a full adder. HISCOAP works bestwhen the circuit has a number of copies of acomplex module, as in the case of add32_hl
(execution time is 300 ms, module is 4-bit CLA).In contrast, consider the add32 circuit, where themodule is a full adder and the execution, time is 500ms. When there is only one copy of a complexmodule, as in the case of add4_hl, the executiontime of HISCOAP is somewhat larger than that ofgate-level SCOAP, due to overheads in maintain-ing the SCOAP expression diagrams.
Table II shows the results of HISCOAP on n-bitarray multiplier circuits, 4 _<n_< 32. When HIS-COAP was executed on a gate-level description ofthe 4-bit multiplier, the execution time (withoutcounting the time for flattening) was 330 ms.HISCOAP took 5450 ms to process a gate-leveldescription of an 8-bit array multiplier. We do nothave HISCOAP results for gate-level 16-bit and32-bit array multipliers since the flattening opera-tion took an excessively large amount of time andhad to be aborted.The core memory requirement of HISCOAP is
substantially lower than that of SCOAP. This wasclearly apparent in one of our experiments dealing
TABLE Comparison of Execution Times of SCOAP and HISCOAP for CLA circuits. The time for flattering the hierarchicalcircuit description is not included
Circuit Number of Number of Times (ms) Time (ms)Modules Gates (HISCOAP) (SCOAP)
TABLE II Results on n-bit array multiplier circuits
Number of Number of ExecutionModules Gates Time (ms)
Memory(pages * ticks)
481632
16 208 1.00 77764 416 340 1719
256 3328 2440 138811024 13312 29000 175742
Circuit Number ofModules
TABLE III Sample runs on sequential circuits
Types of Number ofModules Standard Cells
Time Memory(ms) (pages * ticks)
Serial Adder 4 3 47 100 1418s27 13 80 731
with the 32-bit array multiplier. The gate-leveldescription of the circuit demanded a largeamount of core memory, leading to disk swapping,in turn leading to an excessively large run time.When we attempted to flatten the 32-bit multipliercircuit on an HP/9000 computer with 4 MB ofmain memory, the program failed to completeeven after 4 hours of execution time. On the otherhand, the HISCOAP algorithm was able to handlethe 32-bit multiplier example in 29 seconds.Although several ISCAS combinational and
sequential benchmarks were available to us, wedid not attempt extensive experimentation onthese benchmarks since these circuits are gate-levelcircuits. To the best of our knowledge, no bench-mark circuits are available in public domain forhierarchical testing. However, we constructedsome fictitious circuits by duplicating two or morecopies of circuits such as s27, and adding intercon-nections between them. Table III shows the resultson two sequential circuits a serial adder (using afull adder, 3 shift registers, and a flip-flop asmodules) and the circuit s27 using NAND gates asmodules.
5. CONCLUSIONS
We have presented a hierarchical implementationof the well known SCOAP testability analysisprogram. Our algorithm, called HISCOAP, has
been implemented on a Sun/SPARC workstationand has been tested against a number of largebenchmark examples. The hierarchical algorithmapplies to both sequential and combinationalcircuits. The algorithm takes a hierarchical de-scription of the circuit as input. Presently, a two-level hierarchy is employed in the hierarchicalnetlist description. It is easy to extend the ideaspresented in this paper to handle multiple levels ofhierarchy. Such an extension would imply that theSCOAP Expression Diagrams must themselves beimplemented in a hierarchical fashion (See [5] fordetails). The HISCOAP algorithm gives a two-sided advantage over the conventional SCOAPalgorithm; first, the run time of the HISCOA.Palgorithm is significantly smaller. Secondly, thememory requirement of the HISCOAP algorithmis substantially lower, which in turn gives it anadvantage in terms of execution time due toreduced disk swap operations.
Acknowledgements
We thank the two anonymous referees whosefeedback helped us in improving the first draft ofthis paper. Initial discussions with Mr. H. Rasheedwere useful. We thank Dr. A. Muzumder and Dr.R. Jain for providing us with gmalloc.c. We arethankful to the Computing Services Center of IITDelhi for providing the facilities to carry out thiswork.
TESTABILITY ANALYSIS 141
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Authors’ Biographies
C. P. Ravikumar obtained his Ph.D. in ComputerEngineering from the Department of ElectricalEngineering Systems, University of SouthernCalifornia, in 1991. Since then, he is an AssistantProfessor in the Department of Electrical En-gineering at the Indian Institute of Technology,Delhi. He is the Indian editor of the InternationalJournal of VLSI Design and is on the editorialboard of the Computers and Informatics journal.His research interests are in the areas of VLSIDesign Automation and Testing, CombinatorialOptimization, Interconnection networks for multi-processors, and parallel algorithms.Hemant Joshi obtained his Master’s degree in
Computer Technology in December 1993 from theDepartment of Electrical Engineering, Indian In-stitute of Technology. He is currently an engineerworking with Synopsys, Inc. His research interestsare in the areas ofVLSI design, testing, and HDLS.
