SEED: The Big New DevelopmentSEED: The Big, New Development

2

System-Efficient ESD Design• In 2010, Industry Council releases White Paper 3,

advocating for system-efficient ESD design (SEED)– SEED: a board-chip co-design methodology for resilienceSEED: a board chip co design methodology for resilience

to IEC 61000-4-2 stress– Circuit-level simulation is used to find ESD pulse amplitude

and shape at chip pin after filtering by TVS and/or other b d ton-board componentsTLP data used to determine if this “residual” stress is

above safe limit2011 EOS/ESD Symposium: Four papers on circuit level• 2011 EOS/ESD Symposium: Four papers on circuit-level simulation of system-level ESD– SEED concept was adopted quicklyDetailed methodolog aries bet een research gro psDetailed methodology varies between research groups,

best practices still to emergeSee 4B.2 (Lee et al.), 5B.3 (Besse et al.), 6A.2

(Monnereau et al ) 6A 4 (Johnsson and Gossner)(Monnereau et al.), 6A.4 (Johnsson and Gossner)Topic now being presented in archival journals, e.g.,

Scholz et al., in IEEE T-DMR 2012.3

Circuit-level Simulation of System-level ESD

SPICE model of ferrite bead(6A.4)

4

System electrical model (5B.3)

Simulation of System-level ESD – An Alternate Approachpp

[Zhang 2011 EMC Symp ]

• Models featured on previous slide are computationally efficient but not easily adapted to indirect discharges

[Zhang, 2011 EMC Symp.]

y p g• Is a coupled full-wave simulation / circuit simulation

approach needed at times?5

Functional Failures (Upsets)

• SEED methodology ensures that the residual IESD entering the IC is ESD gless than Ifail– Hard failure (physical damage)

is avoidedPart of power management is avoided

• Design-dependent soft failure may occur

Temporary loss of function

chip for automotive MCU

– Temporary loss of function– Automatic recovery, or manual

reset• Besse et al. performed experiments

to better understand soft failures– Micro. Rel., Sept.-Nov. 2011 ESD causes loss of current 

6

reference; reset is generated

Since we’re on the subject of system-level ESD …

A th ti th t d i f t l l ESD li bilit d t• Authors caution that design for component level ESD reliability does not necessarily yield a component with good resilience to system-level ESD and other EOS → Important to mitigate EOS by design

– Kaschani and Gaertner, 2011 EOS/ESD Symp. 7

Circuit-level Simulation of Component-level ESD—Now Mainstream

8

EDA Tools for ESD Analysis• Development of such tools continues to be a big

topicA f ll i thi t th 2011 EOS/ESD• A full session on this at the 2011 EOS/ESD Symposium (5A) and several papers on related topics in other sessionstopics in other sessions

ESD reliability can be considered during chip floor-planning (5A 3 Chang)planning (5A.3, Chang)

9

EDA, cont’d

ESD discharge path g presistance checker (Trivedi, 5A.4)

ESD current density checker (Mitra, 5A.2)

10

Circuit-level Simulation of ESDW k hi hli ht d di lid f hi h l l• Works highlighted on preceding slides perform high-level analysis

• Circuit-level simulation may also be a part of ESD EDA– CDM simulation requires compact models that are

valid on a very short time scale

Pulsed I‐V characteristic of a 5V NMOS differs when 200ps pulses are used instead of 1.2ns(S. Ruth et al., 2011 ESD Symp.)

11

Familiar Topics in ESD R&DFamiliar Topics in ESD R&D

12

Still Fighting Low It2 of HV MOSD i t d d NMOS f• Drain extended NMOS for HV applications

• Low It2 due to current o t2 due o cu efilamentation upon base push-outNew countermeasures• New countermeasures proposed

• Featured work (A. Salman(et al., 2012 IRPS)

– Silicide block N+ drain to improve It2 with little impactimprove It2 with little impact on Rds,on

• See also 2011 EOS/ESD Symp.: 1B 3 (Fujiwara) 1B 4 (Shrivastava)1B.3 (Fujiwara), 1B.4 (Shrivastava)

• See also Aliaj et al., Micro Rel, 12/11.

13

New Process Technologies are Always of Concern/Interest

Fin-based ESD diodes

[Thijs, 2011 ESD Symp.]

• Gated Diodes, Lgate=70nm, HKMG process• Despite lower mA/μm wide fins preferred for a fixed

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• Despite lower mA/μm, wide fins preferred for a fixed layout area– Lower Ron, better voltage clamping

Co-design for High Performance and ESD Reliability—Now Accepted for RF andReliability Now Accepted for RF and

High-speed ICs

15

ESD Reliable, mm-Wave CMOS ICs

[Raczkowski et al., 2012 IEEE SiRF]

• Co-design allows for ESD protection regardless of operating frequencyoperating frequency– Now accepted that high frequency operation does not

preclude ESD protection16

Co-design being Widely Practiced

Varactor protection devices were co-designed with 24-GHz LNA and laid out for maximum ESD resilience.[T i IEEE Mi Wi l[Tsai, IEEE Microwave Wireless Comp. Lett., July 2011]

17

ESD Protection for Broadband IO

1) 2nd protection must be small 2) Usual scheme

[Okushima, 2011 ESD Symp.] 18

3) Proposed protection circuit 4) Overshoot eliminated(CDM level improved, too)

Works on Component-level ESD Test Methodology

19

ESD qualification testing doesn’t replicate all real-world events

• Case study: IC field returns with CDM-like failure signature but component had passed 2kV CDM

I about 4 A– Ipeak about 4 A• Charged styrofoam cup used to generate higher stress;

antenna based ESD event detector used to measure amplitudeamplitude– For Ipeak > 20 A, real world damage was replicated– Tape and reel process might be culprit

On chip protection was modified– On-chip protection was modified

Charged cup event waveform

[Jahanzeb, 2011 ESD Symp.]

20

Sub-critical, ESD-induced Damage

• ESD protection should be able to survive multiple IEC 61000-4-2 type stress events ypduring a product’s lifetime

• Study cumulativeStudy cumulative damage from repetitive stressing

• Diatta et al IEEE• Diatta et al., IEEE T-ED, Jan. 2012.

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Waveform at Scope ≠ Waveform at DUT

• Inverse filtering can mitigate bandwidth limitation of scope [Maloney, 2011 ESD Symp.]y p ]

• Directional couplers eliminate bandwidth li it ti f ltlimitation of voltage probes [Gillon, 2011 ESD Symp.]y p ]

22

Noteworthy Studies (but no unifying theme)

23

Protection Circuit for VPP Pin

• Cannot connect aconnect a diode from VPP to VDDPP DD

• ESD bus based solution is suitable

• Ker, IEEE JSSC, Feb. 20112011.

24

Advanced Packaging and ESD Reliability[Olson, 2011 CICC]

Die stackingDie stacking improved CDM reliability of cross-domain

#Fail/#Tested Pos.:Neg. Vpre-charge

StressPolarity

Stress Location

circuits

1/3 1000 Both All pins3/3 1500 Both All pins1/2 2000 Positive Output

Single Die2/3:1/1 2000 Positive/

Negative VDD2

2/3:2/2 2000 Positive/ VSS22/3:2/2 2000 Negative VSS2

Stacked Die 1/3 2000 Positive/ Negative All Pins

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CDM Protection for SiGe BiCMOS RFICs

• High It2/C of SCR is favorable but slow turn-on willHigh It2/C of SCR is favorable but slow turn on will limit its ability to protect gate oxide or base-emitter junction

• A low-C SCR with fast turn-on is demonstrated• A low-C SCR with fast turn-on is demonstrated• Parthasarathy et al., 2011 BCTM

26

Not Everything is Silicon!Not Everything is Silicon!

27

ESD occurs in components other than Si ICs

• GaN HEMTs used in power amps• Investigate candidate protection deviceInvestigate candidate protection device

– Schottky diode• Chen et al., 2011 EOS/ESD Symp.

28

ESD Reliability of Non-Si ICs, cont’dLeakage current →

nt →

TLP curren

T

Vt1 = 21 V

• Low capacitance ESD protection for high power RF I/O

TLP voltage →

– Clamp comprised of GaAs pHEMT devices– C < 100 fF– Muthukrishnan et al., 2011 IEEE CSICS 29

ESD R&D: The Next GenerationESD R&D: The Next Generation

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EOSESD’11: Student Papers Caught Attendees’ Attention

ESD gun stress of NPN

• Y. Cao et al., “ESD simulation with Wunsch-Bell based behaviorWunsch-Bell based behavior modeling methodology”

• PWL device models. R = f(time)Time dependence introduced to–Time-dependence introduced to capture self-heating (but also used to capture delayed turn-on)

M d l t ti ll ffi i t• Models are computationally efficient and applicable to ESD stresses on widely varying time scales 31

Best Paper Award

EOSESD’11: Student Papers, cont’d

N. Jack and E. Rosenbaum

2 53

V) Dark

Rosenbaum, “Voltage monitor circuit for ESD diagnosis”

0.51

1.52

2.5

VM

Out

put

(V Ambient LightdiagnosisOutstanding Paper Award

5.00(V)

00.5

0 2 4 6 8 10 12 14

V

Time (min)

• ICDM measured at pogo pin doesn’t provide information about what is happening inside the chip2 00

2.75

3.504.25

at th

e re

ceiv

er

happening inside the chip• VMC records on-chip voltage for

later read-out32

1.25

2.00

Small TXPMOS

Large TXPMOS

LocalClamp

LocalAPD

Vgs

a

Bibliography1. J. Lee et al., “A study of a measurement and simulation method on ESD noise

causing soft-errors by disturbing signals,” EOS/ESD Symp., pp. 274-278, 2011.2. P. Besse et al., “ESD system level characterization and modeling methods

applied to a LIN transceiver,” EOS/ESD Symp., pp. 329-337, 2011.pp , y p , pp ,3. N. Monnereau et al., “Investigating the probability of susceptibility failure within

ESD system level consideration,” EOS/ESD Symp., pp. 343-348, 2011.4. D. Johnsson and H. Gossner, “Study of system ESD codesign of a realistic

mobile board ” EOS/ESD Symp pp 360 369 2011mobile board, EOS/ESD Symp., pp. 360-369, 2011.5. M. Scholz et al., “System-level ESD protection design using on-wafer

characterization and transient simulations, accepted for publication in IEEE Trans. Dev. Mat. Rel., 2012. (Early access version available on-line.)

6. J. Zhang et al., “Modelling electromagnetic field coupling from an ESD gun to an IC,” IEEE Symp. EMC, pp. 553-558, 2011.

7. P. Besse et al., “Identifying electrical mechanisms responsible for functional failures during harsh external ESD and EMC aggression ” Micro Rel vol 51failures during harsh external ESD and EMC aggression, Micro. Rel., vol. 51, pp. 1597-1601, 2011.

8. K. Kaschani and R. Gaertner, “The impact of electrical overstress on the design, handling and application of integrated circuits,” EOS/ESD Symp., pp. 220-229, 20112011.

9. N. Chang et al., “Efficient multi-domain ESD analysis and verification of large SoC designs,” EOS/ESD Symp., pp. 300-306, 2011.

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Bibliography, cont’d10.S. Mitra et al., “A current density analysis tool to identify BEOL fails under ESD

stress,” EOS/ESD Symp., pp. 294-299, 2011.11.N. Trivedi et al., “An automated approach for verification of on-chip interconnect

resistance for electrostatic discharge paths,” EOS/ESD Symp., pp. 307-314, g p , y p , pp ,2011.

12.S. Ruth et al., “A CDM robust 5V distributed ESD clamp network leveraging both active MOS and lateral NPN conduction,” EOS/ESD Symp., pp. 7-15, 2011.

13 A Salman et al “Engineering optimal high current characteristics of high13.A. Salman et al., Engineering optimal high current characteristics of high voltage DENMOS,” IEEE Int. Rel. Phys. Symp., pp. 3E.1-3E.6, 2012.

14.S. Fujiwara, “Source engineering for ESD robust NLDMOS,” EOS/ESD Symp., pp. 53-58, 2011.

15.M. Shrivastava, “ESD robust DeMOS devices in advanced CMOS technologies,” EOS/ESD Symp., pp. 59-68, 2011.

16.B. Aliaj et al., “Self protection capability of integrated NLDMOS power arrays in ESD pulse regimes ” vol 51 no 12 pp 2015-2030 2011ESD pulse regimes, vol. 51, no. 12, pp. 2015 2030, 2011.

17.S. Thijs et al., “On gated diodes for ESD protection in bulk FinFET CMOS technology,” EOS/ESD Symp., pp. 27-34, 2011.

18.K. Raczkowski et al., “60 GHz low noise amplifiers with 1 kV CDM protection in 40 LP CMOS ” IEEE M SiRF 9 12 201240 nm LP CMOS,” IEEE Mtg. SiRF, pp. 9-12, 2012.

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Bibliography, cont’d19. M-H Tsai and S. Hsu, “A 24 GHz low-noise amplifier using RF junction varactors

for noise optimization and CDM ESD protection in 90 nm CMOS,” IEEE Microwave Wireless Comp. Lett., vol. 21, no. 7, pp. 374-376, 2011.

20 M Okushima and J Tsuruta “CDM secondary clamp of RX and TX for high20. M. Okushima and J. Tsuruta, CDM secondary clamp of RX and TX for high speed SerDes application in 40 nm CMOS technology,” ,” EOS/ESD Symp., pp. 94-99, 2011.

21. A. Jahanzeb et al., “Capturing real world ESD stress with event detector,” ,”21. A. Jahanzeb et al., Capturing real world ESD stress with event detector, , EOS/ESD Symp., pp. 197-201, 2011.

22. M. Diatta et al., “Understanding the failure mechanisms of protection diodes during system level ESD: toward repetitive stresses robustness,” IEEE Trans. Elec. Dev., vol. 59, no. 1, pp. 108-113, 2012.

23. T. Maloney and A. Daniel, “Filter models of CDM measurement channels and TLP device transients,” ,” EOS/ESD Symp., pp. 386-394, 2011.

24 R Gill t l “U i di ti l l t th b d idth24. R. Gillon et al., “Using directional couplers to overcome the bandwidth limitations of IV-probes in TLP measurements,” ,” EOS/ESD Symp., pp. 395-401, 2011.

25 M-D Ker et al “Electrostatic discharge protection design for high-voltage25. M D Ker et al., Electrostatic discharge protection design for high voltage programming pin in fully-silicided CMOS ICs,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 537-545, 2011.

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Bibliography, cont’d26. N. Olson et al., “CDM-ESD induced damage in components using stacked-die

packaging,” IEEE Custom Int. Circuits. Conf., pp. 6-3.1-6-3.4, 2011.27. S. Parthasarathy et al., “Design of SCR devices for SiGe BiCMOS applications,”

IEEE Bipolar/BiCMOS Circuits Tech Mtg pp 235 238 2011IEEE Bipolar/BiCMOS Circuits Tech. Mtg., pp. 235-238, 2011.28. S-H Chen et al., “HBM ESD robustness of GaN-on-Si Schottky diodes,”

EOS/ESD Symp., pp. 147-154, 2011.29 S Muthukrishnan et al “A novel clamp based ESD protection structure for high29. S. Muthukrishnan et al., A novel clamp based ESD protection structure for high

power RF ports in GaAs pHEMT process,” IEEE Compound Semiconductor IC Symp., 2011.

30. Y. Cao et al., “ESD simulation with Wunsch-Bell based behavior modeling gmethodology,” EOS/ESD Symp., pp. 187-196, 2011.

31. N. Jack and E. Rosenbaum, “Voltage monitor circuit for ESD diagnosis,” EOS/ESD Symp., pp. 370-378, 2011.

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