TEL Technology Center, America, LLC - imec
Selective isotropic etching of Group IV
semiconductors to enable gate all around
device architectures
S. Kal1, C. Pereira1, Y. Oniki2, F. Holsteyns2, J. Smith1, A. Mosden1, K. Kumar1, P. Biolsi1, T Hurd1.
1TEL Technology Center, America, LLC, USA2 Imec, Belgium
SPCC, April 10, 2018
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
2
Chemical Oxide Removal (COR) Reaction Mechanism:
Case for SiO2 etch
HF and NH3 adsorb on the SiO2 surface, reacting to form (NH4)2SiF6 (Ammonium
Fluorosilicate - AFS)
NH3 catalyzes a desired reaction pathway
SiO2
HF
HF
NH3
NH3(NH4)2SiF6
Slide courtesy: Tokyo Technology Solutions
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
3
A typical oxide etch process with Certas
12nm Oxide Removal Recipe
~4X Volume Expansion Pristine oxide surface regenerated
post PHT
(COR PHT) process can be
repeated in cyclic fashion to
meet process requirements
AFS Thickness=50.02 nm
Post COR etch
AFS
SiO2 SiO2
Post PHT treatment
Ability to:
• Process with PR
• Additional knob to control:
Pattern wiggling
Pattern damage
Slide courtesy: Tokyo Technology Solutions
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
4
HM/dummy poly
Si/SiGe fin
Spacer
N
P
SiGe
SiGe
SiGe
SiGe
Spac
er
Dmy OX
Dmy
poly
Spacer formation
Si
Si
Si
Si
SiGe
SiGe
SiGe
SiGe
Fin recess
Si
Si
Si
Si
SiGe
SiGe
SiGe
SiGe
Cavity etch
Si
Si
Si
Si
SiGe
SiGe
SiGe
SiGe
Si
Si
Si
Si
SiGe
SiGe
SiGe
SiGe
Inner
spacer
Si
Si
Si
Si
Inner spacer formation
HM: SiN (or SiCN, SiOC)
Spacer: SiOxCyNz
Inner spacer: SiOxCyNz (would be different from spacer material)
INNER SPACER MODULE
Nanosheet Selective Etches
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
5
Nanosheet Selective Etches
SD EPI
EPI
SiGe
SiGe
SiGe
SiGe
Inner
spacer
Si
Si
Si
Si
Spac
er
Dmy OX
Dmy
poly
CESL/ILD0
SiGe
SiGe
SiGe
SiGe
Si
Si
Si
Si
ILD0
CESL
Channel
release
Si
Si
Si
Si
HKMG
Si
Si
Si
Si
MG
HK
SiGe
SiGe
SiGe
SiGe
Si
Si
Si
Si
Dummy poly/OX
removal
N-EPI: SiGe:B, P-EPI: Si:P
CESL: SiN
ILD0: SiO2
Dummy poly (dummy gate): a-Si
SD/ILD0/RMG MODULES
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
6
Selective SiGe etch for Nanowire
Partial release :
• SiGe etch =5-6 nm (each side,
total = 10-12nm)
• Si loss <1nm
• Etch target and uniformity >5 A
• Square SiGe etch front
Full release:
• SiGe etch ~25 nm (each
side, total ~25nm)
• Si loss <1nm
SiN
SiGe
Si
SiGe
Si
SiN
SiGe
Si
SiGe
Si
SiGe SiGe
SubstrateSubstrate
Step 1
SiN
Si
Si
Substrate
0
5
10
15
20
25
30
0 20 40 60 80 100 120
EA[n
m]
Etch gas[sccm]
Certas Si:SiGe selectivity
Poly Si
SiGe
The above data is on blanket films
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
7
COR SiGe:Si etch: etch time optimization
Incoming POST gas phase etch (recipe A; aggressive etch)
No process T1 T2 T3 (T1<<T3)
Summary for Si/SiGe stack:
• Selective SiGe: Si etch on imec wafer looks good (SiGe:Si >50:1)
• SiGe etch front looks VERY flat/square
• SiGe EA proportional etch time, without additional Si loss
• Partial SiGe etch uniformity ~3nm for Left /right side & top/bottom
layers (incoming tapper may contribute)
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
8
• Selective SiGe: Si etch on imec wafer looks good (SiGe:Si >50:1)
• SiGe etch front looks VERY flat/square
• SiGe EA proportional etch time, without additional Si loss
• Pressure (i.e etch gas partial pressure) is contributing to slower etch rate due to byproduct
formation depending on CD causing left-right and top-bottom non uniformity
COR SiGe:Si etch: pressure optimization
Incoming POST TEL gas phase etch (Recipe B; medium etch)
No process P1 P2 P3 P4 (P1<<P4)
Summary for Si/SiGe stack:
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
9
Incoming POST Etch
ET/
cyc No process Cavity etch Channel release
Ove
rla
y c
om
pa
ris
on
wit
h in
co
min
g
Til
ted
No
n-T
ilte
d
Ge%for SiGe = 20%
Summary:
• SiGe: Si etch selectivity > 50:1
• No SiN HM loss
• ER = 70nm/min
• SiGe etch front is square
Data based on alternate test structures
COR SiGe:Si etch: “cavity” and “channel release”
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
10
COR SiGe:Si etch: annealing effect
Incoming POST etch
No process Without anneal WITH anneal
No
n-T
ilte
d
Summary :
• Anneal affects the SiGe ER significantly
• Anneal also reduces the SiGe:Si selectivity at the SiGe-Si interface
o resulting in Si loss
o meniscus etch front
Ge%for SiGe = 20%1 Steam anneal 500C 2hrs
2 RTP 850C 1min
3 RTP 850C 5s
Data based on alternate test structures
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
11
Selective Si etch for Nanowire application
Partial release :
• Si etch =5-6 nm (each side, total
= 10-12nm)
• SiGe loss <1nm
• Etch target and uniformity >5 A
• Square SiGe etch front
Full release:
• Si etch ~25 nm (each
side, total ~25nm)
• SiGe loss <1nm
SiN
SiGe
Si
SiGe
Si
SiGe
Substrate
Step 1
SiN
SiGe
Si
SiGe
Si
SiGe
Substrate
SiN
SiGe
SiGe
SiGe
Substrate
0
5
10
15
20
25
30
0 20 40 60 80 100 120
EA[n
m]
Etch gas[sccm]
Certas Si:SiGe selectivity
Poly Si
SiGe
The above data is on blanket films
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
12
COR Si:SiGe etch: etch time optimization
Incoming POST Etch
ET/
cyc No process 90S 120S
Til
ted
No
n-T
ilte
d
Ge%for SiGe = 20%
Summary:
• Si: SiGe etch selectivity > 10:1
• No SiN HM loss
• ER = 7nm/min
• Si etch front is requires further
improvement
• Post etch surface is smooth
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
13
COR SiN spacer etch
SiN liner
SiN
SiGe
Si
SiGe
SiGe
Si
SiN liner
SiN
SiGe
Si
SiGe
SiGe
Si
Substrate Substrate
Selective SiN spacer etch:
• Required SiN:Si etch selectivity > 25:1 (no Si loss)
• Required SiN:SiGe etch selectivity > 25:1 (no SiGe loss)
Summary:
• SiN: SiGe/Si etch selectivity > 50:1
• No Si loss
• SiN still preserved on SiGe layers
SiN liner/spr dep SiN liner/spr etch
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
14
COR Selective dummy poly (a-Si) pull
SiN/SiOa-Si
SiN/SiO
Isotropic
gas etch
CESL/ILD0
SiGe
SiGe
SiGe
SiGe
Si
Si
Si
SiILD0
CESL
SiGe
SiGe
SiGe
SiGe
Si
Si
Si
Si
Dummy poly/OX
removalDummy poly removal :
• Extremely selective Si etch ~100-200nm
• No SiN loss or SiO2 loss
Device structure Test structure
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
15
Nanosheet Selective Etches: Updated
Fin recess Cavity etch Inner spacer formation Channel release
Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Step 9
Dummy poly removalTest structure
S. Kal / TEL / April 10-11th, 2018/ SPCC 2018
TEL Technology Center, America, LLC – imec
16
Conclusion
Dry plasma free etches are advantageous & crucial for Nanowire/CFET
integrations applications, due to:
– High etch selectivity, inherent from the etch mechanism
– No plasma damage
– Aspect ratio dependency
– Cyclic process (potential self limiting capability)
