Sequential Design

Part II

Output

A(t+1)=DA = AX + BX

B(t+1)=DB = AX Y = AX + BX

2-D State Table

Even Easier, State Diagrams:

Using State Diagrams

Using J-K Flip Flops

JA = B KA = BXJB = X KB = AX + AX

What about designing a state machine using J-K Flip Flops...

Giventhisstatetable

Recall

Sequential Circuit Design

• Obtain either the state diagram of the state table from the statement of the problem• If only a state diagram is available from set 1, obtain the state table

• Assign binary codes to the states

• Derive the flip-flop input equations from the next-state entries in the encoded state table

• Derive the output equations from the output entries in the state table

• Simplify the flip-flop input equations and output equations

• Draw the logic diagram with D flip-flops and combinational gates, as specified by the flip-flop input equations and output equations

Mealy Machine

Sta

te R

egis

ter

C1

x(t)

s(t+1)

s(t)z(t)

clk

init

present state

present input

nextstate

C2

Output based onstate and presentinput

Moore Machine

Sta

te R

egis

ter

C1

x(t)

s(t+1)

s(t)

z(t)

clk

init

present state

present input

nextstate

C2

Output base on state only

Example: A Sequence Recognizer

Let’s detect the sequence “1101” in a bit sequence

We need to “remember” what bits have passed by.

If the input is a ‘1’ then move to state B and the outputis a 0 (have not yet detected the “1101” sequence

If we are at state B (which meansthat we have read a ‘1’ immediatelybeforehand) and the next input is a ‘1’then we are making our way towardsa successful “1101” read so move to stateC.

Means first bitwas a ‘1’

The next bit we would like to read alongour “1101” sequence is a ‘0’. So ifwe read a 0, go to State D -- notice output isstill 0, we have not yet read the entire sequence.

After state D we have succeeded if a ‘1’is read so we will proceed and the outputwill now be ‘high’ or ‘1’

We don’t want to proceed to an E state, instead, if wehave detected “1101”, we have not only detected the bitsequence but we also are on our way to detecting another“1101” sequence. Consider “1101101”.

Two Sequences

We set the output‘high’ and go toState B.

We must also fill in the “unsuccessful” states, ones in whichwe have not read a “1101” sequence.

Begins with‘0’

Second bit is ‘0’

Third bit is a‘1’ which means wehave read a“111” seq.This puts uswaiting for a‘0’

A ‘0’ is the last bit (“1100”) back to the beginning.

Given the following:

Designing with D Flip-Flops

A(t + 1) = DA(A,B,X) = m(2,4,5,6)

B(t + 1) = DB(A,B,X) = m(1,3,5,6)

Y(A,B,X) = m(1,5)

Y(A,B,X) = m(1,5)

A(t + 1) = DA(A,B,X) = m(2,4,5,6)

B(t + 1) = DB(A,B,X) = m(1,3,5,6)

Using k-maps to reduce the equations:A(t + 1) = DA(A,B,X) = m(2,4,5,6)

B(t + 1) = DB(A,B,X) = m(1,3,5,6)

Y(A,B,X) = m(1,5)

00 01 11 100 11 1 1 1

DA = AB + BX

00 01 11 100 1 11 1 1

A

BX

A

BX

DB = AX + BX + ABX

00 01 11 100 11 1

ABX

Y = BX

Logic Diagram for Circuit with D Flip-Flops

Don’t cares: A Design Advantage

JA = BX JB = X

KA = BX KB = AX + AX

Significantly Reduces Logic Equations