SEQUENTIAL LOGIC TESTING AND VERIFICATION

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SEQUENTIAL LOGIC TESTING AND VERIFICATION

by

Abhijit Ghosh University of California/Berkeley

Srinivas Devadas Massachusetts Institute of Technology

A. Richard Newton University of California/Berkeley

~.

" Springer Science+Business Media, LLC

Library of Congress Cataloging-in-Publication Data

Ghosh, Abhijit, 1964-Sequentiallogic testing and verification Iby Abhijit Ghosh,

Srinivas Devadas, A Richard Newton. p. cm. -- (Kluwer international series in engineering and

computer science ; SECS 163) Includes bibliographical references and index. ISBN 978-1-4613-6622-5 ISBN 978-1-4615-3646-8 (eBook) DOI 10.1007/978-1-4615-3646-8 1. Logic circuits--Testing. 2. Logic design. 3. Computer-aided

design. 1. Devadas, Srinivas. II. Newton, A. Richard (Arthur Richard), 1951- . III. Title. IV. Series. TK7868.L6G47 1992 621.39'5--dc20 91-36094

CIP

Copyright © 1992 Springer Science+Business Media New York Originally published by Kluwer Academic Publishers,New York in 1992 Softcover reprint of the hardcover lst edition 1992

AII rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transIDÎ tted in any form ar by any means, mechanical, photo-copying, recording, ar otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC.

Printed on acid-free paper.

Contents

Table of Contents

List of Figures

List of Tables

Preface

Acknowledgements

1 Introduction 1.1 IC Design Systems . . . .. 1.2 Implementation Verification 1.3 Testing ......... . 1.4 Synthesis For Testability. 1.5 Outline ......... .

2 Sequential Test Generation 2.1 Preliminaries .............. . 2.2 Methods for Sequential Test Generation

2.2.1 Random Techniques ... 2.2.2 Deterministic Techniques .. . .

2.3 Test Generation Strategy ....... . 2.4 Cover Extraction and Combinational ATG . 2.5 Justification ...... . 2.6 Initialization of Circuits . . . . . . 2.7 State Differentiation ....... . 2.8 Identification of Redundant Faults

v

v

ix

Xl

xiii

XVII

1 2 5 6 9

10

11 ...... 12

21 22 23 27 32 35 39 42 45

2.9 Test Generation Results Using STEED. 2.10 Conclusions ............... .

3 Test Generation Using RTL Descriptions 3.1 Preliminaries . . . . . . . . . . . . . 3.2 Previous Work " . . . . . . . . . . 3.3 Global Strategy for Test Generation 3.4 State Justification .. 3.5 Indexed Backtracking ..... . 3.6 Conflict Resolution . . . . . . . .

3.6.1 Assembling the equations State Differentiation . . . . . . .

47 54

57 58 62 64 71 78 83 83 86 3.7

3.8 3.9

Test Generation Results Using ELEKTRA . . . . . . . .. 91 Conclusions . . . . . . . . . . . . . . 94

4 Sequential Synthesis for Testability 97 4.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . .. 98

4.1.1 Eliminating Sequential Redundancies ........ 106 4.2 Previous Work . . . . . . . . . . . . . . . . . . . . 107 4.3 Theoretical Results. . . . . . . . . . . . . . . . . . . 109

4.3.1 An Unconditional Testability Theorem. . . 109 4.3.2 Logic Partitioning ....

4.4 The Synthesis and Test Strategy 4.5 Detection of Invalid States. . . 4.6 Detection of Equivalent States 4.7 Experimental Results. 4.8 Conclusions...........

5 Verification of Sequential Circuits 5.1 Preliminaries ..... . 5.2 Previous Work . . . . . . . . . . . 5.3 Implicit STG Traversal. . . . . . .

5.3.1 Incompletely-specified machines .... 5.4 Implicit STG Enumeration .....

5.4.1 Traversal versus enumeration 5.5 Experimental Results. 5.6 Conclusions..............

vi

. .110

.114 .116 .118 .118

· 120

123 · 125 · 127 · 128

. ... 137

· 138 · 145 · 147 · 151

6 Symbolic FSM Traversal Methods 6.1 Preliminaries ........... .

6.2 6.3

6.4

6.5

6.6 6.7 6.8

6.1.1 Binary Decision Diagrams ..... . 6.1.2 Sets and Characteristic Functions .. Traversal by Recursive Range Computation Traversal based on Transition Relations 6.3.1 Iterative Squaring ..... 6.3.2 Detecting Equivalent States Depth-First Geometric Chaining 6.4.1 An Autonomous Counter 6.4.2 A Loop Counter ... A Mixed Traversal Algorithm . . 6.5.1 Introduction ...... . 6.5.2 k-Convergence and t-Periodicity 6.5.3 Traversing Cascaded Machines .. 6.5.4 Traversing Mutually Interacting Machines 6.5.5 Generalization to Multiple Submachines 6.5.6 Input-Selection-Based Traversal .. Implementation of Algorithm Experimental Results. Conclusions

7 Conclusions 7.1 Test Generation. 7.2 Synthesis for Testability 7.3 Verification ...... . 7.4 Directions for Future Work

Bibliography

Index

vii

153 · 155

. .. 155

· 158 .. 162

· 163

· 166 · 167 · 168

.. 169 .171 .174 .174 .174

· 177 .184

· 185 · 186 · 189 · 191

· 193

195 .195

· 196 · 197 .198

199

213

List of Figures

1.1 A typical synthesis pipeline ...... 4

2.1 A general synchronous sequential circuit 14 2.2 An example State Transition Graph .. 15

2.3 Circuit illustrating explicit and implicit enumeration 16

2.4 STG offaulty machine . . . . . . . . . . . . . . . . 18

2.5 The iterative array model of a sequential circuit. . 24

2.6 A machine illustrating problem with initialization. 27

2.7 Cover enumeration example . . . . . . . . . . . . . 34 2.8 ON and OFF-sets for NS lines of example machine 36

2.9 Justifying state A. . . . . . 37

2.10 Fault-free state justification . .. ...... 39

2.11 Justification algorithm . . . . . . . . . . . . . 40 2.12 ON and OFF-set for PO of example machine 44

3.1 An example RTL description 60

3.2 An example circuit . . . . . 65

3.3 An ALU and its model. . . 67

3.4 List of primitives used in test generation . 68 3.5 Main justification procedure . . . . . . . . 72 3.6 Procedure for justifying a state . . . . . . 73

3.7 Circuit to illustrate justification and differentiation 77

3.8 Circuit to illustrate indexed backtracking 79

3.9 Circuit illustrating conflict resolution. 3.10 Procedure for state differentiation.

4.1 An example STG . . . . . . . .. 4.2 The STG of an implemented machine

ix

84

88

99

. 100

4.3 Equivalent-SRF. 4.4 Invalid-SRF ... 4.5 Isomorph-SRF . 4.6 Complicated equivalent-SRF. . . 4.7 Two-level cover of the FSM ... 4.8 An implementation of a sequential circuit

4.9 Partitioned logic blocks

.102

.103

.104

. 105

.106 .. 111

.112

5.1 Product machine . . . . . 126

5.2 A cascade of two machines. . 129 5.3 STGs using explicit and implicit state enumeration . 130 5.4 Main verification procedure using traversal .. . 131 5.5 Procedure for traversing the STG of a machine . 132 5.6 The STG of a product machine . . . . . . . . . . 134 5.7 Parts of the STG enumerated during traversal. . 135 5.8 Final STG after traversal . . . . . . . . . . . . . . . . 137 5.9 ON and OFF-sets of the PO and NS lines of a machine . 139

5.10 State Transition Graph enumeration algorithm . . . . .. 140 5.11 Example to illustrate STG enumeration . . . . . . . . .. 142 5.12 Machines illustrating difference between traversal and enu-

meration. . . . . . . . . . . . . . . . . . . . 145

6.1 An example ROBDD . . . . . ........ 157 6.2 An example ROBDD with negative edges ...... 159 6.3 The generalized cofactor algorithm . . . 161 6.4 Recursion tree for image computation . 164 6.5 A 4-bit autonomous counter. . . . . . . 168 6.6 Obtaining the geometric functions .. . 169 6.7 Example traversal of a 4-bit autonomous counter . 171 6.8 A 4-bit loop counter with an input . . . . . 172 6.9 Example traversal of a 4-bit loop counter .... . 173 6.10 Example Finite State Machines . . . . . . . . . . . 175 6.11 The decomposition of a machine into two submachines .. 178

6.12 An example of a cascade . . . . . . . . . . . . . . . . ... 181 6.13 An example circuit . . . . . . . . . . . . . . . . . . . ... 186 6.14 Effect of mixed depth-first/breadth-first traversal . . . . . 188

x

List of Tables

2.1 Statistics for example circuits .... 48 2.2 Statistics of test pattern for circuits 48 2.3 Test generation results for circuits 49 2.4 Time profiles for example circuits . . 49 2.5 Time profiles for example circuits . . 50 2.6 Comparisons with STALLION and CONTEST ...... 51 2.7 N umber of clock cycles needed for testing ... . . . . . . 52 2.8 Test generation results for ISCAS sequential benchmarks. 53

3.1 Statistics for example circuits ... 92 3.2 Test generation results for circuits 92 3.3 Time profiles for example circuits . 93 3.4 Comparisons with STEED . . . 93 3.5 Clock cycles needed for testing 94

4.1 Statistics for example circuits .119 4.2 Test generation results for circuits · 120 4.3 Results of logic optimization. · 120

5.1 Statistics of examples · 147 5.2 Comparison of implicit and explicit state techniques .148 5.3 Verification of machines using traversal ........ .149 5.4 Verification of machines using enumeration-simulation · 149 5.5 Comparison of times for verification · 150

6.1 Traversal times for counters ..... · 191 6.2 Traversal times for circuits with datapaths and counters · 192 6.3 Traversal times for example Key ............. · 192

Xl

Preface In order to design and build computers that achieve and sustain

high performance, it is essential that reliability issues be considered care­fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte­gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes.

Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance.

In this book, we are concerned about the testing and verifica­tion of VLSI designs as well as the relationship of these problems to the design or synthesis process itself. If VLSI circuits were exclusively com­binational, the problems encountered would be those of combinational logic testing and verification. However, since VLSI circuits are generally sequential, i.e., they have memory elements that store state, the prob­lems encountered are those of sequential logic testing and verification. Since switching or combinational circuits are inherently easier to analyze and synthesize than more complex and powerful sequential circuits, it is intuitive that sequential test and verification problems are harder to solve than their combinational counterparts.

While it is easy to directly access the wires connecting to the pins of a packaged VLSI circuit, it is relatively difficult to directly access internal wires or the inputs/outputs of memory elements embedded in the circuit. This causes complications in sequential logic testing. A wide variety of approaches have been taken for solving the sequential testing

problem. One class of approaches modify the logic circuit with the goal of easing the task of test generation. This class of approaches have been collectively called design. for testability. Design for testability appears to be somewhat of a misnomer because such approaches apply post-design modifications to the optimized logic circuit in an effort to simplify the succeeding task of logic testing. A relatively new class of approaches uses testability as a cost function during logic synthesis 1 in an effort to produce fully and easily testable circuits. This class of approaches have been collectively termed synthesis for testability. A third class of approaches modify the manufacturing or packaging processes to enhance the observability of internal wires in the sequential circuit.

The logic testing part of this book is mainly concerned with the problems of test generation for optimized sequential designs with­out requiring the addition of extra circuitry in a post-design step, and the logic optimization problem of automatically synthesizing fully and easily testable sequential machines. Synthesis for testability approaches can be classified into two categories: synthesis approaches that impose constraints on the logic optimization such that the resulting circuit is restricted to the fully testable subset of the overall design space, or approaches that exploit the fundamental relationships between don't­cares and redundancy in combinational and sequential circuits. We will concentrate on the latter approach, which has the advantage that the addition of extra don't-care conditions during the logic optimization step can only improve the area/performance characteristics of the design as well as its testability. The main issue in the use of these approaches is the CPU time required for determination of don't-cares and subsequent logic optimization.

Research in synthesis for testability approaches has led to deeper insights into the problems of sequential logic synthesis and verification. The property of 100% testability signifies local area optimality for a cir­cuit because any redundant wire can be set to a logic 0 or 1, thereby reducing the area of the circuit. Relationships between circuit topology, area, performance, and testability are understood better in the context of logic optimization.

The problem of test generation can be viewed as the problem

lThe traditional cost functions in logic synthesis have been circuit area and performance.

xiv

of verifying the equivalence of two sequential designs, the first being the correct design and the second being the design with an injected fault. The problem of verifying the equivalence of two designs can be viewed as the problem of generating a test for the stuck-at-O fault on the output of the circuit produced by xOR,'ing the outputs of the two designs. The two designs are equivalent if and only if the fault is redundant. Thus, techniques for test generation are applicable to implementation verification and vice versa.

We have focused on three main themes in this book. We have tried to comprehensively explore the relationships between synthesis, test, and verification, in the context of sequential logic circuits.

We have described how the use of high-level information, for example, information available at the register-transfer level, can be used to great advantage in solving the problems encountered in manipulating sequential circuits.

Circuit representations and data structures cut across all facets of design such as synthesis, test, and verification. At the combinational or sequential circuit level, Boolean functions are continually manipulated in various ways. The search for more efficient representations of Boolean functions is ceaseless, mainly because discovering such representations can have a significant impact on synthesis, test, and verification prob­lems. In this book, we have described commonly-used representations for sequential circuits, and their advantages and disadvantages when applied to particular problems in synthesis, test, and verification.

Since we intended this book to be useful to CAD researchers, practitioners, and VLSI designers, we have included considerable detail in the description of the various algorithms. Most of the algorithms described have been implemented by researchers at MIT, U. C. Berkeley and elsewhere.

xv

Acknowledgments

Over the years, several people have helped to deepen our un­derstanding of automata theory, sequential logic testing, verification, synthesis, and VLSI CAD in general. We thank Jonathan Allen, Pranav Ashar, Robert Brayton, Gaetano Borriello, Raul Camposano, Tim Cheng, Aart De Geus, Giovanni De Micheli, Kurt Keutzer, Michael Lightner, Bill Lin, Tony Ma, Sharad Malik, Rick McGeer, Paul Penfield, Richard Rudell, Alberto Sangiovanni-Vincentelli, Fabio Somenzi, Herve Touati, Albert Wang, Jacob White, and Wayne Wolf.

Lastly, we thank our families and friends for their continual encouragement and support.

SEQUENTIAL LOGIC TESTING AND VERIFICATION