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Presented By:

Mohit Singh Choudhary

M.Tech. Communication and Signal Processing

Discipline of Electrical Engineering

IIT-Indore | EE 799 | M.Tech. Project Stage 1

Supervised By:

Dr. Santosh Kum

Assistant Profess

Discipline of Elec

Current Mode Logic Serializer and Des

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IIT-Indore |

Contents

Introduction

Motivation

Literature Survey

Previous Work

Proposed Work

Applications

Future Work

References

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Motivation

Parallel Interconnections• Large I/O pins

• More power consumed

•

Problem in meeting timing requirement• On Chip-area is more

Sender Receiver

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David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer

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Introduction

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SerDes ( Serializer and Deserializer)• Multiplexing bit data to bit of interconnect and at receiver demultiplexing

interconnect to bit data(< ).

SerializerDeserializer

/

David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer

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Introduction

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SerDes

Types of SerDes on the basis of design techniques.

Introduction

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Literature Survey

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1. Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low power SerDes transceiver for on-chip net

and Systems (ISCAS), 2011 IEEE International Symposium, pp.1419-1422, 15-18 May 2011.

2. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power self-t imed SerDes transceiver for mult

in Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp.1660-1663, 20-23 May 2012

  /2 /4

DETFF

DETFF

DETFF

DETFF

DETFF

DETFF

DETFF

VDD/2

"1"

VDD

0

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Literature Review

IIT-Indore |

Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes,

(SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014

a). Serializer b). Deserializer

Literature Survey

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Literature Review

IIT-Indore |

Tondo, D.F.; Lopez, R.R., "A low-power, high-speed CMOS/CML 16:1 serializer," in Micro-Nanoelectronics, Technology and A

 Argentine School of Micro-Nanoelectronics, Technology and Application, pp.81-86, 1-2 Oct. 2009

Serializer Architecture

Literature Survey

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Previous Work

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Serializer

9

/2/4

MUX

MUX

MUX

MUX

MUX

MUX

MUX

DFF DFF D

DFF DFF D

Deserializer

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Implementation

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Serializer and Deserializer are implemented in 65nm UMC technology

Previous Work

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Serializer Deserializer

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Implementation

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Results

Previous Work

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() (℃) −

1.08 125 11.49 / 15.36 /

1.2 27 12.67 / 16.64 /

ff 1.32 −45 13.75 / 16.96 /

 ℎ ℎ () ()

− [4] 65 16 18.1 − [2] 65 12.67 14.3

CMOS − CML[5] 45/65 10 50/106

. .

PVT Corners of various SerDes techniques

Comparison of various SerDes techniques

Mohit Singh Choudhary, Mahesh Kumawat, Pramod Kumar Bharti and Dr. S. K. Vishvakarna, “Power Optimized High Speed

CML SerDes Transceiver Design with Process Corner Variation”, IET Electronics Letter (Under Review)

l

d k

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Implementation

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Proposed Work

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Block Diagram of Serializer

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d k

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Implementation

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Proposed Work

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Block Diagram of Deserializer

I l i

P d W k

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Implementation

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Proposed Work

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Control Block

I l t ti

P d W k

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Implementation

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Proposed Work

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Serialized Output

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P d W k

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Implementation

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Proposed Work

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Deserialized Output

I l t ti

P d W k

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Implementation

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Results

Proposed Work

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 ℎ ℎ () () − [6] 180 3.9 2.44

− [5] 45/65 10 50/106

− [3] 65 12 15.5

− [4] 65 16 18.1

− [2] 65 12.92 14.3

. .

Comparison of various SerDes techniques

A li ti

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Applications

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Applications• Telecom wireless communication

• In video transmission (FlatLink)

• Transceiver Devices

• Telecom Switching Applications

• 8b/10b SerDes are used in Ethernet, Fiber optics, InfiniBand

Dave Lewis, “SerDes Architectures and Application”, National Semiconductor Corporation

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Future work

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Future work

IIT-Indore |

Dynamic CML• Reduced swing logic style that reduces both gate and interconnect power diss

• DyCML circuits combines the advantages of CML with those of dynamic logic f

achieve high performance at a low-voltage with low-power dissipation.

Equailizer• Equalization is the reversal of distortion incurred by a signal transmitted throu

a channel.

Encoding• Serial data can be encoded to 3-level, 8b/10b etc so that speed can be increas

1 . Allam, M.W.; Elmasry, M.I., "Dynamic current mode logic (DyCML): a new low-power high-performance logic style," in S

 Journal of , vol.36, no.3, pp.550-558, Mar 2001.

2. Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerD

Conference (SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014.

3. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power self-timed SerDes transceiver for mul

in Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp.1660-1663, 20-23 May 2012.

19

References

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References

IIT-Indore |

References[1]. David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Ed

Springer

[2]. Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asy

Wave-pipelined CML SerDes," in System-on-Chip Conference (SOCC), 2014 27th IEEEInternational , pp.5-10, 2-5 Sept. 2014

[3]. Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low pow

transceiver for on-chip networking," in Circuits and Systems (ISCAS), 2011 IEEE Interna

Symposium on , pp.1419-1422, 15-18 May 2011

[4]. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power

SerDes transceiver for multi-core communication," in Circuits and Systems (ISCAS), 20

International Symposium on, pp.1660-1663, 20-23 May 2012[5]. Tondo, D.F.; Lopez, R.R., "A low-power, high-speed CMOS/CML 16:1 serializer," in

Nanoelectronics, Technology and Applications, 2009. EAMTA 2009. Argentine School o

Nanoelectronics, Technology and Application, pp.81-86, 1-2 Oct. 2009

[6]. Bui Chinh Hien; Seok-Man Kim; Kyoungrok Cho, "Design of a wave-pipelined seria

deserializer with an asynchronous protocol for high speed interfaces," in Quality Elect

Design (ASQED), 2012 4th Asia Symposium on , vol., no., pp.265-268, 10-11 July 2012

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Thanks