Accepted Manuscript

Sharp switching behaviour in graphene nanoribbon p-n junction

Ahmed M.M. Hammam, Marek E. Schmidt, Manoharan Muruganathan, Hiroshi Mizuta

PII: S0008-6223(17)30563-8

DOI: 10.1016/j.carbon.2017.05.097

Reference: CARBON 12073

To appear in: Carbon

Received Date: 27 February 2017

Revised Date: 15 May 2017

Accepted Date: 30 May 2017

Please cite this article as: A.M.M. Hammam, M.E. Schmidt, M. Muruganathan, H. Mizuta,Sharp switching behaviour in graphene nanoribbon p-n junction, Carbon (2017), doi: 10.1016/j.carbon.2017.05.097.

This is a PDF file of an unedited manuscript that has been accepted for publication. As a service toour customers we are providing this early version of the manuscript. The manuscript will undergocopyediting, typesetting, and review of the resulting proof before it is published in its final form. Pleasenote that during the production process errors may be discovered which could affect the content, and alllegal disclaimers that apply to the journal pertain.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

1

Sharp switching behavior in graphene

nanoribbonp-njunction

Ahmed M. M. Hammam,a,b,* Marek E. Schmidt,a Manoharan Muruganathana and Hiroshi

Mizutaa

a School of Materials Science, Japan Advanced Institute of Science and Technology, 1-

1Asahidai, Nomi 923-1292, Japan

b Physics Department, Faculty of Science, Minia University, Main Road - Shalaby Land, Minia

11432, Egypt

Abstract 1

The experimental study of interband quantum mechanical tunneling in graphene nanoribbons

is a major step to realizing graphene tunneling-based field effect transistors (TFET). Here, we

report the sharp switching behavior observed in an electrostatically controlled graphene

nanoribbon p-n junction in pn and np biasing. We demonstrate current modulation with a slope

of 42 mV/dec over five order of magnitude in drain current at 5 K when the device is switched

from nn to np configuration. This slope is unaffected by temperature up to 50 K. The suppression

of carrier transmission in the OFF state is attributed to the finite bandgap of the ~15 nm wide

graphene nanoribbon channel. We show that the reported device characteristics can be explained

by band-to-band tunneling through the junction. This work is expected to offer valuable insight

into BTBT in GNRs and be a valuable contribution towards competitive graphene TFETs.

*Corresponding author. Tel: +81 761-51-1573. E-mail: a_hammam@jaist.ac.jp (Ahmed M.

M. Hammam)

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

2

Introduction 2

Complementary metal oxide semiconductor (CMOS) devices have continuously been

downscaled for decades, however, the stand-by power governed by the leakage current at their

OFF state is now exceeding the dynamic power at the ON state[1]. In order to overcome this

issue, various types of abrupt switches are currently examined, which are expected to realize a

subthreshold slope (SS) smaller than the theoretical limit of 60 mV/decade at room temperature

for Metal-oxide-semiconductor field effect transistors (MOSFET) and a lower threshold voltage,

leading to a remarkable reduction of the leakage floor. In this direction, tunnel field effect

transistors (TFETs) are currently under serious study as one of the promising candidates for

beyond-Moore electronics [2]. It is worth to mention that a conventional semiconductor TFET is

formed by a fixed p-doped source and n-doped drain region, where the gate is used to tune the

channel potential to realize ON and OFF states. In the ON-state, a p-n junction is formed

between source and channel. Over the past decade, various TFETs based on both group IV and

group III-V semiconductors have been studied. However, these TFETs commonly suffer from

seriously low ON-state current due to the large band gap of the employed semiconductors [2,3].

In contrast, TFET designs based on graphene, which features inherently zero band gap and

massless charge carriers, are expected to achieve a higher tunneling current at the ON-state.

Moreover, superior gate controllability due to the atomically thin two-dimensional (2D) nature of

graphene is expected. Unlike conventional semiconductors, in graphene, doping level and type

can be controlled electrostatically by a perpendicular electric field. Thus, the device performance

can be optimized by modulating the electrostatic gates. Despite its exceptional electrical

properties, graphene with its zero bandgap is handicapped in the field of digital electronics where

a finite bandgap is an essential requirement to control the carrier transport through a device.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

3

However, patterning 2D graphene sheets into very narrow ribbons has been reported to introduce

an energy gap[4–9]. Therefore, Graphene Nano-Ribbons (GNRs) have a significant potential to

enable graphene to be used in digital electronics.

The large number of theoretical studies about graphene TFETs[10–13]currently lack extensive

experimental verification to help identify the most crucial aspects and study the feasibility and

challenges. To the best of our knowledge, experimental demonstration of such kind of abrupt

switches based on band-to-band tunneling in GNRs have not yet been reported, although there

has been related research on graphene p-n junctions that can be divided into two categories:

Based on graphene (i) with energy gap, and (ii) without. In case of zero bandgap graphene p-n

junctions, carrier transport demonstrated a substantial evidence of the existence of the so-called

Klein tunneling (perfect transmission of the electrons in graphene with normal incidence onto a

potential barrier) phenomenon. Therefore it has been concluded that charge carriers cannot be

confined electrostatically in zero bandgap graphene p-n junctions[14–23].

On the other hand, when the graphene in the junction region has a finite energy gap,

suppression of Klein tunneling is theoretically reported [24,25]. Additionally, two important

considerations emerge in GNRs patterned by plasma etching techniques, namely, quantum

confinement (energy gap opening) and the effect of edge states that arises from unavoidable line

edge roughness (LER)[5,6,14,26–29]. Due to this edge disorder, the carrier transport in

semiconducting GNRs is dominated by the Coulomb blockade of multiple quantum dots[5,14]

and quantum confinement[30]. The former was observed by Liu et al.[14] who studied a p-n

junction in 30 nm wide GNR using one top gate and a global back gate for electrostatic

modulation. Müller et al.[31] fabricated a p-i-n junction using 30 nm wide GNR using buried

triple gates and attributed the electronic transport through the junction to band-to-band tunneling

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

4

(BTBT). However, electrical characterization at only one temperature was reported in their study

that focuses on the fabrication process, and the BTBT was not explained in detail.

In this paper, we present a study of the carrier transport through a low biased GNR p-n

junction in a wide range of temperatures extending from 5 to 300 K. Two individual top gates

with spatial separation of ~ 40 nm are used to define the PN junction electrostatically along the

GNR with a width of ~ 15 nm. By individually modulating the potential of the top gates, four

distinct configurations corresponding to nn, pp, pn and np are observed. Carrier transport shows

a remarkable step transition during switching the device configuration from nn to pn (forward

direction) or np (reverse direction), respectively, at lower temperature. Ion/Ioff ratios of 104 to 105

are realized at low temperature. Our detailed analysis shows that, although concurrent

mechanisms influencing the transport through the device, the sharp switching behavior can be

explained by considering BTBT through the p-n junction. The asymmetry between np and pn

biasing is explained based on 3D device simulations that show the effect of the top gate

alignment.

Experimental 3

3.1 Device Fabrication

The schematic of our device is shown in Fig. 1(a), and a scanning electron micrograph in 1(b). It

consists of a narrow GNR at the centre of the channel for p-n junction formation, with wider

graphene acting as the source and drain contacts. Here, a commercial chemical vapour deposition

(CVD) grown single-layer graphene is transferred on top of a SiO2 (90nm)/Si substrate. To

decrease the amount of PMMA residues after the transfer process that can degrade the carrier

mobility [32–34], we put the sample in hot Acetone for 30 min, followed by annealing in

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

5

forming gas for 3hrs at 250°C. Electron beam lithography (EBL) followed by e-beam

evaporation of 5/35 nm of Cr/Au and the lift-off technique are used to fabricate source drain

electrodes. High-resolution, negative tone resist, hydrogen silsesquioxane (HSQ), which is

converted into SiO2 after e-beam exposure, is used with a thickness of 35 nm to form the gate

dielectric and, at the same time, a hard mask. The narrow GNR is achieved by the reactive ion

etching (RIE) technique. It is worth mentioning that we did a second annealing (identical

conditions) just before coating the sample with HSQ to decrease the PMMA residues from the

previous fabrication steps. A part of the ~ 22 nm wide and 1µm long continuous HSQ hard mask

is shown in the inset of Fig. 1(b). Before the top gate fabrication, an additional passivation layer

of SiO2 was deposited by electron beam evaporation (10 nm), effectively reducing the gate-

channel leakage. Finally, a high-resolution positive tone resists (SML-100) was used to fabricate

the two Cr/Au (2/10 nm) top gates with spatial separation of 40 nm by the previously used EBL

lift-off technique. In the fabricated p-n junction device shown in Fig. 1 (b) the misalignment

between the top gate and the GNR of ∆X ≈ 325 nm is caused by the accuracy limit of the

lithography alignment process.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

6

Fig. 1 (a) Schematic illustration of our GNR p-n junction device. (b) Scanning electron

micrograph of the measured device with false colouring for better visibility. Insets show the

separation of ~ 40 nm between the top gates above the GNR, and the HSQ etching mask of ~22

nm width. ∆X is the misalignment of the top gates in respect to the GNR. (c) Ambipolar

characteristics at 300 K for Vd = 5 mV measured for individual gates. (d) Arrhenius plot used to

extract the energy gap Eg = 44 meV.

3.2 Characterization

A semiconductor device analyser (Agilent–B1500A) was used for all electrical measurements

performed under vacuum (~ 10-4 Pa) in a variable temperature helium closed cycle cryocooler

prober system. The base temperature of the system is T ≈ 4.8 K. To confirm the functionality of

each gate and the performance of the GNR, the drain current was measured as a function of the

top and back gate voltages. The room temperature measurements shown in Fig. 1 (c) demonstrate

the individual gate potential tunability that is important to achieve electrostatically controlled

individual p and n regions in the GNR device. In all gate modulations, it was observed that the

charge neutrality point (CNP) is located close to 0 V, demonstrating the nearly intrinsic

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

7

characteristics of the GNR. This characteristic is important as it minimizes the required gate

voltage offsets and offers symmetric tuning.

Results 4

As mentioned earlier, the width of the HSQ hard mask is ≈ 22 nm as shown in Fig. 1 (b),

however, the actual width of the patterned GNR is narrower due to the isotropic etching

component of plasma RIE [4,28,35]. From the linear high-temperature region of the Arrhenius

plot shown in Fig. 1 (d) , an energy gap (Eg) of ~ 44 meV was extracted for the fabricated GNR.

Using the empirical model W / ( is the reduced Plank constant, W is the GNR

width and = 106 m/s is the Fermi velocity)[8], the effective GNR width is thus estimated to be

~ 15 nm.

The four possible configurations of the p-n junction (nn, pp, pn, np) are realized by

modulating the top gates independently while applying a drain bias Vd. For this, one of the top

gates is swept from -5V to +5V while the second gate is stepped in the same voltage range (-5V

to +5V). Note that, throughout this paper, the doping configuration is indicated by two letters

(such as np), where the first letter denotes the doping below Tg1 (positive voltage for n-doping,

negative voltage for p-doping), and the second letter denotes the doping below Tg2. Fig. 2 shows

the characteristic contour plot of drain current (Id) as a function of the two top gate voltages at 10

K (plots for other temperatures can be found in the supplementary information). Vd is fixed at 3

mV for all measurements at 25 K and above, and 12 mV below due to the high current

suppression at lower temperatures. As can be seen in Fig. 2, the low current region due to Tg2

modulation (transport gap) is wider than the low current region due to Tg1 modulation. This

difference is ascribed to the slight misalignment between the two top gates and the GNR in the

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

8

fabricated device as shown in Fig. 1(b). Tg1 covers a larger part of the wide graphene contact

region.

Fig. 2 Contour plot of drain current as function of the top gate voltages at T = 10 K. Drain

voltage Vd is 12 mV. The clearly defined doping regions induced by the electrostatically doping

are indicated by np, nn, pn, and pp, respectively. The three dashed lines indicate the location of

the profiles in Fig. 3(b-d).

The drain current (Id) at 10 K is shown for different gating configurations in Fig. 3. When

using the global back gate (Fig. 3 (a)), a symmetric modulation is observed with some random

oscillation around the CNP at Vg = -0.5 V. The symmetric modulation is consistent with the 300

K measurement shown in Fig. 1(c). When modulating by the synchronized top gates (along the

black dotted line in Fig. 2), the symmetric characteristics are observed, as well (Fig. 3 (b)),

however, some differences exist compared to the back gate modulation. Firstly, the ON current

(VTg = +/- 5 V) is higher. As the dielectric layer between the top gates and the graphene is

significantly thinner than between the substrate and graphene, the modulation at a given voltage

is stronger with a higher doping level. The higher OFF current is due to the charge neutrality

points (CNP) having a slight offset for the two top gates (see Fig.1 (c)), and the device cannot be

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

9

effectively turned off for synchronized top gate voltages (i.e. while the GNR underneath one gate

is completely turned off, the GNR under the other gate is still slightly ON). In contrast to these

two cases, when fixing one of the top gates and sweeping the other one, a remarkable step

change in the drain current is observed. For fixed VTg1 = 4.9 V (Fig. 3(c), corresponding to np

biasing), the step change with a rate of ~42 mV/dec over a range five order of magnitude in drain

current (5x105) is observed at VTg2 ≈ -1 V. The OFF state current is at least one order of

magnitude lower than for the back gate modulated current. In case of a fixed VTg2 = 4.9 V (Fig.

3(d), pn biasing), the rate of the step change at VTg1 ≈ -0.8 V is ~32 mV/dec but only over a

range of four order of magnitude in drain current (~1.3x104). Furthermore, the current is only

very slightly affected by the VTg1 outside of the suppression region.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

10

Fig. 3 Drain current as a function of gate voltage at T = 10K and Vd = 10 mV: (a) Back gate

voltage sweep. (b) Simultaneous Tg1 and Tg2 sweep. The GNR is modulated from nn

configuration to pp configuration. (c) Tg2 sweep at VTg1 = 4.9 V. The device is switched from nn

configuration to pn configuration by sweeping VTg2 from 5 V to -5 V (forward biasing). Inset

shows the transition region with sharp slope of 42 mV/decade over five orders of magnitude. (d)

VTg1 sweep at VTg2 = 4.9 V (reverse biasing) showing similar characteristics with 32 mV/decade

in the sharp switching region over four orders of magnitude.

Similar characteristics are observed at 100 K and slightly changed bias conditions, as well

(compare Fig. 4), however, two observations are made that require further elaboration. Firstly,

the slope of the abrupt current change decreases with increasing temperature. Secondly, there is a

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

11

clear difference between np and pn biasing, both in terms of the modulated gate voltage, but also

in terms of the fixed gate voltage. For the np biasing (Fig. 4(a)), the current is unaffected by VTg1

(from 2 to 3.9 V). In clear contrast, the current is strongly affected by VTg2 in the pn biasing, and

shows a constant current beyond the sharp switching (Fig. 4(b)). At 10 K this effect is observable

as well for the np biasing (see supplementary information) but strong current fluctuation and the

wide transport gap due to Tg2 masks this effect for the pn biasing. Although the source-drain

biasing direction is reversed in respect to the doping configuration for these two cases, such an

asymmetry is not expected and will be discussed in the next section.

Fig. 4 Device characteristics at 100 K for np and pn biasing conditions. (a) Drain current vs VTg2

(Vd = 3 mV and variable VTg1). (b) Drain current vs VTg1 (Vd = 3 mV and variable VTg2).

Discussion 5

5.1 Asymmetry of forward/reverse biasing

To understand the origin of the observed asymmetry between np and pn biasing, we have

performed 3D technology computer-aided design (TCAD) simulations. We have mentioned

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

12

earlier that the top gates have a misalignment of ∆X ≈ 325 nm as shown in Fig. 1(b). Thus, along

the GNR channel from source to drain, there are two areas not fully modulated by the top gates,

and a non-uniform modulation within the top gate regions are expected. In Fig. 5(a), the

perspective representation of the used 3D model is shown that reproduces the fabricated device.

All dielectrics (SiO2) are hidden for better visibility. Here we use Silvaco Atlas device

simulation framework [36], and the graphene is modelled as a 5 nm thin polysilicon layer with 1

µOhm.cm resistivity, dielectric relative permittivity of 3, and a balanced donor and acceptor

doping of 1019 cm-3 in order to reproduce the centered Fermi level of unmodulated graphene. The

energy gap of the narrow part is set to 44 meV, while this value is 0 meV for the remaining

graphene. The energy of the conduction and valence band of the graphene channel is affected by

the potential distribution between the top gates and the graphene. For the simulation, Vd is 10

mV. Fig. 5 (b) is the cross section through the simulated 3D model (cut parallel to yz plane

through the centre of the GNR at x=0) showing the potential distribution in the gate dielectric

with VTg1 -1 V and VTg2 4 V. In the p-n junction region, a continuous transition from negative to

positive potential is observed without intrinsic region. The potential gradient is directly affected

by the geometry (i.e. the top gate separation and the thickness of the HSQ and SiO2 layers).

Furthermore, in the regions inside of Tg1 and Tg2, it is clearly visible that the electrostatic

modulation of the GNR is reduced, but not eliminated. The band energies along the graphene

channel (x = 0 nm) are extracted as shown in Fig. 5(c) for the np, and in Fig. 5(d) for the pn

biasing condition for different variable gate voltages (the fixed gate is at 4 V).

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

13

Fig. 5 TCAD simulation results. (a) Perspective view of 3D model representation of device

shown in Figure 1b used for Silvaco TCAD 3D simulation. All SiO2 elements are hidden for

better visibility. (b) Cut plane parallel to the yz plane through the center of the GNR (x=0)

showing potential distribution induced by VTg1 = -1 V, VTg2 = 4 V and Id = 10 mV. The potential

varies with the position below the top gates due to the partially unmodulated GNR. (c+d)

Extracted band structure at center of GNR in the pn biasing configuration (VTg2 = 4 V) and np

biasing (VTg1 = 4 V). When sweeping the variable gate from 4 V to -4 V, initially a potential

barrier is present. Then, when the valence band below the variable gate is lifted above the

conduction band of the fixed gate, a relatively narrow tunnelling barrier is formed that allows the

rapid increase of current. The bias window is indicated by dashed lines. (e) Close-up of the PN

junction, highlighting the formation of the tunnelling barrier with length less than 40 nm.

For the nn configuration (4/4 V), a continuous doping along the channel is realized that allows

the high current. However, two potential bumps caused by the unmodulated GNR region are

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

14

present. As VTg1 is reduced to 0.4 V, a wide potential barrier is formed in the Tg1 region,

effectively blocking the current through the channel (compare Fig. 3(c)). At this point, the

thermally activated leakage current over the potential barrier is governing the Ioff level. Note that,

due to the edge roughness and the resulting potential variation in the band structure, multiple

quantum dot effect (Coulomb oscillations) is observed for all curves in Fig. 3 [27,37], and will

be discussed in more details later. Then, as VTg1 is further reduced to -0.8 V, the potential barrier

is further heightened and a decrease of current would be expected. However, as the valence band

edge on the Tg1-side of the junction is shifted above the energy of the conduction band edge on

the Tg2-side, a narrow barrier with the width WT is formed at the p-n junction inside the bias

window that is defined as the energy difference between the Fermi level in the source and drain

(EFS - EFD). This is highlighted in Fig. 5(e) where the junction region is shown for different pn

biasing conditions. For such a band structure with the narrow spacing (~ 40 nm) between Tg1 and

Tg2, the significant band-to-band tunnelling (BTBT) current through various mechanisms, such

as thermally assisted tunneling and hoping through trap states is expected [38]. The sharp

switching apparent in Fig. 3(c) and (d) occurs immediately after the current minimum is

observed. The 3D TCAD simulation results show that the valence band is shifted above the

conduction band at around 0.4 V of the variable gate, however, the current minima in Fig. 3(c)

and (d) are at gate voltages of ~ -1 V and -0.8 V, respectively. This, in fact, is consistent with the

simulation where the tunnelling window, which is defined as the energy difference between the

valence band edge in the p(n)-doped region and the conduction band edge in the n(p)-doped

region, is shifted into the bias window at those voltages.

When the gate voltages are further reduced, the previously described effect continues, namely

the potential barrier becomes higher and the tunnelling region is increased. The width WT of the

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

15

tunnel barrier is also decreased, but this change is relatively limited. Nevertheless, the current

level reached is comparable to the nn configuration in both cases, however, current saturation is

observed for pn biasing but not for np biasing. The 3D TCAD simulation shows that the

tunnelling barrier is identical for both configuration, thus a different reason has to exist.

The small potential bumps inside of the top gates show a clear, but weaker, modulation

compared to the fully covered areas (see red and blue dots in Fig. 5(c) and (d)). These bumps are

very similar, however, due to the source-drain biasing condition, the bump band energies in the

Tg1 region are up-shifted compared to Tg2. To help understand the consequences of this, the

different effects governing the transport of a charge carrier from source to drain in the pn

configuration will be described first. Most of the carrier at low temperature (depending on the

thermal distribution in the source region, charge carriers can overcome the source/Tg1 potential

bump and contribute to the thermally activated leakage current) travel along the p-doped channel

until they encounter the potential bump within Tg1. This bump will pose some resistance to the

carriers, but due to the thermal activation (we did not measure the device below 5 K) and edge-

roughness mediated transport [6] the barrier can be overcome. The charge carrier again enters the

p-doped region until it tunnels into the conduction band through the tunnelling barrier. To reach

the drain electrode, only the potential bump in the Tg2 region (which is fixed in this

configuration) is of importance. The charge carrier transport in the np configuration is very

similar. However, in the latter case, the fixed bump in the n-type region is in Tg1, and the BTBT

is from conduction to valence band.

The curves in Fig. 4 for 100 K show that, in the np configuration, the current level is

unaffected by VTg1 and keeps increasing after the sharp switching. In contrast, for the pn

configuration, the current level after the sharp switching is approximately constant, and strongly

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

16

depends on VTg2. Based on the device design and 3D TCAD results, such a characteristic is only

possible if the transport from source to drain is governed by the Tg2 region, namely, the transport

through the Tg2 region has the highest resistance and this resistance changes with VTg2. The

potential bump inside Tg2 has a lower energy at a given voltage, thus, for p-doping, the potential

barrier is higher and thermal activation is required to overcome it. These 3D TCAD suggest that

BTBT occurs at the p-n junction, however, the saturation current after the sharp switching

behaviour is dominated by the potential bump and density of states (DOS) below Tg2 for pn and

np biasing configurations.

5.2 Origin of sharp switching

The sharp switching was observed in the np and pn biasing condition at low temperature (Fig.

3(c) and (d)), when one of the gates is biased so that the valence band edge in the variable gate

region is lifted into the bias window and at the same time above the conduction band edge in the

fixed gate region. This is evident from the 3D TCAD simulation results in the previous section.

We can thus sketch the simplified band structure of the p-n junction as shown in Fig. 6(a). In the

uniformly nn-doped state, a large drift current is enabled. As the energy of the band edges in the

Tg2 region are shifted up, the drift current is reduced and a thermally activated leakage current

dominates the transport. Finally, as the band overlap occurs, the tunnelling width WT is abruptly

reduced. As the tunnelling window is formed in the bias window (between EFD and EFS), the

large number of available charge carriers enables the increase of the drain current over five

orders of magnitude with the sharp slope. As the tunnelling energy window is further increased

(VTg2 is further decreased), the sharp switching saturates because the transport through the

remaining parts of the channel limit the allowed current.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

17

5.3 Quantum confinement and Coulomb oscillation

The Id/VTg data at low temperature shows significant peaks of comparable amplitude to the

sharp switching highlighted in Fig. (c) and (d). Due to the EBL-RIE GNR formation method

used in this work, we have to consider the effect of edge disorder that is unavoidable issue of it.

The carrier transport in GNR based devices is mainly affected by the multiple quantum dots,

Anderson localized states, and the disorder potential [5,6,14,26–28]. For short GNRs, the

multiple quantum dots effect has a stronger effect compared to the Anderson localized states.

The effect of multiple quantum dots is illustrated in Fig. 6(b), where the band structure of a GNR

with edge disorder is schematically sketched. Varying doping levels, (location of bands in

respect to the Fermi level) can cause the formation of isolated quantum dots along the GNR (Fig.

6 (b1)). Charge carriers have to overcome these potential barriers between the dots, greatly

influencing the current. The shape and number of the dots can change significantly with the

slight change of the Fermi level (such as change of gate voltage, compare Fig. 6(b2)), forming

continuous charge puddles. At higher doping levels (higher gate voltages), this effect is strongly

suppressed and the current at higher doping levels in Fig. 3 is smooth. Also, the effect of the

quantum confinement is reduced by thermal smearing, which is apparent when comparing Fig. 3

and Fig. 4. The current spikes in the low-current region sometimes exceed two orders of

magnitude, and thus we want to discuss if the reported sharp switching over five order or

magnitude might in fact be due to coincidental oscillation. For this purpose, the Id/Vd curves for

the p-n junction device at different top gate biasing conditions and temperatures is plotted in Fig.

6(c), showing a near-ohmic behaviour for the np configuration. For the intrinsic state (Tg1 and

Tg2 floating), the current level is more than two orders of magnitude lower and exhibit clear non-

linearity (see inset of Fig. 6(c)) which is evidence of a clear Coulomb blockade effect.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

18

Fig. 6 (a) Proposed band structure model of p-n junction. (a1) In the nn configuration (VTg2 = 4

V), continuous doping leads to high current. (a2) In the ni configuration, only low thermally

activated leakage current is observed together with coulomb oscillation. (a3) When the valence

band below Tg2 crosses above the conduction band below Tg1, band-to-band tunnelling leads to

sharp increase of current. (b) Schematic illustration of quantum dot formation in GNR with edge

irregularities. The size of charge puddles varies strongly at low doping levels. (c) Id/Vd at various

temperatures and doping configurations. In the intrinsic state, clear Coulomb blockade is

observed. For the np configuration, near-ohmic characteristics indicate existence of band-to-band

transport mechanism.

5.4 Temperature dependence of switching slope

The switching slope as function of temperature for the forward biasing condition has been

extracted for various temperatures and is shown in Fig. 7(a). A remarkable independence on

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

19

temperature is observed up to 25 K. It is worth to mention here that the SS degradation by

temperature is also observed in conventional semiconductor,[39–41] however, it follows a

continuous increase governed by the thermal activation energy, and the remarkable temperature

independence is not expected. By considering the BTBT phenomena, the transmission

probability can be expressed by the WKB approximation [2]:

, where WT is the screening tunnelling length, m* is the effective mass, Eg is the energy gap,

∆Ф is the tunnelling window (i.e. the energy difference between the valence and conduction

band right and left of the tunnelling barrier EVD-ECS) and ħ is the reduced Planck constant.

Hence, the SS becomes[42]:

As can be seen from Eq. (2), the SS modelled by the WKB approximation does not depend on

temperature. By using the experimentally determined SS at low temperature, the energy gap of

44 meV and m* = 0.05 m0 [9], we calculate a tunnelling length of 8.3 nm. This value is lower

than the estimated 20 nm from the 3D TCAD simulation results shown in Fig. 5(e). This

disagreement between Eq. (2) and the 3D TCAD simulation might be due to the LER. If a

variation of the tunnelling length occurs at the junction between the p-side and n-side, the

effective tunnelling length at the junction is reduced [43]. For temperatures above 25 K, the

experimental data shows a noticeable deviation. It should be noted that the SS due to BTBT

≈ − √∗ !"ΔФ% &'

(( ≈ )*'+ !"ΔФ%√∗ , &

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

20

cannot be observed directly, instead, it is derived from the transport behaviour of the complete

device including irregularities, source/drain leads, OFF-state current and thermally activated

leakage current. The suppression of the latter is greatly reduced at higher temperature [7,11,44]

when the thermal energy becomes comparable to the energy gap. In fact, in our p-n junction we

observe a rapid increase of the off state current by temperature. Thus, when a different effect

than the increase in tunnelling current becomes more dominant, or the change of current due to

BTBT is relatively small compared to other leakage paths, the SS degradation is predicted and

the measured characteristics do not follow the model.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

21

Fig. 7 p-n (a) Temperature dependence of switching slope and modelling results. A good

agreement is found for WT = 8.3 nm. (b+c) Device resistance as function of temperature in (b) np

configuration (VTg1 = 4 V, VTg2 = -4 V) and (c) nn configuration (VTg1 = VTg2 = 4 V) showing

distinctively different characteristics. (d) Sketch schematically illustrating influence of device

temperature on current contributions. At higher temperature, the thermally activated leakage

contribution increases (above ECD).

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

22

The device resistance as function of temperature is shown in Fig. 7(b) for the np and in Fig.

7(c) for the nn configuration. The drain voltage is 12 mV (3 mV) at low (high) temperature as

mentioned earlier. The resistance increases in both cases at low temperature, which is explained

by the multiple quantum dots effect. For the nn configuration, the curve follows the general trend

of semiconductors, where the increase of temperature is associated with an increase of the charge

carrier concentration, which leads to a decrease in the resistance before phonon scattering leads

to an increase of resistance at increasing temperature. In stark contrast, the resistance in the np

configuration has a minimum at around 100 K, before increasing significantly with temperature.

The origin of this increase is illustrated in Fig. 7(d), where the band structure of the junction in

the np configuration is schematically sketched together with the source Fermi-Dirac distribution

at low and high temperature, respectively. At low temperature, a larger number of carriers is

available in the BTBT energy window, and the thermally activated leakage current is suppressed

(due to the energy gap and low concentration above ECD). With increasing temperature, however,

the FD distribution smears out in a way that the total charge contribution for transport is reduced

(suppression due to energy gap below Tg2 is enhanced). The FD distribution of the carrier within

the bias window changes considerably with temperature. Therefore, the tunnelling current

decreases by increasing the temperature [7]. Finally, above 250 K, the device resistance

decreases again (see Fig. 7(b)). This is due to the enhanced thermally activated leakage current.

Note that the absolute resistance at 300 K of ~300 kΩ in the np configuration is still considerably

higher than in the nn configuration (~160 kΩ), signifying the presence of the potential barrier.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

23

Conclusion 6

The sharp switching behaviour observed in a graphene p-n junction with a finite bandgap of

~44 meV shows good agreement with a device model based on band-to-band tunnelling. When

the channel is modulated continuously by the back or synchronized top gates, the sharp

switching is not observed due to the lack of BTBT. The asymmetry between np and pn

configuration is explained as a consequence of the top gate misalignment. Device simulations

shows that potential bumps are formed in the unmodulated channel regions, which affect the bias

window differently. The current noise in the OFF-state is caused by the edge roughness induced

by the reactive ion etching technique to pattern the GNR. Finally, we show the temperature

dependence of the switching slope and the device resistance, highlighting that the observed

device characteristics can only be explained by BTBT.

Acknowledgements 7

This work is supported by the Center Of Innovation (COI) program of the Japan Science

Technology Agency. The authors are very grateful to Shunri Oda and Michiharu Tabe for the

fruitful technical discussions. Ahmed M. M. Hammam acknowledges the financial support from

the Egyptian Ministry of Higher Education (Culture Affairs and Missions Sector).

References 8

[1] R. Puri, L. Stok, S. Bhattacharya, Keeping hot chips cool, in: Proc. 42nd Des. Autom. Conf.

2005, 2005: pp. 285–288. doi:10.1145/1065579.1065653.

[2] A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic

switches, Nature. 479 (2011) 329–337. doi:10.1038/nature10679.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

24

[3] H. Lu, A. Seabaugh, Tunnel Field-Effect Transistors: State-of-the-Art, IEEE J. Electron

Devices Soc. 2 (2014) 44–49. doi:10.1109/JEDS.2014.2326622.

[4] M.Y. Han, B. Özyilmaz, Y. Zhang, P. Kim, Energy Band-Gap Engineering of Graphene

Nanoribbons, Phys. Rev. Lett. 98 (2007) 206805. doi:10.1103/PhysRevLett.98.206805.

[5] F. Sols, F. Guinea, A.H.C. Neto, Coulomb Blockade in Graphene Nanoribbons, Phys. Rev.

Lett. 99 (2007) 166803. doi:10.1103/PhysRevLett.99.166803.

[6] M. Evaldsson, I.V. Zozoulenko, H. Xu, T. Heinzel, Edge-disorder-induced Anderson

localization and conduction gap in graphene nanoribbons, Phys. Rev. B. 78 (2008) 161407.

doi:10.1103/PhysRevB.78.161407.

[7] D. Jena, T. Fang, Q. Zhang, H. Xing, Zener tunneling in semiconducting nanotube and

graphene nanoribbon p−n junctions, Appl. Phys. Lett. 93 (2008) 112106.

doi:10.1063/1.2983744.

[8] C. Stampfer, E. Schurtenberger, F. Molitor, J. Güttinger, T. Ihn, K. Ensslin, Tunable

Graphene Single Electron Transistor, Nano Lett. 8 (2008) 2378–2383.

doi:10.1021/nl801225h.

[9] G. Liang, N. Neophytou, D.E. Nikonov, M.S. Lundstrom, Performance Projections for

Ballistic Graphene Nanoribbon Field-Effect Transistors, IEEE Trans. Electron Devices. 54

(2007) 677–682. doi:10.1109/TED.2007.891872.

[10] J. Knoch, S. Mantl, J. Appenzeller, Impact of the dimensionality on the performance of

tunneling FETs: Bulk versus one-dimensional devices, Solid-State Electron. 51 (2007) 572–

578. doi:10.1016/j.sse.2007.02.001.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

25

[11] Q. Zhang, T. Fang, H. Xing, A. Seabaugh, D. Jena, Graphene Nanoribbon Tunnel

Transistors, IEEE Electron Device Lett. 29 (2008) 1344–1346.

doi:10.1109/LED.2008.2005650.

[12] Y. Yoon, S. Salahuddin, Inverse temperature dependence of subthreshold slope in graphene

nanoribbon tunneling transistors, Appl. Phys. Lett. 96 (2010) 013510.

doi:10.1063/1.3280379.

[13] N. Ma, D. Jena, Interband tunneling in two-dimensional crystal semiconductors, Appl.

Phys. Lett. 102 (2013) 132102. doi:10.1063/1.4799498.

[14] X. Liu, Electrostatic confinement of electrons in graphene nanoribbons, Phys. Rev. B. 80

(2009). doi:10.1103/PhysRevB.80.121407.

[15] R.V. Gorbachev, A.S. Mayorov, A.K. Savchenko, D.W. Horsell, F. Guinea, Conductance

of p-n-p Graphene Structures with “Air-Bridge” Top Gates, Nano Lett. 8 (2008) 1995–

1999. doi:10.1021/nl801059v.

[16] A. Laitinen, G.S. Paraoanu, M. Oksanen, M.F. Craciun, S. Russo, E. Sonin, P. Hakonen,

Contact doping, Klein tunneling, and asymmetry of shot noise in suspended graphene,

ArXiv150204330 Cond-Mat. (2015). http://arxiv.org/abs/1502.04330 (accessed February

22, 2016).

[17] J. Liu, S. Safavi-Naeini, D. Ban, Fabrication and measurement of graphene p #8211;n

junction with two top gates, Electron. Lett. 50 (2014) 1724–1726.

doi:10.1049/el.2014.3061.

[18] N. Stander, B. Huard, D. Goldhaber-Gordon, Evidence for Klein Tunneling in Graphene

$p\mathrm\text-n$ Junctions, Phys. Rev. Lett. 102 (2009) 026807.

doi:10.1103/PhysRevLett.102.026807.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

26

[19] T. Low, S. Hong, J. Appenzeller, S. Datta, M.S. Lundstrom, Conductance Asymmetry of

Graphene p-n Junction, IEEE Trans. Electron Devices. 56 (2009) 1292–1299.

doi:10.1109/TED.2009.2017646.

[20] S. Sutar, E.S. Comfort, J. Liu, T. Taniguchi, K. Watanabe, J.U. Lee, Angle-Dependent

Carrier Transmission in Graphene p–n Junctions, Nano Lett. 12 (2012) 4460–4464.

doi:10.1021/nl3011897.

[21] J. Baringhaus, A. Stöhr, S. Forti, U. Starke, C. Tegenkamp, Ballistic bipolar junctions in

chemically gated graphene ribbons, Sci. Rep. 5 (2015) 9955. doi:10.1038/srep09955.

[22] M.I. Katsnelson, K.S. Novoselov, A.K. Geim, Chiral tunnelling and the Klein paradox

in graphene, Nat. Phys. 2 (2006) 620–625. doi:10.1038/nphys384.

[23] B. Huard, J.A. Sulpizio, N. Stander, K. Todd, B. Yang, D. Goldhaber-Gordon, Transport

Measurements Across a Tunable Potential Barrier in Graphene, Phys. Rev. Lett. 98 (2007)

236803. doi:10.1103/PhysRevLett.98.236803.

[24] X. Xu-Guang, Z. Chao, X. Gong-Jie, C. Jun-Cheng, Electron tunneling in single layer

graphene with an energy gap, Chin. Phys. B. 20 (2011) 027201. doi:10.1088/1674-

1056/20/2/027201.

[25] M.R. Setare, D. Jahani, Electronic transmission through p–n and n–p–n junctions of

graphene, J. Phys. Condens. Matter. 22 (2010) 245503. doi:10.1088/0953-

8984/22/24/245503.

[26] J. Güttinger, F. Molitor, C. Stampfer, S. Schnez, A. Jacobsen, S. Dröscher, T. Ihn, K.

Ensslin, Transport through graphene quantum dots, Rep. Prog. Phys. 75 (2012) 126502.

doi:10.1088/0034-4885/75/12/126502.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

27

[27] P. Gallagher, K. Todd, D. Goldhaber-Gordon, Disorder-induced gap behavior in graphene

nanoribbons, Phys. Rev. B. 81 (2010) 115409. doi:10.1103/PhysRevB.81.115409.

[28] M.Y. Han, J.C. Brant, P. Kim, Electron Transport in Disordered Graphene Nanoribbons,

Phys. Rev. Lett. 104 (2010) 056801. doi:10.1103/PhysRevLett.104.056801.

[29] M. Manoharan, H. Mizuta, Edge irregularities in extremely down-scaled graphene

nanoribbon devices: role of channel width, Mater. Res. Express. 1 (2014) 045605.

doi:10.1088/2053-1591/1/4/045605.

[30] Y.-M. Lin, V. Perebeinos, Z. Chen, P. Avouris, Electrical observation of subband formation

in graphene nanoribbons, Phys. Rev. B. 78 (2008) 161409.

doi:10.1103/PhysRevB.78.161409.

[31] M.R. Müller, A. Gumprich, F. Schütte, K. Kallis, U. Künzelmann, S. Engels, C. Stampfer,

N. Wilck, J. Knoch, Buried triple-gate structures for advanced field-effect transistor

devices, Microelectron. Eng. 119 (2014) 95–99. doi:10.1016/j.mee.2014.02.001.

[32] A. Pirkle, J. Chan, A. Venugopal, D. Hinojos, C.W. Magnuson, S. McDonnell, L. Colombo,

E.M. Vogel, R.S. Ruoff, R.M. Wallace, The effect of chemical residues on the physical and

electrical properties of chemical vapor deposited graphene transferred to SiO2, Appl. Phys.

Lett. 99 (2011) 122108. doi:10.1063/1.3643444.

[33] Y.-C. Lin, C.-C. Lu, C.-H. Yeh, C. Jin, K. Suenaga, P.-W. Chiu, Graphene Annealing: How

Clean Can It Be?, Nano Lett. 12 (2012) 414–419. doi:10.1021/nl203733r.

[34] T. Iwasaki, M. Muruganathan, M.E. Schmidt, H. Mizuta, Partial hydrogenation induced

interaction in a graphene–SiO2 interface: irreversible modulation of device characteristics,

Nanoscale. 9 (2017) 1662–1669. doi:10.1039/C6NR08117G.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

28

[35] J. Sun, T. Iwasaki, M. Muruganathan, H. Mizuta, Lateral plasma etching enhanced on/off

ratio in graphene nanoribbon field-effect transistor, Appl. Phys. Lett. 106 (2015) 033509.

doi:10.1063/1.4906609.

[36] Silvaco Atlas—Device Simulation Framework, (n.d.).

http://www.silvaco.com/products/tcad/device_simulation/atlas/atlas.html (accessed

February 8, 2017).

[37] F. Molitor, C. Stampfer, J. Güttinger, A. Jacobsen, T. Ihn, K. Ensslin, Energy and transport

gaps in etched graphene nanoribbons, Semicond. Sci. Technol. 25 (2010) 034002.

doi:10.1088/0268-1242/25/3/034002.

[38] R. Nouchi, Contact resistance at planar metal contacts on bilayer graphene and effects of

molecular insertion layers, Nanotechnology. 28 (2017) 134003. doi:10.1088/1361-

6528/aa5ec2.

[39] R.J. Van Overstraeten, R.P. Mertens, Heavy doping effects in silicon, Solid-State Electron.

30 (1987) 1077–1087. doi:10.1016/0038-1101(87)90070-0.

[40] A. Schenk, A model for the field and temperature dependence of Shockley-Read-Hall

lifetimes in silicon, Solid-State Electron. 35 (1992) 1585–1596. doi:10.1016/0038-

1101(92)90184-E.

[41] M.J. Kerr, A. Cuevas, General parameterization of Auger recombination in crystalline

silicon, J. Appl. Phys. 91 (2002) 2473–2480. doi:10.1063/1.1432476.

[42] J. Knoch, S. Mantl, J. Appenzeller, Impact of the dimensionality on the performance of

tunneling FETs: Bulk versus one-dimensional devices, Solid-State Electron. 51 (2007) 572–

578. doi:10.1016/j.sse.2007.02.001.

MANUSCRIP

T

ACCEPTED

ACCEPTED MANUSCRIPT

29

[43] M. Luisier, G. Klimeck, Performance analysis of statistical samples of graphene nanoribbon

tunneling transistors with line edge roughness, Appl. Phys. Lett. 94 (2009) 223505.

doi:10.1063/1.3140505.

[44] Z. Chen, Y.-M. Lin, M.J. Rooks, P. Avouris, Graphene nano-ribbon electronics, Phys. E

Low-Dimens. Syst. Nanostructures. 40 (2007) 228–232. doi:10.1016/j.physe.2007.06.020.