Simplified Design of a Solid State Pulsed Power Modulator Based...

2112 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018

Simplified Design of a Solid State Pulsed PowerModulator Based on Power Cell Structure

Sung-Roc Jang , Member, IEEE, Chan-Hun Yu, and Hong-Je Ryoo , Member, IEEE

Abstract—This study presents a simplified design fora solid state pulsed power modulator (SSPPM) based ona power cell structure. Similar to the Marx generator, thepower cell structure has advantages such as reliability andmodularity. In addition, the proposed SSPPM includes a ca-pacitor charger that is simple and compact. The operatingprinciple of, and the design considerations taken for, theSSPPM are discussed from a practical viewpoint. Based ona reasonable approximation, simplified design equationsare developed for a capacitor charger and a high-voltagepulse-switching part, which are comprised of an LCC reso-nant converter and a power stage, respectively. Accordingly,detailed design procedures are proposed to develop theSSPPM with the following specifications: 40 kV, 20 A, 300 µs,200 Hz, and 50 kW. The experimental results verify the spec-ifications at the rated operating condition with an efficiencyof 92.4%, and also confirm reliable arc-protection perfor-mance. Finally, the proposed design methodology, whichutilizes simplified equations, can be used for designing anSSPPM based on the power cell structure for extensive ap-plications.

Index Terms—Pulse generation, pulse power supplies,resonant inverters.

I. INTRODUCTION

CURRENTLY, high-voltage pulsed power modulatorsbased on solid-state switches are widely used in pulsed-power applications that require a relatively high repetitionrate, high efficiency, low jitter, and long lifespan [1]–[19]. Inparticular, the solid state pulsed power modulator (SSPPM) thatuses an insulated gate bipolar transistor (IGBT) and/or metal-oxide-semiconductor field-effect transistor (MOSFET) has many

Manuscript received February 8, 2017; revised June 1, 2017, July 19,2017, and August 1, 2017; accepted August 8, 2017. Date of publica-tion August 25, 2017; date of current version December 15, 2017. Thiswork was supported in part by Korea Electrotechnology Research Insti-tute Primary Research Program through the National Research Councilof Science & Technology funded by the Ministry of Science, ICT, andFuture Planning (MSIP) (17-12-N0101-23) and in part by the NationalResearch Foundation of Korea (NRF) Grant funded by the Korea gov-ernment (MSIP) (NRF-2017R1A2B 3004855). (Corresponding author:Hong-Je Ryoo.)

S.-R. Jang is with the Electric Propulsion Research Center, KoreaElectrotechnology Research Institute, Changwon 51543, South Korea,and also with the University of Science and Technology, Daejeon 34113,South Korea (e-mail: [email protected]).

C.-H. Yu is with the Electric Propulsion Research Center, KoreaElectrotechnology Research Institute, Changwon 51543, South Korea(e-mail: [email protected]).

H.-J. Ryoo is with the School of Energy Systems Engineering, Chung-Ang University, Seoul 06974, South Korea (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2017.2745472

advantages owing to its fast switching characteristics. However,the voltage limitations of the semiconductor switches should beovercome to apply a high-voltage pulse. Accordingly, studieson SSPPMs have been reported, and various configurations,such as direct switching from a capacitor bank [1], voltageboost-up using a pulse transformer [2], vector inversion usinga coupled transformer [3], and modular structure based on theMarx generator [4], are introduced. Each method that generatesa high-voltage pulse has its own advantages [5].

In particular, the solid-state Marx modulator is widely usedto generate a controllable rectangular pulse, as it requires arelatively low charging voltage compared to the output pulsevoltage; moreover, a modular design is possible [6]–[9]. Hence,to utilize these advantages, a power cell structure is proposedto improve the performance of the SSPPM in terms of the effi-ciency and power density, even if it has restriction to increasemaximum output pulse voltage by only adding the power cells[10]–[18]. A distinctive characteristic of the power-cell-basedSSPPM is that it includes a capacitor charger for simultaneouslycharging multiple capacitors. Compared to the general schemeof the Marx modulator, which utilizes an external high-voltagedc source with a charging switch, the proposed circuit deliv-ers high-frequency ac power to each cell through a multiwind-ing transformer. Hence, the design is compact, and utilizes aminimum number of components. In addition, a soft-switching-based resonant inverter can be effectively designed by using theparasitic component of the multiwinding high-voltage trans-former [19]. Owing to these advantages, a power-cell-basedSSPPM is proposed for various types of pulsed-power appli-cations. However, to implement the SSPPM and achieve highperformance in terms of efficiency, reliability, and power den-sity, several technicalities need to be considered.

Based on the required specifications, this study presents asimplified guideline and equations to design and implement thepower-cell-based SSPPM. The detailed components include anLCC resonant inverter for high-efficiency capacitor charging, atransformer for delivering the charging power, a power cell forapplying the pulse, and a protection algorithm for reliable oper-ation against arc generations, and are discussed in the followingsections.

II. OPERATING PRINCIPLE AND DESIGN CONSIDERATIONS OFTHE SSPPM BASED ON THE POWER CELL STRUCTURE

Fig. 1 shows the overall scheme of the power-cell-basedSSPPM [10]–[14]. It mainly comprises a capacitor-charging partand a pulse-switching part. The capacitor-charging part includes

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JANG et al.: SIMPLIfiED DESIGN OF A SOLID STATE PULSED POWER MODULATOR BASED ON POWER CELL STRUCTURE 2113

Fig. 1. Overall scheme of the power-cell-based SSPPM.


a resonant inverter (S1–S4, Cs , Ls , Cp1–Cp48) and a powerloop (TR CIsolation , TR Stage) to generate and transfer high-frequency ac charging power, respectively. The power loop,which represents the secondary winding of the TR CIsolation ,couples the resonant inverter with the power stage simul-taneously. Each power stage includes a stage transformer(TR stage) and four power cells. Four secondary windings(n2 1–n2 4) in each power stage (e.g., Power Stage1) chargeeight storage capacitors (Cs1–Cs8) through rectifier diodes(Dr1–Dr8). The voltage-doubled rectifier circuit helps to reducethe required number of secondary windings by charging twostorage capacitors in each power cell. Compared to the generalcharging scheme of the Marx modulator, which uses a separatedhigh-voltage dc source with additional semiconductor devicesfor charging [6], the proposed configuration does not requireadditional components for charging the storage capacitors. Inaddition, the design is compact because the high-voltage insula-tion distance for designing the charger and the pulse-switchingpart is considered together. On the other hand, the power loopis required to ensure isolation between the primary resonant in-verter and secondary power cell. In other words, the insulationstrength of the power-loop cable should be greater than the max-imum pulse output voltage. Considering the required insulationstrength and the high-frequency rms current, a cable with a rel-atively large cross-sectional area is required for the power loop.To overcome this limitation of the power-cell-based SSPPM,two solutions are suggested in this study. The first is insertingan isolation transformer (TR CIsolation) between the resonantinverter and the power cell, which provides a second step iso-lation. In particular, the secondary winding of TR CIsolation(node PPL in Fig. 1) is intentionally connected to a storagecapacitor (power stage 3, power cell 3_4, node PC3_8), whichhas potential that is nearly half of the pulse output. This con-figuration, wherein the potential of the power loop is appliedas half of the pulse output, can halve the required insulationstrength of the power loop. Consequently, the thickness of theinsulation layer can be minimized. The second method involvesreducing the cross-sectional area of the conductor by decreas-ing the rms value of the resonant current. Hence, the resonanttank parameters should be designed to achieve less crest factor.Based on the trapezoidal approximation of the LCC resonantconverter, a detailed design guideline is discussed in the follow-ing section. Furthermore, the charging voltage of the storagecapacitors should be balanced to prevent over-voltage acrossthe switches (S1–S48) and allow simple control of the chargingvoltage. The voltage between the capacitors inside each powercell is balanced by using equalizing resistors (Re1–Re48). Thetertiary winding of each power stage transformer (n3) is specif-ically configured to compensate the voltage difference betweenthe power stages. The tertiary windings are connected in parallel(PB1“+” ∼ PB6“+”, PB1“–” ∼ PB6“–”), and the compensat-ing current flows between the stages. Consequently, the chargingvoltage between the storage capacitors is balanced. This helpsto control the pulse output voltage easily by sensing the voltageacross the two storage capacitors (Cs1 and Cs2) located at theground side.

Fig. 2. Waveforms of on/off pulse and gate-emitter voltage.

The pulse-switching part comprises a full-bridge inverter(S5–S8), a control loop (TR PIsolation , TR GD), and semicon-ductor switches (Sw1–Sw48, Sw1’–Sw48’) with their drive cir-cuits (GD for Sw1&1’–Sw48&48’). To control the pulse width(PW) and pulse repetition rate (PRR), the full-bridge inverterand control loop are designed to generate and transfer the on/offpulse, respectively. The pulse-control algorithm is known fromthe waveform of the on/off pulse (Von/off (t)) and the gate–emitter voltage (VGE(t)), as shown in Fig. 2. The gate drivecircuit (GD) for pulse-switching IGBTs (SW1∼SW48) is de-signed to provide and maintain VGE(t) when it receives the “on”pulse from control loop. In addition, VGE(t) starts to decreasewhen the “off” pulse is applied. Controlling VGE(t) by means ofthe bipolar short pulse allows for the size of TR PIsolation andTR_GDs to be reduced. Accordingly, the PW and PRR are con-trolled based on the time delay between the on and off pulses andthe time delay between the on and on pulses, respectively [10].The function of the pulse isolation transformer (TR PIsolation)is similar to that of the TR CIsolation . Therefore, a node referredto as PCL1“+” is connected to a storage capacitor that has al-most half of the potential of the output pulse (node PC3_8). Ahigh-voltage insulated cable couples the control loop with eightgate drivers (GDs) inside each power stage. To combine the con-trol loop between the stages, a parallel configuration (PCL1“+”∼ PCL6“+”, PCL1“–” ∼ PCL6“–”) is employed, because theinput voltage of the full-bridge inverter (Vdp) is limited. Withthe help of the simple gate-driving operating concept, an arc pro-tection algorithm is proposed using two additional off pulses,as shown in Fig. 2. When the pulse-output current sensor de-tects an arc, the on/off pulse controller generates the “off” pulseto pull down the gate voltage of the semiconductor switches.In addition, the second “off” pulse helps to confirm that theperformance of the arc protection circuit is reliable. Comparedto the arc protection circuit implemented in each GD circuit,the proposed protection circuit has advantages such as simplic-ity in design, because of its minimized number of components,and flexibility in choosing a suitable arc-current level [12]–[14].Furthermore, the proposed GD is designed to drive not only theswitches (Sw1–Sw48) that apply the pulse to the load, but alsothe switches (Sw1’–Sw48’) that pull down the output pulse.Compared to a conventional power cell structure comprising aswitch with a bypass diode [11]–[14], a controllable semicon-ductor called the bypass switch (Sw1’–Sw48’) is used in theproposed SSPPM instead of the bypass diode [10]. The antipar-allel diode of the bypass switch can serve as the bypass diode.In addition, the bypass switch helps to discharge the energy


Fig. 3. Node connection diagram for positive and negative pulse output.

stored in the parasitic capacitance and decrease the falling timewithout an additional pull-down resistor. The circuit shown inFig. 1 is intentionally drawn with node numbering, PP1_1–PP6_8, without connection because the proposed SSPPM facil-itates the configuration for both the positive and negative pulseoutputs.

As depicted in Fig. 3, the following are the node connectionsfor both polarities.

1) Node connection for the positive output pulseGround→ PP1 8, PP1 7 → PP1 6, PP1 5 →PP1 4, PP1 3 → PP1 2, PP1 1 →PP2 8, . . . , PP6 3 → PP6 2, PP6 1 → + Output.

2) Node connection for the negative output pulseGround→ PP1 1, PP1 2 → PP1 3, PP1 4 →PP1 5, PP1 6 → PP1 7, PP1 8 →PP2 1, . . . , PP6 6 → PP6 7, PP6 8 → −Output.

To change the output pulse polarity, it is necessary to changethe connection between the power stages but modifying theconnection in each power stage is not required.

III. DETAILED DESIGN OF SSPPM

Depending on the required specifications of the SSPPM sum-marized in Table I, the detailed design procedures are describedin this section.

A. Design of Capacitor Charger Based on TrapezoidalApproximation of LCC Resonant Converter

The simplified circuit of the capacitor-charging part, shownin Fig. 1, is illustrated in Fig. 4. The power stage trans-formers (TR_Stage1-TR_Stage6), parallel resonant capacitors(Cp1–Cp48), and storage capacitors (Cs1–Cs48) are equalized asTReq , Cpeq , and Cseq , respectively.

TABLE IDESIGN SPECIFICATIONS OF SSPPM

AC input voltage, Vac 380 ± 10%DC input of the capacitor charger, Vdc 513 V ± 10%DC input of the on/Off pulse generator, Vdf 310 V ± 10%Maximum pulse output voltage, Vpulse ,m ax 40 kVMaximum pulse output current, Ipulse ,m ax 20 AMaximum pulse width, PWm ax 300 μsMaximum pulse repetition rate, PRRm ax 200 ppsMaximum pulse voltage droop rate, VDroop ,rate Less than 2.5%Maximum charging power, Po ,m ax 50 kW

Fig. 4. Simplified circuit of capacitor charger based on LCC resonantconverter.

To understand the capacitor charger based on the LCC res-onant converter, the detailed design is explained by using anequivalent parallel resonant capacitor (Cp) placed on the pri-mary side of the transformer. It should be noted that the parallelresonant capacitors are practically implemented in parallel withthe rectifier diodes. Hence, the leakage inductance of the trans-formers (TR CIsolation and TR Stage) can be employed for theresonant inductor by using this configuration. Furthermore, theparallel resonant capacitor can be effectively used to balancethe voltage of the rectifier diodes when the diodes are stackedin series [22]. Considering the major operating waveforms andthe equivalent circuit shown in Fig. 5, the detailed design of thecapacitor charger is as follows.

1) Brief Explanation About Trapezoidal Approximationof the LCC Resonant Converter: The operating principle andanalysis of the LCC resonant converter is well known and thedetailed design procedures are introduced previously [20], [21].

This study focuses on the simplified design of the LCC res-onant converter to reduce the rms value of the resonant cur-rent based on the trapezoidal approximation. For a trapezoidalshape of the resonant current, the value of the series resonantcapacitor (Cs) should be considerably greater than Cp . In addi-tion, the voltage across the series resonant tank (Ls, Cs) duringMode2&4 (M2&M4) should be reduced to maintain the resonantcurrent as an almost constant value. Accordingly, the resonantcurrent increases abruptly and stabilizes during M1 and M2,respectively, owing to the above two design assumptions.


Fig. 5. Waveforms of resonant current, series and parallel resonantcapacitor voltage depending on operational mode.

2) Calculation of Transformer Turns Ratio: The turns ra-tio of the equivalent transformer, 1 : Neq , should be calcu-lated such that the voltage across the series resonant tank dur-ing M2 and M4 is minimum. Accordingly, the turns ratio ofTReq is calculated by equating Vdc and Vpri , as in (1). Aninput voltage of 513 V is considered in the calculation be-cause the resonant current value at t2 increases and decreasesslightly, depending on the high and low input voltage conditions,respectively

Neq =VsecVpri

=Vpulse,max

Vdc· 12≈ 40. (1)

3) Determining the Peak Value of the Resonant Current(ILs,Peak) and Frequency Ratio (fs,m in/ fop ): The requiredvalue of the peak resonant current (ILs,peak) that provides amaximum charging power (Po,max) of 50 kW should be de-termined to calculate the resonant tank parameters. Based onthe ampere–second area (charge Q) of the resonant current,the design equations for the LCC resonant converter are intro-duced [20]. Based on the proposed equations, the relationshipbetween Po,max and ILs,peak is simplified by assuming a trape-zoidal shape of the resonant current, as in (2). This equationhelps to design the LCC resonant converter efficiently, despitehaving been derived by neglecting the effects of Q1’ and Q2’,shown in Fig. 5. It should be noted that this equation is validonly in a limited switching-frequency range, because the switch-ing frequency should be less than 1.6 times the parallel resonantfrequency (fop : resonant frequency calculated using Ls and Cp )

Po = Vdc × ILs,peak ×(

1−58· fsfop

). (2)

Fig. 6. Graph of the current ratio (IL s,p eak /Idc ) and light load power(calculated output power at three times of fs,m in ) depending on thefrequency ratio (fs,m in /fop ).

By equating (2) and the dc input power (Vdc · Idc), the currentratio of the required ILs,peak to the ideal Idc can be drawn withdifferent frequency ratios of the minimum switching frequency(fs,min) to the parallel resonant frequency (fop).

The solid line in Fig. 6 indicates that a low value of the fre-quency ratio (fs,min/fop) helps to reduce the required ILs,peakfor the rated operation. This is because the high parallel reso-nant frequency reduces the circulating energy during M1 andM4. On the other hand, the circulating energy is closely relatedto the light load operation of the LCC resonant converter. Thedashed line in Fig. 3 indicates the power ratio of the outputpower at three times fs,min (Po,3fs,min) to the maximum outputpower at the minimum switching frequency (Po,max). The resultclearly shows the difficulty in operating at the light-load condi-tion based on the increase in the frequency ratio. This tradeoffbetween the required ILs,peak and the light-load operation char-acteristic need to be considered based on the type of application.For example, a capacitor charger that requires charging with-out regulation can be designed with a low frequency ratio. Incontrast, if the dc power supply and/or the capacitor chargerfor a SSPPM require output voltage regulation, the operatingswitching-frequency range for light load operation should beconsidered. To design the charger for the SSPPM, a frequencyratio of 0.5 is selected such that ILs,peak is less than 1.5 timesIdc , and Po,3fs,min is less than 10% of the rated power.

4) Determining the Maximum Voltage Across the SeriesResonant Capacitor (VCs ,p eak ): To validate the trapezoidal ap-proximation, the capacitance of the series resonant capacitor(Cs) should be much greater than that of the parallel resonantcapacitor (Cp). Accordingly, the abrupt increase in the resonantcurrent during M1 and the flat waveform of the resonant currentduring M2 can be achieved using the parallel resonant frequency(fop) and the series resonant frequency (fos : resonant frequencycalculated using Ls and Cs), respectively. This relationship im-plies that the lower the maximum charging voltage (VCs,peak)of Cs is, the lower rms value of the resonant current (with thetrapezoidal waveform) will be. Hence, the value, VCs,peak , is


determined to be a quarter of the input voltage ((1/4) · Vdc).This is because Vdc represents the maximum charging voltageof Cp and a reasonable capacitance of Cs can be selected.

5) Calculation of the Design Parameters for CapacitorCharger: To calculate the resonant tank parameters, the mini-mum switching frequency (fs,min) should be determined basedon the power losses in S1–S4. To generate 50 kW of the max-imum charging power from a single phase, full-bridge LCCresonant inverter, considerable conduction loss on the inverterswitches is inevitable even if the proposed design provides lessrms value of the resonant current with the trapezoidal waveform.In addition, the proposed LCC resonant converter operation hasturn-off switching loss that is proportional to the switching fre-quency. To achieve high-efficiency, a minimum switching fre-quency of 30 kHz is selected based on the characteristic of powerMOSFET (CAS300M12BM2, CREE) that is used for S1–S4. Ac-cordingly, the range of switching frequencies is determined from30–180 kHz for regulating the output from 100% to 1% loadconditions, respectively. Depending on an fs,min of 30 kHz,the resonant tank parameters are calculated by using (3)–(6).From the operating waveforms of the proposed LCC resonantconverter shown in Fig. 5, it is clear that the value of ILs,peakis determined during M1. Based on the equivalent circuit forM1 in Fig. 5, ILs,peak can be calculated from the sum of volt-age across Ls (as numerator term: Vdc − VC p(t0) − VC s(t0))and the characteristic impedance of resonant tank (as denom-inator term) [20]. The value of two resonant capacitor volt-ages (VC p(t0), VC s(t0)) is already determined, as depicted inFig. 5. One approximation used to derive a simplified (3) is thatthe value of Cs does not significantly affect the resonance, andit can be ignored when calculating the value of the characteristicimpedance (Cs � Cp). Therefore, the characteristic impedanceof the parallel resonant tank (Zop) is calculated as

Zop =

√LsCp

=2 · Vdc + VC s,peak

ILs,peak≈ 7.94 [Ω]. (3)

The parallel resonant frequency is previously found to be60 kHz after determining the frequency ratio (fs,min/fop) andfs,min . From fop and Zop , the resonant inductance (Ls) and theparallel resonant capacitance (Cp) are calculated by using thefollowing:

Ls =Zop

2πfop≈ 21.06 [μH] (4)

Cp =Ls

Zop2 ≈ 0.334 [μH]. (5)

As shown in Fig. 5, the voltage waveform of Cs is a lin-ear function of time owing to the almost constant value ofthe resonant current, and the value of Cs is calculated as (6).Based on the analysis of the LCC resonant converter intro-duced in [20], the equation for tM2 can be simplified basedon the trapezoidal approximation that ignores Q1’ and Q2’ inFig. 5. The amp–second area (Q1, Q2, Q3) of the resonant cur-rent shown in Fig. 5 determines the power from input (Pin =Vdc×(Q1 + Q2 − Q3) × 2fs) and the power transferred bytransformer (PTReq = Vdc×(Q2 + Q3) × 2fs). From the as-

sumption of 100% efficiency, the value of these two power termsshould be the same. Accordingly, the relationship between Q2and Q3 can be determined as Q1 = 2 · Q3 that represents tM3is the half of tM1 (= Top/4). Therefore, the expression for tM2can be derived as

Cs =ILs,peak × tM22 · VC s,peak

=ILs,peak ×

(Ts2

− 38 Top)

2 · VC s,peak ≈ 5.91 [μF]. (6)

The values of the lossless snubber capacitors (C1–C4), whichcan be used to reduce the turn-off switching loss of the switches(S1–S4), are selected by considering the switching-frequencyrange and operating-load condition. To obtain wide controllableoutput voltages and load ranges, a MOSFET output capacitance of2 nF is used as a lossless snubber instead of additional capacitors.The equivalent storage capacitor (Cseq) can serve as a filtercapacitor from a capacitor-charger viewpoint, as shown in Fig. 4.On the other hand, the value of Cseq should be determined usingthe required voltage droop. The calculation steps are discussedin the following section.

B. Design of Pulse-Switching Part Including Power Stage

Based on the specifications related to the output pulse sum-marized in Table I, the step-by-step design procedure for thepulse-switching part is as follows.

1) Determining the Number of Power Stages (Nstage ):The number of power stages (Nstage) largely depends on thecore for the TR_stage. Because the power delivered using thetransformer is limited, a multistage structure is required, asshown in Fig. 1. Hence, the core should be selected to determineNstage . First, the required size of the core can be determinedby calculating the required area product (AP) of the core asfollows [23]:

AP = AW · AE =(

Po,maxK × ΔB × fs,min

)4/3 ≈ 1140 [cm4].(7)

To transfer the maximum charging power (Po,max), the AP iscalculated to be approximately 1140 cm4 . The values of K andΔB are 0.017 (full bridge) and 0.5 T (considering the core loss ofthe ferrite PC40 material), respectively. From the commercial-ized large-size ferrite core, a PQ 107 × 87 × 70 core with anAP of 220 cm4 is selected, and six power stages (Nstage = 6)are configured to satisfy the required AP of 1140 cm4 . Moreover,the multistage structure helps to design the winding structure byconsidering insulation between the windings.

2) Calculating the Primary Winding Turns of TR_Stage(N1 ): As shown in Fig. 1, the power loop, which representsthe primary windings of the TR_stage, simultaneously couplesthe cores from TR_Stage1 to TR_Stage6. Based on Faraday’slaw, the required N1 for achieving the desired ΔB (0.5 T) canbe calculated using Nstage · AE of the cross-sectional area ofthe magnetic core, where AE (14.28 cm

2) is the effective cross-sectional area of the PQ 107 × 87 × 70 core. Accordingly, two


turns of the power loop (N1 = 2) are calculated as

N1 =Vdc

ΔB × Nstage × AE × 2 · fs,min ≈ 2 [turns]. (8)

3) Determining the Number of Power Cells (Ncell ): Thenumber of power cells (Ncell) depends on the charging voltageof each cell; moreover, it is closely associated with the volt-age ratings of the semiconductor switches (Sw1–Sw48, Sw1’–Sw48’). In particular, the dynamic characteristic of Sw1–Sw48largely determines the rising time of the output pulse and thelosses of pulse-switching part. Generally, the lower the ratingsof the semiconductor switches, the better the dynamic per-formance. In addition, other considerations for selecting thesemiconductor switch are the pulsed current capability and/orthe short-circuit withstand time, which are important param-eters for reliable operation against the arc. According to theaforementioned considerations for choosing the switches, theFGL40N120AND IGBT (Fairchild 1200 V, 40 A, TO-264) isselected for the proposed SSPPM. It provides a pulsed currentcapability of 160 A and a short-circuit withstand time of 10 μs.By considering a voltage margin of 20% compared to the ratedvoltage (VCES), Ncell is determined using (9). Equation (9) ismultiplied by half because two storage capacitors are chargedin each power cell

Ncell ≥ Vpulse,max0.8 · VCES ·12≈ 21. (9)

From (9), it can be found that Ncell should be greater than21. In addition, the value should be multiples of Nstage for asymmetrical configuration between the power stages. Finally,Ncell is determined to be 24.

4) Calculating the Secondary Winding Turns ofTR_Stage (N2 ): As shown in Fig. 1, N2 is the sum of thefour secondary windings (n2 1–n2 4), and it can be easily cal-culated by multiplying the number of primary turns, N1 , andthe equivalent transformer ratio, Neq . Thus, the number of turnsfor each secondary winding in the power stage is calculated as

n2 1–n2 4 =N1 × Neq × Nstage

Ncell≈ 20. (10)

5) Determining the Value of Storage Capacitors (Cs 1 –Cs 48 ): In addition to reducing the ripple in the charging volt-age in terms of the capacitor charger, the main function ofthe storage capacitor is to maintain the output pulse voltagewith less voltage droop. Similar to the Marx generator, thestorage capacitors are configured in series to apply the high-voltage pulse. In other words, the capacitance that is calculatedfrom the series connection of all the storage capacitors deter-mines the maximum voltage droop rate (VDroop,rate), depend-ing on the values of the maximum pulse current (Ipulse,max)and PW (PWmax). When all the storage capacitors are con-nected in series, the value of equivalent capacitance canbe calculated as Cs1/2 · Ncell (Cs1 = Cs2 = Cs3 = · · · =Cs48). Therefore, the value of each storage capacitance shouldbe greater than the calculated capacitance from the desiredvoltage droop (ΔVDroop = Vpulse,max × VDroop,rate). Hence,the required capacitance of the storage capacitors can be calcu-

lated by using (11), which is determined to be 390μF

Cs1–Cs48 ≥ Ipulse,max × PWmaxVpulse,max × VDroop,rate

× 2 · Ncell ≈ 288 [μF]. (11)6) Calculating the Capacitance of the Practical Paral-

lel Resonant Capacitors (Cp1 –Cp48 ) from Cp : The equivalentparallel resonant capacitor (Cp) is employed to design the reso-nant inverter. However, for practical implementation, the parallelresonant capacitor is better implemented on the secondary sideof the transformer. This is because the leakage inductance canbe used for the series resonant inductor. Hence, the parallel reso-nant capacitor is implemented using Cp1–Cp48 , as shown in Fig.1. Moreover, the capacitors Cp1–Cp48 are not connected in par-allel with the secondary winding; however, they are connectedin parallel with the rectifier diodes (Dr1–Dr48). This is becauseeach diode in the voltage-doubled rectifier is practically imple-mented with two in series and is required to balance the voltagebetween the series stacked diodes. By connecting the parallelresonant capacitor in parallel with each diode, the voltage canbe balanced without additional components. By employing thecalculated Cp , the equivalent parallel resonant capacitor (Cpeq),shown in Fig. 4, can be determined by dividing 2 · N 2eq [22]. Byusing (12), the capacitance of each parallel resonant capacitor(Cp1–Cp48) is found to be 2.5 nF

Cp1–Cp48 =Cp

2 · Neq2× Ncell ≈ 2.5 [nF]. (12)

7) Determining the Value of Equalizing Resistors(Re1 –Re48 ): To determine the resistance of the equalizing resis-tors, the voltage between the storage capacitors in each powerstage should be balanced. Although a more accurate balancingis possible using equalizing resistors with lower resistance, thepower loss of the resistors should be considered. By employing(13), which is used to calculate the total power loss of the resis-tors, the resistance of each resistor Re1–Re48 is determined tobe 540 kΩ for a power loss of 0.125% compared to Po,max

PRe,loss =Vpulse,max

2

2 · Ncell × Re [W]. (13)

8) Design of Arc Protection Circuit: As part of the re-search discussed in this study, a previous study related to the GDcircuit is introduced and includes a detailed operation principle[10]. Based on the proposed gate-driving concept that employsthe “on” and “off” pulses for charging and discharging the gatevoltage (VGE), the arc protection algorithm is proposed usingan additional “off” pulse. The controller used for generating thegate pulses in S5–S8 is designed to provide two additional “off”pulses when the arc is detected. This method is more reliablethan increasing the PW of the off pulse. The design prevents thesaturation of the TR_GD without increasing the cross section ofthe core. In addition, the arc protection level can be adjusted, un-like the conventional method that employs a protection circuitfor all the drive circuits. Hence, a simple configuration andreliable operation are achieved by using the proposed arc-protection algorithm.


9) Determining the Tertiary Winding Turns of TR_Stage(N3 ): Ahn et al. [11] show the details of the tertiary windingwith detection and protection methodologies against voltage un-balancing. For the tertiary winding, the number of turns is nota critical design factor, despite the fact that a more accuratebalancing can be achieved between the stages by using a largernumber of turns. This is because the compensating current willflow independently, regardless of the number of turns, and thevalue of the current is expected to be relatively small. However,the important design consideration is that the tertiary windingshould be wound to allow better coupling with the secondarywinding, in order to reflect the voltage accurately. In addition,the parallel configuration of the windings in each stage trans-former is better than the winding structure introduced in [11].This is because the effect of the leakage inductance can be re-duced. Another consideration is that the insulation strength ofthe tertiary winding cable should be the same as that of the cablefor the power loop. Based on the aforementioned considerations,one turn of the tertiary winding is determined because of the re-stricted area for winding, and the detailed winding structure isdescribed in Section IV.

IV. EXPERIMENTAL RESULTS OF DEVELOPED SSPPM

Fig. 7 shows the overall structure and an image of the devel-oped SSPPM. The top view of the developed SSPPM showsthe detailed design structure of power stage six, includingTR_Stage6, TR_GD, Cp , and Dr . The structure can be cor-related with the circuit shown in Fig. 1. To implement the powerloop, three high-voltage insulated wires are used in parallelto secure 20 kV of insulation and allow the rated rms of theresonant current. The secondary windings are wound on a spe-cially designed bobbin, and two sections are arranged for eachsecondary winding. The bobbin structure provides effective in-sulation between the secondary windings. One turn of a tertiarywinding is inserted at the center of TR_Stage6, as shown inFig. 7. The distance between the windings is equal owing tothe structural design of TR_Stage, and the charging voltage isbalanced owing to the full winding area, along with the reduc-tion in the difference between leakage inductances. One turnof the control loop is designed to penetrate the toroidal cores(TR_GD), which deliver the on/off pulse to each GD circuit,which drive the switches (Sw & Sw’) simultaneously.

Dr48 and Cp48 in Fig. 7 show that the diodes (Dr1–Dr48)and the parallel resonant capacitors (Cp1–Cp48) are practicallyimplemented as two stacked diodes, and the voltage betweenthe two stacked diodes is balanced using the parallel resonantcapacitor. To satisfy the capacitance and voltage rating of thestorage capacitor, four capacitors are installed: two in series andtwo in parallel. The same can be observed in Cs41 . Utilizing theaforementioned structure of each power stage, six power stagesare configured as shown in the side view of Fig. 7.

The power loop couples the stage transformers with the res-onant inverter, which is located at the bottom of the devel-oped SSPPM. Except for the power stages, the bottom case isdesigned to include all the parts, such as two full-bridge invert-

Fig. 7. Overall structure and image of the developed SSPPM.

Fig. 8. Experimental waveforms at rated operation.

ers, two isolation transformers (TR CIsolation , TR PIsolation),an input rectifier with a filter, and a controller.

To verify the design described in this study, the developedSSPPM, shown in Fig. 7, was tested using a resistor load of 2 kΩ.The maximum pulse voltage (40 kV) and current (20 A) at themaximum PRR (200 Hz) are measured as shown in Fig. 8. Witha PW of 300μs, a voltage droop rate below 2.5% is confirmedfor a pulse current of 20 A. In the operating condition, shown


Fig. 9. Measured efficiency versus average output power.

Fig. 10. Experimental results of normal and arc protection operatingconditions. (a) Waveforms at normal operation. (b) Waveforms at arcprotection operation.

in Fig. 8, the average output power is measured to be 49.57 kW.Accordingly, a maximum efficiency of 92.4% was determinedby using the measured input power of 53.66 kW obtained fromthe ac input (Vac in Fig. 1).

Fig. 9 shows the curve of the measured efficiency versusaverage output power. The measured efficiency was calculatedby employing not only the pulse-switching part, but also thecapacitor charger.

In contrast to the direct switching method that requires RDCsnubber [24], the proposed SSPPM removes the passive com-ponents for voltage balancing and features high efficiency asdepicted in Fig. 9. Compared to the other solid-state Marx cir-cuits [25]–[26] and the pulsed modulator using a pulse trans-former [27], 92.4% of the maximum efficiency that was achievedbased on the proposed design is relatively high. However, itshould be noted that a direct efficiency comparison is not rea-sonable because of the different input and output specifications.The performance of the proposed arc-protection algorithm isexperimentally verified as shown in Fig. 10. During the normal

operating condition at 40 kV, as shown in Fig. 7(a), an exter-nal arc is intentionally generated by placing the ground wire atthe high-voltage output. The arc protection waveforms, shownin Fig. 7(b), show that the pulse current gradually increases to350 A for a duration of 2 μs after generating the arc, and subse-quently, decreases after applying the “off” pulse. Accordingly,the semiconductor switches are protected against the arc. Evenif the switches (Sw1–Sw48) are expected to turn off after thefirst “off” pulse, the operation is reliable owing to the second“off” pulse.

V. CONCLUSION

This study described a simplified design of the SSPPM basedon a power cell structure. Based on the operating principle andpractical design considerations, the sequential design proce-dures using simple equations were explained and employed todesign the SSPPM with the following specifications: 40 kV,20 A, 300 μs, 200 Hz, and 50 kW. Finally, the experimental re-sults verify the proposed design guideline and demonstrate thehigh performance of the developed SSPPM in terms of high effi-ciency and high reliability. In the future, the developed SSPPMwill be applied to radar applications that require a voltage droopbelow 0.5%. To satisfy the critical droop specification, an activedroop compensator was being developed to be combined withthe proposed SSPPM to achieve high power density withoutincreasing the capacitance of the storage capacitors.

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Sung-Roc Jang (M’17) was born in Daegu,South Korea, in 1983. He received the B.S.degree in electrical engineering from Kyung-pook National University, Daegu, South Korea,in 2008, and the M.S. and Ph.D. degrees in elec-trical engineering from the University of Scienceand Technology, Deajeon, South Korea, in 2011.

Since 2011, he has been a Senior Re-searcher with the Electric Propulsion ResearchCenter, Korea Electrotechnology Research In-stitute, Changwon, South Korea. In 2015, he be-

came an Assistant Professor in the Department of Energy ConversionTechnology, University of Science and Technology, Deajeon. His currentresearch interests include high-voltage resonant converters and solid-state pulsed power modulators and their industrial applications.

Dr. Jang received the Young Scientist Award at 3rd Euro-Asian PulsedPower Conference in 2010, and the IEEE Nuclear Plasma Science So-ciety Best Student Paper Award at the IEEE International Pulsed PowerConference in 2011.

Chan-Hun Yu was born in Daegu, South Ko-rea, in 1988. He received the B.S. degree inelectrical engineering from Kyungpook NationalUniversity, Daegu, South Korea, in 2013 and theM.S. degree in electrical engineering from KoreaAdvanced Institute of Science and Technology,Daejeon, South Korea, in 2015.

Since 2015, he has been with Korea Elec-trotechnology Research Institute, Changwon,South Korea, as a Researcher in ElectricPropulsion Research Center. His current re-

search interests include dc/dc converters, high voltage pulse modulator,and capacitor charger.

Hong-Je Ryoo (M’17) received the B.S., M.S.,and Ph.D. degrees in electrical engineering fromSungKyunkwan University, Seoul, South Korea,in 1991, 1995, and 2001, respectively.

From 2004 to 2005, he was a Visiting Scholarfor his Postdoctoral study with WEMPEC, Uni-versity of Wisconsin–Madison, Madison, WI,USA. During 1996–2015, he was with KoreaElectrotechnology Research Institute, Chang-won, South Korea, where he joined the Elec-tric Propulsion Research Division, as a Principal

Research Engineer, in 2008, and was a Leader of the Pulsed PowerWorld Class Laboratory. He was a Professor with the Department ofEnergy Conversion Technology, University of Science & Technology,Deajeon, South Korea. In 2015, he joined the School of Energy SystemsEngineering, Chung-Ang University, Seoul, where he is currently an As-sociate Professor. His current research interests include pulsed-powersystems and their applications, as well as high-power and high-voltageconversions.

Dr. Ryoo is a member of Korean Institute of Power Electronics andthe Korean Institute of Electrical Engineers.

http://dx.doi.org/10.1109/TPEL.2014.2352651http://dx.doi.org/10.1109/TPS.2011.2181426http://dx.doi.org/10.1109/TPS.2012.2186592http://dx.doi.org/10.1109/TDEI.2011.5976122http://dx.doi.org/10.1109/TDEI.2013.6571412http://dx.doi.org/10.1109/TDEI.2009.5211857http://dx.doi.org/10.1109/TDEI.2015.004959http://dx.doi.org/10.1109/TDEI.2013.6571437http://dx.doi.org/10.1109/TPS.2013.2277879http://dx.doi.org/10.1109/TPEL.2007.909243http://dx.doi.org/10.1109/TIE.2012.2227897http://dx.doi.org/10.1109/TIE.2016.2586021http://dx.doi.org/10.1109/TDEI.2009.5211851http://dx.doi.org/10.1109/PPC.2011.6191665

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