Single Stage Amplifier
• Common Source Amplifier• Source Follower• Common Drain
Common Source Amplifier
• Resistive Load• Diode Connected• Current Source Load• Triode Load• Source Degeneration
CS with Resistive Load
CS with Resistive Load
W/L=35.6 um/0.6um
Small Input Signal
Amplitude of input: 2 mV (peak to peak)Amplitude of output: 19.5 (peak to peak)Av=9.75
Small Signal Operation
Calculation of Small Signal Gain
(Valid only for device in saturation region)
Small Signal Model
1. small signal analysis2. the intuitive approach
Numerical Calculation
• Small Signal Gain:– gm=2 mS
– ro=1/gds=22.288 Kohms
– RD=6 Kohms
– AV=-gm(roRD/(ro+RD))=-9.454
What if the magnitude of the input signal is increased?
Distortion is observed when Vin swings high.
Triode Region (1)Triode Region
Reduction of transconductancein the triode region
Triode Region (2)
Disadvantage of resistively loaded CS:The DC level of Vout is tied to the AV.An increase of RD will increase AV, but at the price of pushingthe transistor closer into the triode region.
Diode Connected Load
• Common Source– Diode Connected Load– NFET Implementation– PFET Implementation
Diode Connected Load
Impedance:
(Body Effect ignored.)
Useful when tightly controlled resistors are not available, or physically not realizable.
Diode Connected Load With Body Effect
Example
M1: W/L=4.62 um/0.6umBias Current: 100 uAgm2=8 mSgds2=35.43 uSgmbs2=100.6 uSRX=1,068 Ohms
CS Stage with Diode Connected Load
Not sensitive of bias current, e.g. gm
Better linearity.
Diode Connected Load (NFET)
W/L_To=35.6 um/0.6um; W/L_T1=4.62 um/0.6um
Amplitude of input: 2 mV (peak to peak)Amplitude of output: 4.447 mV (peak to peak)Av=2.22
Design Issue
• If the bias current is fixed and the dc Vout (VGS) is fixed, then (W/L) of the load is fixed.
• It maybe difficult to increase Av.
Diode Connected PFET with CS
Plot
Amplitude of input: 2 mV (peak to peak)Amplitude of output: 15.24 mV (peak to peak)Av=7.62
Gain Calculation
M1: W/L=6.00 um/0.6umBias Current: 100 uACurrent source: 75 uAgm=2 mSgm2=200 uSgds2=4.69 uSgds=44.8 uS
Av=-8.013
CS Stage with Current Source Load
ro2 depends on L and ID of a transistor.|VDS2,min=VGS-Vth2| can be reduced by increasing the width of M2.
Downside: the DC output voltage is not well-defined.
Spice Example
Amplitude of input: 2 mV (peak to peak)Amplitude of output: 62.92 mV (peak to peak)Av=-31.44
Sensitivty
Even a slight deviation in the gate voltage of PFET is enoughto change the output voltage signficantly.E.g. Sensitivity of output voltage around 0.6 V.
Calculation:
W/L for T2: 24.06um/0.6umro1=22.288 Kohm
ro2=53.20 Kohm
gm=2 mS
Av=-31.41 Ideal Vout=0.6 VVth2=-0.269Vod=-0.213Vb=717.64 mV
CS Stage with Triode Load
Disadvantage: Sensitivity to a precise Vb.Advantage: Vout, max=VDD
CS Stage with Source Degeneration
• Intuition• Small signal gain• Output resistance
Intuition
Vin↑, ID ↑, VS ↑Δvin is dropped across RS, thus leading to a smoother variation of ID.
Small Signal Gain
If gmRS>>1, AV is approximately RD/RS
ДID=ДVin/RS
Effective Gm with Non-negligible body effect
Gain By Inspection
Interpretation: The resistance at the drainDivided by the resistance in the source path
Determination of Gain by Inspection Example
Output Resistance
Homework: Derive the output resistance using the smallequivalent circuit
A More Intuitive Approach
Analysis
Norton Equivalent Circuit
Gain of a Degenerated Current Source
Conductance with body effectOutput Resistance